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[/] [System09/] [rev_86/] [rtl/] [VHDL/] [timer.vhd] - Blame information for rev 158

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1 19 dilbert57
--===========================================================================----
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--
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--  S Y N T H E Z I A B L E    timer - 9 bit timer
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--
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--  www.OpenCores.Org - September 2003
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--  This core adheres to the GNU public license  
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--
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-- File name      : timer.vhd
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--
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-- Purpose        : 8 bit timer module for System 09
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--
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-- Dependencies   : ieee.Std_Logic_1164
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--                  ieee.std_logic_unsigned
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--
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-- Uses           : None
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--
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-- Author         : John E. Kent      
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--                  dilbert57@opencores.org      
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--
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--===========================================================================----
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--
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-- Revision History:
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--===========================================================================--
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--
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-- Version 0.1 - 6 Sept 2002 - John Kent
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-- converted to a single timer 
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-- made syncronous with system clock
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--
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-- Version 1.0 - 6 Sept 2003 - John Kent
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-- Realeased to open Cores
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-- changed Clock Edge
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--
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-- Version 2.0 - 5th February 2008 - John Kent
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-- removed Timer inputs and outputs
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-- made into a simple 8 bit interrupt down counter
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--
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--===========================================================================
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--
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-- Register Addressing:
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-- addr=0 rw=1 down count
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-- addr=0 rw=0 preset count
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-- addr=1 rw=1 status
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-- addr=1 rw=0 control
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--
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-- Control register
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-- b0 = counter enable
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-- b7 = interrupt enable
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--
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-- Status register
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-- b7 = interrupt flag
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--
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-- Operation:
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-- Write count to counter register
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-- Enable counter by setting bit 0 of the control register
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-- enable interrupts by setting bit 7 of the control register
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-- Counter will count down to zero
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-- when it reaches zero the terminal flag is set
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-- if the interrupt is enabled an interrupt is generated
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-- The interrupt may be disabled by writing a 0 to bit 7 of the control register
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-- or by loading a new down count into the counter register.
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-- 
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity timer is
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        port (
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         clk        : in  std_logic;
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    rst        : in  std_logic;
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    cs         : in  std_logic;
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    rw         : in  std_logic;
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    addr       : in  std_logic;
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    data_in    : in  std_logic_vector(7 downto 0);
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         data_out   : out std_logic_vector(7 downto 0);
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         irq        : out std_logic
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  );
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end;
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architecture rtl of timer is
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signal timer_ctrl  : std_logic_vector(7 downto 0);
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signal timer_stat  : std_logic_vector(7 downto 0);
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signal timer_count : std_logic_vector(7 downto 0);
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signal timer_term  : std_logic; -- Timer terminal count
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--
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-- control/status register bits
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--
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constant T_enab   : integer := 0; -- 0=disable, 1=enabled
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constant T_irq    : integer := 7; -- 0=disabled, 1-enabled
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begin
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--------------------------------
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--
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-- write control registers
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-- doesn't do anything yet
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--
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--------------------------------
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timer_write : process( clk, rst, cs, rw, addr, data_in,
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                       timer_ctrl, timer_term, timer_count )
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begin
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  if rst = '1' then
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           timer_count <= "00000000";
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                timer_ctrl  <= "00000000";
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                timer_term  <= '0';
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  elsif clk'event and clk = '0' then
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    if cs = '1' and rw = '0' then
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           if addr='0' then
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                  timer_count <= data_in;
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                  timer_term  <= '0';
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           else
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                  timer_ctrl <= data_in;
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                end if;
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         else
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           if (timer_ctrl(T_enab) = '1') then
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                  if (timer_count = "00000000" ) then
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                    timer_term <= '1';
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        else
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          timer_count <= timer_count - 1;
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                  end if;
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                end if;
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    end if;
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  end if;
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end process;
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--
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-- timer data output mux
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--
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timer_read : process( addr, timer_count, timer_stat )
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begin
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  if addr='0' then
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    data_out <= timer_count;
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  else
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    data_out <= timer_stat;
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  end if;
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end process;
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--
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-- read timer strobe to reset interrupts
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--
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timer_interrupt : process( timer_term, timer_ctrl )
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begin
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         irq <= timer_term and timer_ctrl( T_irq );
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end process;
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  --
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  -- timer status register
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  --
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  timer_status : process( timer_ctrl, timer_term )
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  begin
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    timer_stat(6 downto 0) <= timer_ctrl(6 downto 0);
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    timer_stat(T_irq) <= timer_term;
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  end process;
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end rtl;
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