Subversion Repositories System09

--===========================================================================----

--

--  T E S T B E N C H    System09_tb - SOC Testbench.

--

--  www.OpenCores.Org - September 2003

--  This core adheres to the GNU public license  

--

-- File name      : System09_tb.vhd

--

-- Purpose        : Test Bench for system 09

--                  Top level file for 6809 compatible system on a chip

--                  Designed with Xilinx XC2S300e Spartan 2+ FPGA.

--                  Implemented With BurchED B5-X300 FPGA board,

--                  B3-SRAM module, B5-CF module and B3-FPGA-CPU-IO module

--

-- Dependencies   : ieee.Std_Logic_1164

--                  ieee.std_logic_unsigned

--                  ieee.std_logic_arith

--                  ieee.numeric_std

--

-- Uses           : boot_rom (sbug.vhd)       Monitor ROM

--                  cpu09    (cpu09.vhd)      CPU core

--                  dat_ram  (datram.vhd)     Dynamic Address Translation

--                  miniuart (minitUART2.vhd) ACIA / MiniUART

--                           (rxunit2.vhd)

--                           (tx_unit2.vhd)

--                           (clkunit2.vhd)

--                  timer    (timer.vhd)      Timer module

-- 

-- Author         : John E. Kent

--                  dilbert57@opencores.org      

--

--===========================================================================----

--

-- Revision History:

--===========================================================================--

--

-- Version 1.0 

-- John Kent - 6 Sep 2003 - Initial release to Open Cores

--

--===========================================================================--

library ieee;

   use ieee.std_logic_1164.all;

   use IEEE.STD_LOGIC_ARITH.ALL;

   use IEEE.STD_LOGIC_UNSIGNED.ALL;

   use ieee.numeric_std.all;

entity System09 is

  port(

    LED         : out std_logic;  -- Diagnostic LED Flasher

    -- Memory Interface signals

    ram_csn     : out Std_Logic;

    ram_wrln    : out Std_Logic;

    ram_wrun    : out Std_Logic;

    ram_addr    : out Std_Logic_Vector(16 downto 0);

    ram_data    : inout Std_Logic_Vector(15 downto 0);

         -- Stuff on the peripheral board

--  aux_clock   : in  Std_Logic;  -- FPGA-CPU-IO clock

         -- PS/2 Mouse interface

--       mouse_clock : in  Std_Logic;

--       mouse_data  : in  Std_Logic;

         -- Uart Interface

    rxbit       : in  Std_Logic;

         txbit       : out Std_Logic;

    rts_n       : out Std_Logic;

    cts_n       : in  Std_Logic;

         -- CRTC output signals

--         v_drive     : out Std_Logic;

--    h_drive     : out Std_Logic;

--    blue_lo     : out std_logic;

--    blue_hi     : out std_logic;

--    green_lo    : out std_logic;

--    green_hi    : out std_logic;

--    red_lo      : out std_logic;

--    red_hi      : out std_logic;

--         buzzer      : out std_logic;

-- Compact Flash

    cf_rst_n     : out std_logic;

         cf_cs0_n     : out std_logic;

         cf_cs1_n     : out std_logic;

    cf_rd_n      : out std_logic;

    cf_wr_n      : out std_logic;

         cf_cs16_n    : out std_logic;

    cf_a         : out std_logic_vector(2 downto 0);

    cf_d         : inout std_logic_vector(15 downto 0);

-- Test Pins

         test_alu    : out std_logic_vector(15 downto 0);

         test_cc     : out std_logic_vector(7 downto 0)

         );

end;

-------------------------------------------------------------------------------

-- Architecture for memio Controller Unit

-------------------------------------------------------------------------------

architecture my_computer of System09 is

  -----------------------------------------------------------------------------

  -- Signals

  -----------------------------------------------------------------------------

  signal SysClk    : std_logic;

  signal reset_n   : std_logic;

  -- BOOT ROM

  signal rom_data_out  : Std_Logic_Vector(7 downto 0);

  -- UART Interface signals

  signal uart_data_out : Std_Logic_Vector(7 downto 0);

  signal uart_cs       : Std_Logic;

  signal uart_irq      : Std_Logic;

  -- timer

  signal timer_data_out : std_logic_vector(7 downto 0);

  signal timer_cs    : std_logic;

  signal timer_irq   : std_logic;

  signal timer_out   : std_logic;

  -- compact flash port

  signal cf_data_out : std_logic_vector(7 downto 0);

  signal cf_cs       : std_logic;

  signal cf_rd       : std_logic;

  signal cf_wr       : std_logic;

  -- RAM

  signal ram_cs      : std_logic; -- memory chip select

  signal ram_wrl     : std_logic; -- memory write lower

  signal ram_wru     : std_logic; -- memory write upper

  signal ram_data_out    : std_logic_vector(7 downto 0);

  -- CPU Interface signals

  signal cpu_reset   : Std_Logic;

  signal cpu_clk     : Std_Logic;

  signal cpu_rw      : std_logic;

  signal cpu_vma     : std_logic;

  signal cpu_halt    : std_logic;

  signal cpu_hold    : std_logic;

  signal cpu_firq    : std_logic;

  signal cpu_irq     : std_logic;

  signal cpu_nmi     : std_logic;

  signal cpu_addr    : std_logic_vector(15 downto 0);

  signal cpu_data_in : std_logic_vector(7 downto 0);

  signal cpu_data_out: std_logic_vector(7 downto 0);

  -- Dynamic address translation

  signal dat_cs      : std_logic;

  signal dat_addr    : std_logic_vector(7 downto 0);

  -- Boot ROM Map switch

--  signal map_cs      : Std_Logic;

--  signal map_sw      : Std_Logic;

  -- synchronous RAM

  signal xram_data_out : std_logic_vector(7 downto 0);

  signal xram_cs       : std_logic;

  -- Flashing Led test signals

  signal countL      : std_logic_vector(23 downto 0);

-----------------------------------------------------------------

--

-- CPU09 CPU core

--

-----------------------------------------------------------------

component cpu09

  port (

         clk:        in std_logic;

    rst:      in        std_logic;

    rw:      out        std_logic;              -- Asynchronous memory interface

    vma:             out        std_logic;

    address:  out       std_logic_vector(15 downto 0);

    data_in:  in        std_logic_vector(7 downto 0);

         data_out: out std_logic_vector(7 downto 0);

         halt:     in  std_logic;

         hold:     in  std_logic;

         irq:      in  std_logic;

         nmi:      in  std_logic;

         firq:     in  std_logic;

         test_alu: out std_logic_vector(15 downto 0);

         test_cc:  out std_logic_vector(7 downto 0)

  );

end component;

-----------------------------------------------------------------

--

-- Open Cores Mini UART

--

-----------------------------------------------------------------

component miniUART

  port (

     SysClk   : in  Std_Logic;  -- System Clock

     rst      : in  Std_Logic;  -- Reset input

     cs       : in  Std_Logic;

     rw       : in  Std_Logic;

     RxD      : in  Std_Logic;

     TxD      : out Std_Logic;

     CTS_n    : in  Std_Logic;

     RTS_n    : out Std_Logic;

     Irq      : out Std_logic;

     Addr     : in  Std_Logic;

     DataIn   : in  Std_Logic_Vector(7 downto 0); -- 

     DataOut  : out Std_Logic_Vector(7 downto 0)); -- 

end component;

----------------------------------------

--

-- Timer module

--

----------------------------------------

component timer

  port (

     clk       : in std_logic;

          rst       : in std_logic;

          cs        : in std_logic;

          rw        : in std_logic;

          addr      : in std_logic;

          data_in   : in std_logic_vector(7 downto 0);

          data_out  : out std_logic_vector(7 downto 0);

          irq       : out std_logic;

     timer_in  : in std_logic;

          timer_out : out std_logic

          );

end component;

component boot_rom

  port (

    addr  : in  Std_Logic_Vector(10 downto 0);  -- 2K byte boot rom

         data  : out Std_Logic_Vector(7 downto 0));

end component;

--component sbug_rom

--    Port (

--       MEMclk   : in std_logic;

--       MEMaddr  : in std_logic_vector (10 downto 0);

--       MEMrdata : out std_logic_vector (7 downto 0)

--    );

--end component sbug_rom;

component dat_ram

  port (

    clk:      in  std_logic;

         rst:      in  std_logic;

         cs:       in  std_logic;

         rw:       in  std_logic;

         addr_lo:  in  std_logic_vector(3 downto 0);

         addr_hi:  in  std_logic_vector(3 downto 0);

    data_in:  in  std_logic_vector(7 downto 0);

         data_out: out std_logic_vector(7 downto 0)

         );

end component;

-- component block_ram

--    Port (

--       MEMclk   : in  std_logic;

--               MEMcs    : in  std_logic;

--               MEMrw    : in  std_logic;

--       MEMaddr  : in  std_logic_vector (10 downto 0);

--       MEMrdata : out std_logic_vector (7 downto 0);

--       MEMwdata : in  std_logic_vector (7 downto 0)

--    );

--end component;

-- component BUFG 

--  port (

--     i: in std_logic;

--        o: out std_logic

--  );

-- end component;

begin

  -----------------------------------------------------------------------------

  -- Instantiation of internal components

  -----------------------------------------------------------------------------

my_cpu : cpu09  port map (

         clk         => SysClk,

    rst       => cpu_reset,

    rw       => cpu_rw,

    vma       => cpu_vma,

    address   => cpu_addr(15 downto 0),

    data_in   => cpu_data_in,

         data_out  => cpu_data_out,

         halt      => cpu_halt,

         hold      => cpu_hold,

         irq       => cpu_irq,

         nmi       => cpu_nmi,

         firq      => cpu_firq,

         test_alu  => test_alu,

         test_cc   => test_cc

  );

my_uart  : miniUART port map (

    SysClk    => SysClk,

         rst       => cpu_reset,

    cs        => uart_cs,

         rw        => cpu_rw,

         RxD       => rxbit,

         TxD       => txbit,

         CTS_n     => cts_n,

         RTS_n     => rts_n,

    Irq       => uart_irq,

    Addr      => cpu_addr(0),

         Datain    => cpu_data_out,

         DataOut   => uart_data_out

         );

my_timer  : timer port map (

    clk       => SysClk,

         rst       => cpu_reset,

    cs        => timer_cs,

         rw        => cpu_rw,

    addr      => cpu_addr(0),

         data_in   => cpu_data_out,

         data_out  => timer_data_out,

    irq       => timer_irq,

         timer_in  => CountL(5),

         timer_out => timer_out

    );

my_rom : boot_rom port map (

         addr       => cpu_addr(10 downto 0),

    data       => rom_data_out

         );

--my_rom : sbug_rom port map (

--       MEMclk   => SysClk,

--       MEMaddr  => cpu_addr(10 downto 0),

--       MEMrdata => rom_data_out

--    );

my_dat : dat_ram port map (

    clk        => SysClk,

         rst        => cpu_reset,

         cs         => dat_cs,

         rw         => cpu_rw,

         addr_hi    => cpu_addr(15 downto 12),

         addr_lo    => cpu_addr(3 downto 0),

    data_in    => cpu_data_out,

         data_out   => dat_addr(7 downto 0)

         );

--my_ram : block_ram port map (

--       MEMclk   => SysClk,

--       MEMcs    => xram_cs,

--               MEMrw    => cpu_rw,

--       MEMaddr  => cpu_addr(10 downto 0),

--       MEMwdata => cpu_data_out,

--       MEMrdata => xram_data_out

--    );

--  clk_buffer : BUFG port map(

--    i => e_clk,

--         o => cpu_clk

--    );         

----------------------------------------------------------------------

--

-- Process to decode memory map

--

----------------------------------------------------------------------

mem_decode: process(

                     cpu_addr, cpu_vma,

--                                                 map_cs, map_sw,

                                              rom_data_out, ram_data_out,

--                                                 xram_data_out,

                                              cf_data_out,

                                                   timer_data_out,

                                                   uart_data_out )

begin

    --

         -- Memory map

         --

    case cpu_addr(15 downto 11) is

                when "11111" => -- $F800 - $FFFF

                   cpu_data_in <= rom_data_out;       -- read ROM

                        dat_cs    <= cpu_vma;              -- write DAT

                        ram_cs    <= '0';

                        uart_cs   <= '0';

                        cf_cs     <= '0';

                        timer_cs  <= '0';

--                      xram_cs   <= '0';

--                      map_cs    <= '0';

--              when "11101" => -- $E800 - $EFFF

--              when "11111" => -- $F800 - $FFFF

--                 if map_sw = '1' then

--                   cpu_data_in <= rom_data_out;     -- read ROM

--                        dat_cs    <= '0';                -- disable write to DAT

--                        ram_cs    <= cpu_vma;            -- enable write to RAM

--                      else

--                        cpu_data_in <= ram_data_out;     -- read RAM

--                        dat_cs    <= cpu_vma;            -- enable write DAT

--                        ram_cs    <= cpu_vma and cpu_rw; -- disable write to RAM

--                      end if;

--                      uart_cs   <= '0';

--                      cf_cs     <= '0';

--                      timer_cs  <= '0';

--                      map_cs    <= '0';

--      when "11110" => -- $F000 - $F7FF

--            cpu_data_in <= xram_data_out;

--                      dat_cs    <= '0';

--                      ram_cs    <= '0';

--                      uart_cs   <= '0';

--                      cf_cs     <= '0';

--                      xram_cs   <= cpu_vma;

                when "11100" => -- $E000 - $E7FF

                   dat_cs    <= '0';

                        ram_cs    <= '0';

--                      xram_cs   <= '0';

                   case cpu_addr(7 downto 4) is

                        when "0000" => -- $E000

                     cpu_data_in <= uart_data_out;

                          uart_cs     <= cpu_vma;

                          cf_cs       <= '0';

                          timer_cs    <= '0';

--                        map_cs      <= '0';

                        when "0001" => -- $E010

           cpu_data_in <= cf_data_out;

                          uart_cs     <= '0';

           cf_cs       <= cpu_vma;

                          timer_cs    <= '0';

--                        map_cs      <= '0';

                        when "0010" => -- $E020

           cpu_data_in <= timer_data_out;

                          uart_cs     <= '0';

                          cf_cs       <= '0';

           timer_cs    <= cpu_vma;

                          map_cs      <= '0';

                        when "0011" => -- $E030

           cpu_data_in <= "00000000";

                          uart_cs     <= '0';

                          cf_cs       <= '0';

           timer_cs    <= '0';

--                        map_cs      <= cpu_vma;

                        when others => -- $E040 to $E7FF

           cpu_data_in <= "00000000";

                          uart_cs     <= '0';

                          cf_cs       <= '0';

                          timer_cs    <= '0';

--                        map_cs      <= '0';

                   end case;

                when others =>

                  cpu_data_in <= ram_data_out;

                  ram_cs      <= cpu_vma;

--                xram_cs     <= '0';

                  dat_cs      <= '0';

                  uart_cs     <= '0';

                  cf_cs       <= '0';

                  timer_cs    <= '0';

--                map_cs      <= '0';

         end case;

end process;

--

-- B3-SRAM Control

-- Processes to read and write memory based on bus signals

--

ram_process: process( SysClk, Reset_n,

                      cpu_addr, cpu_rw, cpu_data_out,

                                               dat_addr,

                      ram_cs, ram_wrl, ram_wru, ram_data )

begin

    ram_csn <= not( ram_cs and Reset_n );

         ram_wrl  <= (not dat_addr(5)) and (not cpu_rw) and (not SysClk);

         ram_wrln <= not (ram_wrl);

    ram_wru  <= dat_addr(5) and (not cpu_rw) and (not SysClk);

         ram_wrun <= not (ram_wru);

         ram_addr(16 downto 12) <= dat_addr(4 downto 0);

         ram_addr(11 downto 0) <= cpu_addr(11 downto 0);

    if ram_wrl = '1' then

                ram_data(7 downto 0) <= cpu_data_out;

         else

      ram_data(7 downto 0)  <= "ZZZZZZZZ";

         end if;

         if ram_wru = '1' then

                ram_data(15 downto 8) <= cpu_data_out;

         else

      ram_data(15 downto 8)  <= "ZZZZZZZZ";

    end if;

         if dat_addr(5) = '1' then

      ram_data_out <= ram_data(15 downto 8);

         else

      ram_data_out <= ram_data(7 downto 0);

    end if;

end process;

--

-- Compact Flash Control

--

compact_flash: process( Reset_n,

                 cpu_addr, cpu_rw,  cpu_data_out,

                                          cf_cs, cf_rd, cf_wr, cf_d )

begin

         cf_rst_n  <= Reset_n;

         cf_cs0_n  <= not( cf_cs ) or cpu_addr(3);

         cf_cs1_n  <= not( cf_cs and cpu_addr(3));

         cf_cs16_n <= '1';

         cf_wr     <= cf_cs and (not cpu_rw);

         cf_rd     <= cf_cs and cpu_rw;

         cf_wr_n   <= not cf_wr;

         cf_rd_n   <= not cf_rd;

         cf_a      <= cpu_addr(2 downto 0);

         if cf_wr = '1' then

           cf_d(7 downto 0) <= cpu_data_out;

         else

           cf_d(7 downto 0) <= "ZZZZZZZZ";

         end if;

         cf_data_out <= cf_d(7 downto 0);

         cf_d(15 downto 8) <= "ZZZZZZZZ";

end process;

--

-- ROM Map switch

-- The Map switch output is initially set

-- On a Write to the Map Switch port, clear the Map Switch

-- and map the RAM in place of the boot ROM.

--

--map_proc : process( SysClk, Reset_n, map_cs, cpu_rw )

--begin

--  if SysClk'event and SysClk = '1' then

--    if Reset_n = '0' then

--          map_sw <= '1';

--       else

--          if (map_cs = '1') and (cpu_rw = '0') then

--                 map_sw <= '0';

--               else

--                 map_sw <= map_sw;

--               end if;

--       end if;

--  end if;

--end process;

--

-- Interrupts and other bus control signals

--

interrupts : process( Reset_n, uart_irq

--                    ,timer_irq

                                                         )

begin

         cpu_reset <= not Reset_n; -- CPU reset is active high

    cpu_irq  <= uart_irq;

         cpu_nmi  <= timer_irq;

--       cpu_nmi  <= '0';

         cpu_firq <= '0';

         cpu_halt <= '0';

         cpu_hold <= '0';

end process;

  --

  -- flash led to indicate code is working

  --

  increment: process (SysClk, CountL )

  begin

    if(SysClk'event and SysClk = '1') then

      countL <= countL + 1;

    end if;

         LED <= countL(21);

  end process;

-- *** Test Bench - User Defined Section ***

tb : PROCESS

        variable count : integer;

   BEGIN

        SysClk <= '0';

        Reset_n <= '0';

                for count in 0 to 512 loop

                        SysClk <= '0';

                        if count = 0 then

                                Reset_n <= '0';

                        elsif count = 1 then

                                Reset_n <= '1';

                        end if;

                        wait for 100 ns;

                        SysClk <= '1';

                        wait for 100 ns;

                end loop;

      wait; -- will wait forever

   END PROCESS;

end; --===================== End of architecture =======================--