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dilbert57 |
#### UCF file created by Project Navigator
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#
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NET "reset_n" LOC = "p57" ;
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NET "sysclk" LOC = "p77" ;
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#
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# For B5-Compact-Flash:
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# Connector A
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#
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#NET "pin2" LOC = "P3" ; #J1-2
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#NET "pin3" LOC = "P4" ; #J1-3
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#NET "cf_intrq" LOC = "P5" ; #J1-4
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NET "cf_wr_n" LOC = "P6" ; #J1-5
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NET "cf_rd_n" LOC = "P7" ; #J1-6
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NET "cf_cs1_n" LOC = "P8" ; #J1-7
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NET "cf_d<15>" LOC = "P9" ; #J1-8
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NET "cf_d<14>" LOC = "P10" ; #J1-9
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NET "cf_d<13>" LOC = "P11" ; #J1-10
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NET "cf_d<12>" LOC = "P15" ; #J1-11
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NET "cf_d<11>" LOC = "P16" ; #J1-12
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#NET "cf_present" LOC = "P17" ; #J1-13
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NET "cf_d<3>" LOC = "P18" ; #J1-14
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NET "cf_d<4>" LOC = "P20" ; #J1-15
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NET "cf_d<5>" LOC = "P21" ; #J1-16
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NET "cf_d<6>" LOC = "P22" ; #J1-17
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NET "cf_d<7>" LOC = "P23" ; #J1-18
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NET "cf_cs0_n" LOC = "P24" ; #J1-19
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#
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# For B5-Compact-Flash:
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# Connector B
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#
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NET "cf_a<2>" LOC = "P33" ; #J2-6
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NET "cf_a<1>" LOC = "P34" ; #J2-7
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NET "cf_a<0>" LOC = "P35" ; #J2-8
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NET "cf_d<0>" LOC = "P36" ; #J2-9
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NET "cf_d<1>" LOC = "P40" ; #J2-10
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NET "cf_d<2>" LOC = "P41" ; #J2-11
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NET "cf_cs16_n" LOC = "P42" ; #J2-12
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NET "cf_d<10>" LOC = "P43" ; #J2-13
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NET "cf_d<9>" LOC = "P44" ; #J2-14
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NET "cf_d<8>" LOC = "P45" ; #J2-15
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#NET "cf_pdiag" LOC = "P46" ; #J2-16
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#NET "cf_dase" LOC = "P47" ; #J2-17
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#NET "cf_iordy" LOC = "P48" ; #J2-18
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NET "cf_rst_n" LOC = "P49" ; #J2-19
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#
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# I/O Port
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# Connector C
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#
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#NET "porta<0>" LOC = "p55" ; #pin 3
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#NET "porta<1>" LOC = "p56" ; #pin 4
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#NET "porta<2>" LOC = "p58" ; #pin 5
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#NET "porta<3>" LOC = "p59" ; #pin 6
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#NET "porta<4>" LOC = "p60" ; #pin 7
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#NET "porta<5>" LOC = "p61" ; #pin 8
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#NET "porta<6>" LOC = "p62" ; #pin 8
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#NET "porta<7>" LOC = "p63" ; #pin 10
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#NET "portb<0>" LOC = "p64" ; #pin 11
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#NET "portb<1>" LOC = "p68" ; #pin 12
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#NET "portb<2>" LOC = "p69" ; #pin 13
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#NET "portb<3>" LOC = "p70" ; #pin 14
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#NET "portb<4>" LOC = "p71" ; #pin 15
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#NET "portb<5>" LOC = "p73" ; #pin 16
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#NET "portb<6>" LOC = "p74" ; #pin 17
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#NET "portb<7>" LOC = "p75" ; #pin 18
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#NET "timer_out" LOC = "p81" ; #pin 19
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#
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# For B3-FPGA-CPU-IO
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# Connector D
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#
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#NET "aux_clock" LOC = "p80" ; #pin 2
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#NET "buzzer" LOC = "p82" ; #pin 3
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NET "led" LOC = "p82" ; #pin 3
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#NET "mouse_clock" LOC = "p83" ; #pin 4
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#NET "mouse_data" LOC = "p84" ; #pin 5
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NET "cts_n" LOC = "p86" ; #pin 6
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NET "rts_n" LOC = "p87" ; #pin 7
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NET "txbit" LOC = "p88" ; #pin 8
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NET "rxbit" LOC = "p89" ; #pin 9
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#NET "kb_clock" LOC = "p93" ; #pin 10
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#NET "kb_data" LOC = "p94" ; #pin 11
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#NET "v_drive" LOC = "p95" ; #pin 12
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#NET "h_drive" LOC = "p96" ; #pin 13
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#NET "blue_lo" LOC = "p97" ; #pin 14
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#NET "blue_hi" LOC = "p98" ; #pin 15
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#NET "green_lo" LOC = "p99" ; #pin 16
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#NET "green_hi" LOC = "p100"; #pin 17
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#NET "red_lo" LOC = "p101"; #pin 18
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#NET "red_hi" LOC = "p102"; #pin 19
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#
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# For modified B3-SRAM
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# Connector E
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#
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NET "ram_addr<0>" LOC = "p108"; #J1.2
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NET "ram_addr<1>" LOC = "p109"; #J1.3
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NET "ram_addr<2>" LOC = "p110"; #J1.4
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NET "ram_addr<3>" LOC = "p111"; #J1.5
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NET "ram_addr<4>" LOC = "p112"; #J1.6
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NET "ram_addr<5>" LOC = "p113"; #J1.7
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NET "ram_addr<6>" LOC = "p114"; #J1.8
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NET "ram_addr<7>" LOC = "p115"; #J1.9
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NET "ram_csn" LOC = "p116"; #J1.10
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NET "ram_addr<8>" LOC = "p120"; #J1.11
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NET "ram_addr<9>" LOC = "p121"; #J1.12
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NET "ram_addr<10>" LOC = "p122"; #J1.13
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NET "ram_addr<11>" LOC = "p123"; #J1.14
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NET "ram_addr<12>" LOC = "p125"; #J1.15
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NET "ram_addr<13>" LOC = "p126"; #J1.16
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NET "ram_addr<14>" LOC = "p127"; #J1.17
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NET "ram_addr<15>" LOC = "p129"; #J1.18
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NET "ram_addr<16>" LOC = "p132"; #J1.19
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#
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# For modified B3-SRAM
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# Connector F
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#
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NET "ram_data<0>" LOC = "p133"; #J2.2
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NET "ram_data<1>" LOC = "p134"; #J2.3
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NET "ram_data<2>" LOC = "p135"; #J2.4
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NET "ram_data<3>" LOC = "p136"; #J2.5
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NET "ram_data<4>" LOC = "p138"; #J2.6
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NET "ram_data<5>" LOC = "p139"; #J2.7
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NET "ram_data<6>" LOC = "p140"; #J2.8
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NET "ram_data<7>" LOC = "p141"; #J2.9
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NET "ram_data<8>" LOC = "p145"; #J2.10
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NET "ram_data<9>" LOC = "p146"; #J2.11
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NET "ram_data<10>" LOC = "p147"; #J2.12
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NET "ram_data<11>" LOC = "p148"; #J2.13
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NET "ram_data<12>" LOC = "p149"; #J2.14
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NET "ram_data<13>" LOC = "p150"; #J2.15
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NET "ram_data<14>" LOC = "p151"; #J2.16
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NET "ram_data<15>" LOC = "p152"; #J2.17
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NET "ram_wrun" LOC = "p153"; #J2.18
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NET "ram_wrln" LOC = "p154"; #J2.19
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#
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# Connector G
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#
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#NET "pin2" LOC = "p182"; #pin 2 (clk input)
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NET "test_alu<0>" LOC = "p160"; #pin 3
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NET "test_alu<1>" LOC = "p161"; #pin 4
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NET "test_alu<2>" LOC = "p162"; #pin 5
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NET "test_alu<3>" LOC = "p163"; #pin 6
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NET "test_alu<4>" LOC = "p164"; #pin 7
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NET "test_alu<5>" LOC = "p165"; #pin 8
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NET "test_alu<6>" LOC = "p166"; #pin 9
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NET "test_alu<7>" LOC = "p167"; #pin 10
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NET "test_alu<8>" LOC = "p168"; #pin 11
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NET "test_alu<9>" LOC = "p169"; #pin 12
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NET "test_alu<10>" LOC = "p173"; #pin 13
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NET "test_alu<11>" LOC = "p174"; #pin 14
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NET "test_alu<12>" LOC = "p175"; #pin 15
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NET "test_alu<13>" LOC = "p176"; #pin 16
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NET "test_alu<14>" LOC = "p178"; #pin 17
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NET "test_alu<15>" LOC = "p179"; #pin 18
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#NET "pin19" LOC = "p180"; #pin 19
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#
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# Connector H
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#
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#NET "pin2" LOC = "p185"; #pin 2 (clk input)
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#NET "pin3" LOC = "p181"; #pin 3
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#NET "uart_csn" LOC = "p187"; #pin 4
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#NET "test_rw" LOC = "p188"; #pin 5
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#NET "test_d0" LOC = "p189"; #pin 6
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#NET "test_d1" LOC = "p191"; #pin 7
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#NET "pin8" LOC = "p192"; #pin 8
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#NET "pin9" LOC = "p193"; #pin 9
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#NET "pin10" LOC = "p194"; #pin 10
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NET "test_cc<0>" LOC = "p198"; #pin 11
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NET "test_cc<1>" LOC = "p199"; #pin 12
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NET "test_cc<2>" LOC = "p200"; #pin 13
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NET "test_cc<3>" LOC = "p201"; #pin 14
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NET "test_cc<4>" LOC = "p202"; #pin 15
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NET "test_cc<5>" LOC = "p203"; #pin 16
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NET "test_cc<6>" LOC = "p204"; #pin 17
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NET "test_cc<7>" LOC = "p205"; #pin 18
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#NET "pin19" LOC = "p206"; #pin 19
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#
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# Timing Groups
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#
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INST "ram_addr<0>" TNM = "ram_addr";
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INST "ram_addr<1>" TNM = "ram_addr";
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INST "ram_addr<2>" TNM = "ram_addr";
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INST "ram_addr<3>" TNM = "ram_addr";
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INST "ram_addr<4>" TNM = "ram_addr";
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INST "ram_addr<5>" TNM = "ram_addr";
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INST "ram_addr<6>" TNM = "ram_addr";
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INST "ram_addr<7>" TNM = "ram_addr";
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INST "ram_addr<8>" TNM = "ram_addr";
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INST "ram_addr<9>" TNM = "ram_addr";
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INST "ram_addr<10>" TNM = "ram_addr";
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INST "ram_addr<11>" TNM = "ram_addr";
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INST "ram_addr<12>" TNM = "ram_addr";
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INST "ram_addr<13>" TNM = "ram_addr";
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INST "ram_addr<14>" TNM = "ram_addr";
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INST "ram_addr<15>" TNM = "ram_addr";
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INST "ram_addr<16>" TNM = "ram_addr";
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INST "ram_data<0>" TNM = "ram_data";
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INST "ram_data<1>" TNM = "ram_data";
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INST "ram_data<2>" TNM = "ram_data";
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INST "ram_data<3>" TNM = "ram_data";
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INST "ram_data<4>" TNM = "ram_data";
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INST "ram_data<5>" TNM = "ram_data";
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| 201 |
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INST "ram_data<6>" TNM = "ram_data";
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| 202 |
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INST "ram_data<7>" TNM = "ram_data";
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| 203 |
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INST "ram_data<8>" TNM = "ram_data";
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INST "ram_data<9>" TNM = "ram_data";
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| 205 |
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INST "ram_data<10>" TNM = "ram_data";
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INST "ram_data<11>" TNM = "ram_data";
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INST "ram_data<12>" TNM = "ram_data";
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| 208 |
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INST "ram_data<13>" TNM = "ram_data";
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| 209 |
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INST "ram_data<14>" TNM = "ram_data";
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| 210 |
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INST "ram_data<15>" TNM = "ram_data";
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| 211 |
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INST "ram_wrln" TNM = "ram_wr";
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INST "ram_wrun" TNM = "ram_wr";
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| 213 |
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INST "ram_csn" TNM = "ram_cs";
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| 214 |
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INST "test_alu<0>" TNM = "test_alu";
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INST "test_alu<1>" TNM = "test_alu";
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INST "test_alu<2>" TNM = "test_alu";
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INST "test_alu<3>" TNM = "test_alu";
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INST "test_alu<4>" TNM = "test_alu";
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| 219 |
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INST "test_alu<5>" TNM = "test_alu";
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| 220 |
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INST "test_alu<6>" TNM = "test_alu";
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| 221 |
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INST "test_alu<7>" TNM = "test_alu";
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| 222 |
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INST "test_alu<8>" TNM = "test_alu";
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| 223 |
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INST "test_alu<9>" TNM = "test_alu";
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| 224 |
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INST "test_alu<10>" TNM = "test_alu";
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| 225 |
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INST "test_alu<11>" TNM = "test_alu";
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| 226 |
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INST "test_alu<12>" TNM = "test_alu";
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| 227 |
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INST "test_alu<13>" TNM = "test_alu";
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| 228 |
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INST "test_alu<14>" TNM = "test_alu";
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| 229 |
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INST "test_alu<15>" TNM = "test_alu";
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| 230 |
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INST "test_cc<0>" TNM = "test_cc";
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| 231 |
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INST "test_cc<1>" TNM = "test_cc";
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| 232 |
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INST "test_cc<2>" TNM = "test_cc";
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| 233 |
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INST "test_cc<3>" TNM = "test_cc";
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| 234 |
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INST "test_cc<4>" TNM = "test_cc";
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| 235 |
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INST "test_cc<5>" TNM = "test_cc";
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| 236 |
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INST "test_cc<6>" TNM = "test_cc";
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| 237 |
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INST "test_cc<7>" TNM = "test_cc";
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| 238 |
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#
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# Timing Constraints
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| 240 |
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#
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TIMEGRP "ram_cs" OFFSET = OUT 40 ns AFTER "sysclk";
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| 242 |
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TIMEGRP "ram_wr" OFFSET = OUT 40 ns AFTER "sysclk";
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| 243 |
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TIMEGRP "ram_addr" OFFSET = OUT 40 ns AFTER "sysclk";
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| 244 |
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TIMEGRP "ram_data" OFFSET = OUT 40 ns AFTER "sysclk";
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| 245 |
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TIMEGRP "ram_data" OFFSET = IN 15 ns BEFORE "sysclk";
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| 246 |
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TIMEGRP "test_alu" OFFSET = OUT 90 ns AFTER "sysclk";
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| 247 |
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TIMEGRP "test_cc" OFFSET = OUT 95 ns AFTER "sysclk";
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NET "sysclk" TNM_NET = "sysclk";
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TIMESPEC "TS_sysclk" = PERIOD "sysclk" 100 ns LOW 50 %;
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#
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| 251 |
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# Fast I/O Pins
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#
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NET "ram_addr<0>" FAST;
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| 254 |
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NET "ram_addr<1>" FAST;
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| 255 |
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NET "ram_addr<2>" FAST;
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| 256 |
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NET "ram_addr<3>" FAST;
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| 257 |
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NET "ram_addr<4>" FAST;
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NET "ram_addr<5>" FAST;
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| 259 |
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NET "ram_addr<6>" FAST;
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NET "ram_addr<7>" FAST;
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NET "ram_addr<8>" FAST;
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NET "ram_addr<9>" FAST;
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|
|
NET "ram_addr<10>" FAST;
|
| 264 |
|
|
NET "ram_addr<11>" FAST;
|
| 265 |
|
|
NET "ram_addr<12>" FAST;
|
| 266 |
|
|
NET "ram_addr<13>" FAST;
|
| 267 |
|
|
NET "ram_addr<14>" FAST;
|
| 268 |
|
|
NET "ram_addr<15>" FAST;
|
| 269 |
|
|
NET "ram_addr<16>" FAST;
|
| 270 |
|
|
NET "ram_csn" FAST;
|
| 271 |
|
|
NET "ram_data<0>" FAST;
|
| 272 |
|
|
NET "ram_data<1>" FAST;
|
| 273 |
|
|
NET "ram_data<2>" FAST;
|
| 274 |
|
|
NET "ram_data<3>" FAST;
|
| 275 |
|
|
NET "ram_data<4>" FAST;
|
| 276 |
|
|
NET "ram_data<5>" FAST;
|
| 277 |
|
|
NET "ram_data<6>" FAST;
|
| 278 |
|
|
NET "ram_data<7>" FAST;
|
| 279 |
|
|
NET "ram_data<8>" FAST;
|
| 280 |
|
|
NET "ram_data<9>" FAST;
|
| 281 |
|
|
NET "ram_data<10>" FAST;
|
| 282 |
|
|
NET "ram_data<11>" FAST;
|
| 283 |
|
|
NET "ram_data<12>" FAST;
|
| 284 |
|
|
NET "ram_data<13>" FAST;
|
| 285 |
|
|
NET "ram_data<14>" FAST;
|
| 286 |
|
|
NET "ram_data<15>" FAST;
|
| 287 |
|
|
NET "ram_wrln" FAST;
|
| 288 |
|
|
NET "ram_wrun" FAST;
|
