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[/] [System09/] [tags/] [V10/] [rtl/] [vhdl/] [testbench2.vhd] - Blame information for rev 201

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1 2 dilbert57 
--===========================================================================----
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--
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--  T E S T B E N C H    tesetbench2 - CPU09 Testbench.
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--
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--  www.OpenCores.Org - September 2003
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--  This core adheres to the GNU public license
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--
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-- File name      : Testbench2.vhd
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--
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-- Purpose        : cpu09 Microprocessor Test Bench 2
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--                  Contains ROM to read sector from
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--                  a none existant Compact Flash module
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--
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-- Dependencies   : ieee.Std_Logic_1164
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--                  ieee.std_logic_unsigned
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--                  ieee.std_logic_arith
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--                  ieee.numeric_std
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--
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-- Uses           : cpu09    (cpu09.vhd)      CPU core
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--
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-- Author         : John E. Kent
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--                  dilbert57@opencores.org
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--
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--===========================================================================----
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--
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-- Revision History:
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--===========================================================================--
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--
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-- Version 0.1 - 12st April 2003 - John Kent
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-- First version
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--
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-- Version 1.0- 6 Sep 2003 - John Kent
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-- Initial release to Open Cores
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--
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--===========================================================================--
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library ieee;
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   use ieee.std_logic_1164.all;
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   use IEEE.STD_LOGIC_ARITH.ALL;
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   use IEEE.STD_LOGIC_UNSIGNED.ALL;
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   use ieee.numeric_std.all;
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entity my_testbench is
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end my_testbench;
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46 
-------------------------------------------------------------------------------
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-- Architecture for memio Controller Unit
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-------------------------------------------------------------------------------
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architecture behavior of my_testbench is
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  -----------------------------------------------------------------------------
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  -- Signals
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  -----------------------------------------------------------------------------
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  -- CPU Interface signals
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  signal SysClk      : Std_Logic;
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  signal cpu_reset   : Std_Logic;
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  signal cpu_rw      : Std_Logic;
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  signal cpu_vma     : Std_Logic;
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  signal cpu_addr    : Std_Logic_Vector(15 downto 0);
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  signal cpu_data_in : Std_Logic_Vector(7 downto 0);
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  signal cpu_data_out: Std_Logic_Vector(7 downto 0);
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  signal cpu_alu     : Std_Logic_Vector(15 downto 0);
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  signal cpu_cc      : Std_Logic_Vector(7 downto 0);
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  signal cpu_irq     : Std_Logic;
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  signal cpu_nmi     : Std_Logic;
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  signal cpu_firq    : std_logic;
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  constant width   : integer := 8;
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  constant memsize : integer := 128;
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  type rom_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
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73 
  constant rom_data : rom_array :=
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  (
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"00010000", -- $F800 LDS #$F878 (Point to dummy return to test stack)
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"11001110",
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"11111000",
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"01111000",
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"10000110", -- $F804 LDA #$E0 *** START
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"11100000",
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"00011111", -- $F806 TFR A,DPR
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"10001011",
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---------------------------
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-- "10001101", -- $F80E BSR WAITRDY $F86A
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-- "01100000",
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"10001101", -- $F808 BSR $F874 -- test sub call
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"01101010",
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---------------------------
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"10000110", -- $F80A LDA #$E0
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"11100000",
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"10010111", -- $F80C STA <$E016
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"00010110",
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---------------------------
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-- "10001101", -- $F80E BSR WAITRDY $F86A
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-- "01011010",
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"10001101", -- $F80E BSR $F810
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"00000000",
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--------------------------
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"10000110", -- $F810 LDA #$01
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"00000001",
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"10010111", -- $F812 STA <$E011
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"00010001",
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"10000110", -- $F814 LDA #$EF
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"11101111",
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"10010111", -- $F816 STA <$E017
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"00010111",
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--------------------------
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-- "10001101", -- $F818 BSR WAITRDY $F86A
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-- "01010000",
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"10001101", -- $F818 BSR $F816
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"00000000",
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--------------------------
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"00010000", -- $F81A LDY #$F800
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"10001110",
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"11111000",
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"00000000",
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"11000110", -- $F81E LDB #$7C
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"01111100",
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"10000110", -- $F820 LDA #$01 *** RDLP1
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"00000001",
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"10010111", -- $F822 STA <$E012
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"00010010",
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"11010111", -- $F824 STB <$E013
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"00010011",
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"10000110", -- $F826 LDA #$F4
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"11110100",
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"10010111", -- $F828 STA <$E014
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"00010100",
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"01001111", -- $F82A CLRA
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"10010111", -- $F82B STA <$E015
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"00010101",
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"10001110", -- $F82D LDX #512
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"00000010",
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"00000000",
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"10000110", -- $F830 LDA #$20
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"00100000",
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"10010111", -- $F832 STA <$E017
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"00010111",
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--------------------------
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-- "10001101", -- $F834 BSR WAITRDY $F86A
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-- "00110100",
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"10001101", -- $F834 BSR *
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"00000000",
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--------------------------
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"10010110", -- $F836 LDA <$E017 *** WAITDRQ
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"00010111",
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"10000101", -- $F838 BITA #$08
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"00001000",
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"00100111", -- $F83A BEQ WAITDRQ
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"11111010",
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"10010110", -- $F83C LDA <$E010
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"00010000",
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"10100111", -- $F83E STA ,Y+
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"10100000",
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"00110000", -- $F840 LEAX -1,X
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"00011111",
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"10001100", -- $F842 CMPX #$0000
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"00000000",
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"00000000",
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"00100110", -- $F845 BNE RDLP2
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"11110011",
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--------------------------
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-- "10001101", -- $F847 BSR WAITRDY $F86A
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-- "00100001",
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"10001101", -- $F847 BSR $F841
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"00000000",
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--------------------------
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"01011100", -- $F849 INCB
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"11000001", -- $F84A CMPB #$80
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"10000000",
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"00100110", -- $F84C BNE RDLP1
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"11010110",
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"10001110", -- $F84E LDX #$FF97
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"11111111",
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"10010111",
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"00010000", -- $F851 LDY #$F000
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"10001110",
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"11110000",
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"00000000",
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"11000110", -- $F855 LDB #$61
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"01100001",
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"10100110", -- $F857 LDA 0,X+ *** MOVELP
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"10000000",
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"10100111", -- $F859 STA 0,Y+
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"10100000",
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"01011010", -- $F85B DECB
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----------------------------
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-- "00100110", -- $F85C BNE MOVELP
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-- "11111001",
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"00100110", --$F85C BNE $F861
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"00000011",
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----------------------------
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"01111110", -- $F85E JMP $F000
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"11110000",
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"00000000",
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"00001111", -- $F861 CLR <$E030
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"00110000",
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"01001111", -- $F863 CLRA
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"00011111", -- $F864 TFR A,DPR
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"10001011",
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"01101110", -- $F866 JMP [$FFFE]
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"10011111",
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"11111111",
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"11111110",
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--
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-- Wait for Ready
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--
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"10010110", -- $F86A LDA <$E017 *** WAITRDY
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"00010111",
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"00101011", -- $F86C BMI WAITRDY
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"11111100",
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"10010110", -- $F86E LDA <$E017
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"00010111",
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"10000101", -- $F870 BITA #$40
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"01000000",
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"00100111", -- $F872 BNE WAITRQY
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"11110110",
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"00111001", -- $F874 RTS
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"00010010", -- $F875 NOP
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"11111000", -- $F876 FDB $F80A -- dummy sub return
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"00001010",
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"11111000", -- $F878 FDB $F800
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"00000000",
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"11111000", -- $F87A FDB $F800
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"00000000",
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"11111000", -- $F87C FDB $F800
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"00000000",
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"11111000", -- $F87E FDB $F800
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"00000000"
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         );
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component cpu09
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  port (
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         clk:        in std_logic;
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    rst:             in std_logic;
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    rw:      out        std_logic;              -- Asynchronous memory interface
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    vma:             out        std_logic;
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    address:  out       std_logic_vector(15 downto 0);
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    data_in:  in        std_logic_vector(7 downto 0);
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         data_out: out std_logic_vector(7 downto 0);
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         halt:     in  std_logic;
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         hold:     in  std_logic;
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         irq:      in  std_logic;
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         nmi:      in  std_logic;
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         firq:     in  std_logic;
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         test_alu: out std_logic_vector(15 downto 0);
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         test_cc:  out std_logic_vector(7 downto 0)
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  );
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end component cpu09;
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begin
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cpu : cpu09  port map (
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         clk         => SysClk,
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    rst      => cpu_reset,
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    rw       => cpu_rw,
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    vma       => cpu_vma,
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    address   => cpu_addr(15 downto 0),
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    data_in   => cpu_data_in,
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         data_out  => cpu_data_out,
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         halt      => '0',
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         hold      => '0',
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         irq       => cpu_irq,
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         nmi       => cpu_nmi,
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         firq      => cpu_firq,
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         test_alu  => cpu_alu,
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         test_cc   => cpu_cc
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  );
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  -- *** Test Bench - User Defined Section ***
271 
   tb : PROCESS
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        variable count : integer;
273 
   BEGIN
274 
 
275 
        cpu_reset <= '0';
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        SysClk <= '0';
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   cpu_irq <= '0';
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   cpu_nmi <= '0';
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        cpu_firq <= '0';
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281 
                for count in 0 to 512 loop
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                        SysClk <= '0';
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                        if count = 0 then
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                                cpu_reset <= '1';
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                        elsif count = 1 then
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                                cpu_reset <= '0';
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                        end if;
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                        wait for 100 ns;
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                        SysClk <= '1';
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                        wait for 100 ns;
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                end loop;
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      wait; -- will wait forever
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   END PROCESS;
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-- *** End Test Bench - User Defined Section ***
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297 
 
298 
  rom : PROCESS( cpu_addr )
299 
  begin
300 
    cpu_data_in <= rom_data(conv_integer(cpu_addr(6 downto 0)));
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  end process;
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end behavior; --===================== End of architecture =======================--
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