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[/] [System09/] [trunk/] [rtl/] [Spartan2/] [char_rom2k_b4.vhd] - Blame information for rev 159

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1 99 davidgb
--===========================================================================--
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--                                                                           --
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--  Character generator ROM using 4KBit Block RAMs found in the Spartan 2    --
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--                                                                           --
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--===========================================================================--
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--
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-- File name      : char_rom2k_b4.vhd
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--
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-- Entity name    : char_rom
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--
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-- Purpose        : 2KB Character Generator ROM for vdu8 
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--                  using 4 x 4KBit Block RAMs
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--                  8 dots across [data( 7 dwonto 0)]
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--                  16 lines down [addr( 3 downto 0)]
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--                  127 character [addr(10 downto 4)]
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--
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-- Dependencies   : ieee.Std_Logic_1164
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--                  ieee.std_logic_arith
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--                  ieee.std_logic_unsigned
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--                  unisim.vcomponents
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-- 
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-- Author         : John E. Kent      
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--                  dilbert57@opencores.org
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--
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--
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--  Copyright (C) 2003 - 2010 John Kent
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--
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--  This program is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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--                             Revision History:                             --
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--===========================================================================--
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--
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-- Version Date       Author      Comments
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--
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-- 0.1     2007-02-03 John Kent   Initial Version
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-- 0.2     2010-08-27 John Kent   Added header
49 19 dilbert57
--
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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library unisim;
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        use unisim.vcomponents.all;
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58
entity char_rom is
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    Port (
60 99 davidgb
       clk      : in  std_logic;
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       rst      : in  std_logic;
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       cs       : in  std_logic;
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       addr     : in  std_logic_vector (10 downto 0);
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       rw       : in  std_logic;
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       data_in  : in  std_logic_vector (7 downto 0);
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       data_out : out std_logic_vector (7 downto 0)
67 19 dilbert57
    );
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end char_rom;
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70
architecture rtl of char_rom is
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72 99 davidgb
   signal we        : std_logic;
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   signal data_out0 : std_logic_vector (7 downto 0);
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   signal data_out1 : std_logic_vector (7 downto 0);
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   signal data_out2 : std_logic_vector (7 downto 0);
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   signal data_out3 : std_logic_vector (7 downto 0);
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   signal ena0      : std_logic;
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   signal ena1      : std_logic;
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   signal ena2      : std_logic;
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   signal ena3      : std_logic;
81 19 dilbert57
 
82
   component RAMB4_S8
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    generic (
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      INIT_00, INIT_01, INIT_02, INIT_03,
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      INIT_04, INIT_05, INIT_06, INIT_07,
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      INIT_08, INIT_09, INIT_0A, INIT_0B,
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      INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0) :=
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      x"0000000000000000000000000000000000000000000000000000000000000000"
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    );
90
 
91
    port (
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      clk, we, en, rst : in std_logic;
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      addr :  in std_logic_vector(8 downto 0);
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      di   :  in std_logic_vector(7 downto 0);
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      do   : out std_logic_vector(7 downto 0)
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    );
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  end component;
98
 
99
begin
100
 
101
  MY_RAM0 : RAMB4_S8
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    generic map (
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    INIT_00 => x"0000000009090F09090038043840380000000000070404040400444C54644400",
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    INIT_01 => x"00000000110A040A110078407040780000000000110A040A1100380438403800",
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    INIT_02 => x"000000000D1215110E0078407040780000000000040404041F00784070407800",
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    INIT_03 => x"000000000F080808080070487048700000000000090A0C0A0900487848483000",
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    INIT_04 => x"00000000040404041F0044447C444400000000000E010E100E00704870487000",
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    INIT_05 => x"00000000040404041F001028444444000000000010101E101F007C4040404000",
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    INIT_06 => x"0000000011111E111E003C4040403C000000000008080E080F00404070407800",
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    INIT_07 => x"00000000070202020700380438403800000000000E1111110E00380438403800",
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    INIT_08 => x"00000000070202060200704848487000000000000F080E080F00704848487000",
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    INIT_09 => x"000000000E0107020F00704848487000000000000F0806090700704848487000",
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    INIT_0a => x"00000000090A0C0A0900444C546444000000000001010F090900704848487000",
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    INIT_0b => x"000000000E090E090E0078407040780000000000111315191100380438403800",
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    INIT_0c => x"000000001111151B110078407040780000000000111315191100384040403800",
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    INIT_0d => x"000000000E1010100E00784070407800000000000E090E090E00380438403800",
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    INIT_0e => x"000000000E010E100E00384858403800000000000E010E100E00404070407800",
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    INIT_0f => x"000000000E010E100E00304848484800000000000E010E100E00485070487000"
119
    )
120
 
121
    port map ( clk => clk,
122
                    en  => ena0,
123
                                   we  => we,
124 99 davidgb
                                   rst => rst,
125 19 dilbert57
                                   addr(8 downto 0) => addr(8 downto 0),
126 99 davidgb
               di(7 downto 0)   => data_in(7 downto 0),
127
                                   do(7 downto 0)   => data_out0(7 downto 0)
128 19 dilbert57
        );
129
 
130
  MY_RAM1 : RAMB4_S8
131
    generic map (
132
    INIT_00 => x"0000000008080000080808080808080000000000000000000000000000000000",
133
    INIT_01 => x"000000002424247E2424247E2424240000000000000000000000001212121200",
134
    INIT_02 => x"0000000043434020100804020161610000000000083E4909093E4848493E0800",
135
    INIT_03 => x"00000000000000000000002010080C00000000003D4244444438444444443800",
136
    INIT_04 => x"0000000020100804040404040810200000000000020408101010101008040200",
137
    INIT_05 => x"0000000000000808087F0808080000000000000000004122147F142241000000",
138
    INIT_06 => x"0000000000000000007F00000000000000402010181800000000000000000000",
139
    INIT_07 => x"0000000040404020100804020101010000000000181800000000000000000000",
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    INIT_08 => x"000000003E080808080808082818080000000000081422414141414122140800",
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    INIT_09 => x"000000003E410101010E010101413E00000000007F4020100804020141423C00",
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    INIT_0a => x"000000003E410101615E404040407F000000000002020202027F22120A060200",
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    INIT_0b => x"00000000404020100804020101017F00000000001E214141615E404040211E00",
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    INIT_0c => x"000000003C420101013D434141423C00000000003E414141413E414141413E00",
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    INIT_0d => x"0000402010181818000000181818000000000000001818180000001818180000",
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    INIT_0e => x"00000000000000007F00007F0000000000000000010204081020100804020100",
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    INIT_0f => x"00000000080800080808060101413E0000000000402010080402040810204000"
148
    )
149
 
150
    port map ( clk => clk,
151
                    en  => ena1,
152
                                   we  => we,
153 99 davidgb
                                   rst => rst,
154 19 dilbert57
                                   addr(8 downto 0) => addr(8 downto 0),
155 99 davidgb
               di(7 downto 0)   => data_in(7 downto 0),
156
                                   do(7 downto 0)   => data_out1(7 downto 0)
157 19 dilbert57
        );
158
 
159
  MY_RAM2 : RAMB4_S8
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    generic map (
161
    INIT_00 => x"0000000041414141417F414122140800000000001C224140404E494541221C00",
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    INIT_01 => x"000000001E2141404040404041211E00000000007E212121213E212121217E00",
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    INIT_02 => x"000000007F404040407C404040407F00000000007C2221212121212121227C00",
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    INIT_03 => x"000000001E2141414147404040211E000000000040404040407C404040407F00",
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    INIT_04 => x"000000003E0808080808080808083E000000000041414141417F414141414100",
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    INIT_05 => x"00000000414244485060504844424100000000003C4202020202020202020700",
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    INIT_06 => x"00000000414141414141494955634100000000007F4040404040404040404000",
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    INIT_07 => x"000000003E4141414141414141413E0000000000414141434549495161414100",
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    INIT_08 => x"000000003D4245494141414141413E000000000040404040407E414141417E00",
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    INIT_09 => x"000000003E410101013E404040413E000000000041424448507E414141417E00",
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    INIT_0a => x"000000003E414141414141414141410000000000080808080808080808087F00",
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    INIT_0b => x"0000000022225555494941414141410000000000080814141422222241414100",
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    INIT_0c => x"0000000008080808080814224141410000000000414141221408142241414100",
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    INIT_0d => x"000000001E1010101010101010101E00000000007F4040201008040201017F00",
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    INIT_0e => x"000000003C0404040404040404043C0000000000010101020408102040404000",
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    INIT_0f => x"000000007F000000000000000000000000000000000000000000004122140800"
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    )
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179
    port map ( clk => clk,
180
                    en  => ena2,
181
                                   we  => we,
182 99 davidgb
                                   rst => rst,
183 19 dilbert57
                                   addr(8 downto 0) => addr(8 downto 0),
184 99 davidgb
               di(7 downto 0)   => data_in(7 downto 0),
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                                   do(7 downto 0)   => data_out2(7 downto 0)
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        );
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188
  MY_RAM3 : RAMB4_S8
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    generic map (
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    INIT_00 => x"000000003F41413F01013E000000000000000000000000000000000204081800",
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    INIT_01 => x"000000001E21404040211E0000000000000000005E61616141615E4040404000",
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    INIT_02 => x"000000003E40407F41413E0000000000000000003D43414141433D0101010100",
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    INIT_03 => x"003C4202023E424242423D0100000000000000001010101010107C1010110E00",
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    INIT_04 => x"000000003E0808080808180000080800000000004141414141615E4040404000",
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    INIT_05 => x"00000000414448704844414040404000003C4202020202020202020000020200",
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    INIT_06 => x"00000000414141494955220000000000000000001C0808080808080808081800",
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    INIT_07 => x"000000003E41414141413E0000000000000000004141414141615E0000000000",
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    INIT_08 => x"00010101013D434343433D000000000000404040405E616161615E0000000000",
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    INIT_09 => x"000000003E01013E40403E0000000000000000002020202020314E0000000000",
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    INIT_0a => x"000000003D4242424242420000000000000000000C12101010107C1010101000",
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    INIT_0b => x"0000000022554949414141000000000000000000081414222241410000000000",
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    INIT_0c => x"003C4202023A4642424242000000000000000000412214081422410000000000",
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    INIT_0d => x"00000000070808081020100808080700000000007F20100804027F0000000000",
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    INIT_0e => x"0000000070080808040204080808700000000000080808080800080808080800",
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    INIT_0f => x"0000000049224922492249224922490000000000000000000000000046493100"
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    )
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208
    port map ( clk => clk,
209
                    en  => ena3,
210
                                   we  => we,
211 99 davidgb
                                   rst => rst,
212 19 dilbert57
                                   addr(8 downto 0) => addr(8 downto 0),
213 99 davidgb
               di(7 downto 0)   => data_in(7 downto 0),
214
                                   do(7 downto 0)   => data_out3(7 downto 0)
215 19 dilbert57
        );
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217 99 davidgb
my_char_rom2k_b4 : process ( cs, rw, addr, data_out0, data_out1, data_out2, data_out3 )
218 19 dilbert57
begin
219 99 davidgb
    ena0 <= '0';
220
    ena1 <= '0';
221
    ena2 <= '0';
222
    ena3 <= '0';
223 19 dilbert57
         case addr(10 downto 9) is
224
         when "00" =>
225 99 davidgb
      ena0     <= cs;
226
                data_out <= data_out0;
227 19 dilbert57
         when "01" =>
228 99 davidgb
           ena1     <= cs;
229
                data_out <= data_out1;
230 19 dilbert57
         when "10" =>
231 99 davidgb
      ena2     <= cs;
232
                data_out <= data_out2;
233 19 dilbert57
         when "11" =>
234 99 davidgb
           ena3     <= cs;
235
                data_out <= data_out3;
236 19 dilbert57
         when others =>
237
      null;
238
         end case;
239
 
240 99 davidgb
         we <= not rw;
241 19 dilbert57
 
242
end process;
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244
end;
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