OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [Spartan2/] [ram1k_b4.vhd] - Blame information for rev 176

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 19 dilbert57
--
2
-- Ram1k_b4.vhd
3
--
4
-- 1K Byte RAM made out of 2 x 512 byte Block RAMs.
5
-- John Kent
6
-- 3 February 2007
7
--
8
library IEEE;
9
use IEEE.STD_LOGIC_1164.ALL;
10
use IEEE.STD_LOGIC_ARITH.ALL;
11
use IEEE.STD_LOGIC_UNSIGNED.ALL;
12
library unisim;
13
        use unisim.vcomponents.all;
14
 
15
entity ram1k is
16
    Port (
17
       WB_CLK_I : in  std_logic;
18
       WB_RST_I : in  std_logic;
19
       WB_ADR_I : in  std_logic_vector (9 downto 0);
20
       WB_DAT_O : out std_logic_vector (7 downto 0)
21
       WB_DAT_I : in  std_logic_vector (7 downto 0);
22
       WB_WE_I  : in  std_logic;
23
       WB_STB_I : in  std_logic;
24
    );
25
end ram1k;
26
 
27
architecture rtl of ram_2k is
28
 
29
   signal rdata0   : std_logic_vector (7 downto 0);
30
   signal rdata1   : std_logic_vector (7 downto 0);
31
   signal ena0     : std_logic;
32
   signal ena1     : std_logic;
33
 
34
   component RAMB4_S8
35
    generic (
36
      INIT_00, INIT_01, INIT_02, INIT_03,
37
      INIT_04, INIT_05, INIT_06, INIT_07,
38
      INIT_08, INIT_09, INIT_0A, INIT_0B,
39
      INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"
40
    );
41
 
42
    port (
43
      clk, we, en, rst : in std_logic;
44
      addr :  in std_logic_vector(8 downto 0);
45
      di   :  in std_logic_vector(7 downto 0);
46
      do   : out std_logic_vector(7 downto 0)
47
    );
48
  end component;
49
 
50
begin
51
 
52
  MY_RAM0 : RAMB4_S8
53
    generic map (
54
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
55
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000"    )
56
 
57
    port map (
58
        clk => WB_CLK_I,
59
        en  => ena0,
60
        we  => WB_WE_I,
61
        rst => WB_RST_I,
62
        addr(8 downto 0) => WB_ADR_I(8 downto 0),
63
        di(7 downto 0)   => WB_DAT_I(7 downto 0),
64
        do(7 downto 0)   => rdata0(7 downto 0)
65
        );
66
 
67
  MY_RAM1 : RAMB4_S8
68
    generic map (
69
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
70
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000"    )
71
 
72
    port map ( clk => clk,
73
        clk => WB_CLK_I,
74
        en  => ena1,
75
        we  => WB_WE_I,
76
        rst => WB_RST_I,
77
        addr(8 downto 0) => WB_ADR_I(8 downto 0),
78
        di(7 downto 0)   => WB_DAT_I(7 downto 0),
79
        do(7 downto 0)   => rdata1(7 downto 0)
80
        );
81
 
82
 
83
my_ram_1k : process (WB_STB_I, WB_ADR_I, rdata0, rdata1 )
84
begin
85
        case WB_ADR_I(9) is
86
        when "0" =>
87
                ena0     <= WB_STB_I;
88
                ena1     <= '0';
89
                WB_DAT_O <= rdata0;
90
        when "1" =>
91
                ena0     <= '0';
92
                ena1     <= WB_STB_I;
93
                WB_DAT_O <= rdata1;
94
        when others =>
95
                null;
96
        end case;
97
 
98
end process;
99
 
100
end;
101
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.