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[/] [System09/] [trunk/] [rtl/] [System09_BurchED_B5-X300/] [System09_BurchED_B5-X300.vhd] - Blame information for rev 114

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1 19 dilbert57
--===========================================================================----
2
--
3
--  S Y N T H E Z I A B L E    System09 - SOC.
4
--
5
--  www.OpenCores.Org - September 2003
6
--  This core adheres to the GNU public license  
7
--
8 108 davidgb
-- File name      : System09_BurchED_B5-X300.vhd
9 19 dilbert57
--
10
-- Purpose        : Top level file for 6809 compatible system on a chip
11
--                  Designed with Xilinx XC2S300e Spartan 2+ FPGA.
12
--                  Implemented With BurchED B5-X300 FPGA board,
13
--                  B5-SRAM module, B5-CF module and B5-FPGA-CPU-IO module
14
--
15
-- Dependencies   : ieee.Std_Logic_1164
16
--                  ieee.std_logic_unsigned
17
--                  ieee.std_logic_arith
18
--                  ieee.numeric_std
19
--
20
-- Uses           : 
21 108 davidgb
--                  cpu09         (cpu09.vhd)      CPU core
22
--                  SYS09BUG_F800 (sys09b5x_b4.vhd) Monitor ROM
23
--                  dat_ram       (datram.vhd)     Dynamic Address Translation
24
--                  acia6850      (acia6850.vhd) ACIA / MiniUART
25
--                  ACIA_Clock    (ACIA_Clock.vhd) ACIA Baud Clock Divider
26
--                  keyboard      (keyboard.vhd)   PS/2 Keyboard Interface
27
--                  vdu8          (vdu8.vhd)       80 x 25 Video Display
28
--                  timer         (timer.vhd)      Timer module
29
--                  trap               (trap.vhd)       Bus Trap interrupt
30
--                  ioport        (ioport.vhd)     Parallel I/O port.
31 19 dilbert57
-- 
32
-- Author         : John E. Kent      
33
--                  dilbert57@opencores.org      
34
--      Memory Map     :
35 108 davidgb
-- Memory Map     :
36
--
37
-- $0000 - $DFFF System RAM (256K Mapped via DAT)
38
-- $E000 - ACIA (SWTPc)
39
-- $E010 - Reserved for SWTPc FD-01 FD1771 FDC
40
-- $E020 - Keyboard
41
-- $E030 - VDU
42
-- $E040 - Reserved for SWTPc MP-T (was Compact Flash)
43
-- $E050 - Timer
44
-- $E060 - Bus Trap (Hardware Breakpoint Interrupt Logic)
45 19 dilbert57
-- $E070 - Parallel I/O
46 108 davidgb
-- $E080 - Reserved for SWTPc MP-ID 6821 PIA (?)
47
-- $E090 - Reserved for SWTPc MP-ID 6840 PTM (?)
48
-- $E0A0 - Reserved SPP Printer Port
49
-- $E0B0 - Reserved
50
-- $E0C0 - Reserved
51
-- $E100 - $E13F IDE / Compact Flash Card
52
-- $E140 - $E17F Reserved for Ethernet MAC (XESS)
53
-- $E180 - $E1BF Reserved for Expansion Slot 0 (XESS)
54
-- $E1C0 - $E1FF Reserved for Expansion Slot 1 (XESS)
55
-- $E200 - $EFFF Dual Port RAM interface
56
-- $F000 - $F7FF Reserved SWTPc DMAF-2
57
-- $F800 - $FFFF Sys09bug ROM (Read only)
58
-- $FFF0 - $FFFF DAT - Dynamic Address Translation (Write Only)
59 19 dilbert57
--
60
--===========================================================================----
61
--
62
-- Revision History:
63
--===========================================================================--
64
-- Version 0.1 - 20 March 2003
65
-- Version 0.2 - 30 March 2003
66
-- Version 0.3 - 29 April 2003
67
-- Version 0.4 - 29 June 2003
68
--
69
-- Version 0.5 - 19 July 2003
70
-- prints out "Hello World"
71
--
72
-- Version 0.6 - 5 September 2003
73
-- Runs SBUG
74
--
75
-- Version 1.0- 6 Sep 2003 - John Kent
76
-- Inverted SysClk
77
-- Initial release to Open Cores
78
--
79
-- Version 1.1 - 17 Jan 2004 - John Kent
80
-- Updated miniUart.
81
--
82
-- Version 1.2 - 25 Jan 2004 - John Kent
83
-- removed signals "test_alu" and "test_cc" 
84
-- Trap hardware re-instated.
85
--
86
-- Version 1.3 - 11 Feb 2004 - John Kent
87
-- Designed forked off to produce System09_VDU
88
-- Added VDU component
89
--      VDU runs at 25MHz and divides the clock by 2 for the CPU
90
-- UART Runs at 57.6 Kbps
91
--
92
-- Version 1.4 - 21 Nov 2004 - John Kent
93
-- Changes to make compatible with Spartan3 starter kit version
94
-- Designed to run with a 50MHz clock input.
95
-- the VDU divides 50 MHz to generate a 
96
-- 25 MHz VDU Pixel Clock and a 12.5 MHz CPU clock
97
-- Changed Monitor ROM signals to make it look like
98
-- a standard 2K memory block
99
-- Re-assigned I/O port assignments so it is possible to run KBUG9
100
-- $E000 - ACIA
101
-- $E010 - Keyboard
102
-- $E020 - VDU
103
-- $E030 - Compact Flash
104
-- $E040 - Timer
105
-- $E050 - Bus trap
106
-- $E060 - Parallel I/O
107
--
108
-- Version 1.5 - 3rd February 2007 - John Kent
109
-- Changed VDU8 to use external clock divider
110
-- renamed miniUART to ACIA_6850
111
-- Memory decoding of ROM & IO now uses DAT
112
--
113
-- Version 1.6 - 7th Februaury 2007 - John Kent
114
-- Made ACIA Clock generator an external component
115
-- Added Generics to VDU and Keyboard
116
-- Changed decoding
117
--
118
-- Version 1.7 - 20th May 2007 - John Kent
119
-- Added 4 wait states to CF access
120
-- Removed DAT memory map control of ROM & IO
121
-- to allow for full use of RAM as a RAM disk.
122
-- Mapped in all 16 bits of the CF data bus.
123 108 davidgb
--
124
-- Version 1.8 - 23rd February 2009 - John Kent
125
-- Renamed mon_rom to SYS09BUG_F800
126
--
127
-- Version 1.9 - 5th sepember 2010 - John Kent
128
-- Added Peripheral bus interface
129
-- Made the clock divider an external module
130
-- Rearranged VDU generic signals
131
-- Changed address decoding
132
-- Made the SRAM an external module
133 19 dilbert57
-- 
134
--===========================================================================
135
--
136
library ieee;
137
   use ieee.std_logic_1164.all;
138
   use IEEE.STD_LOGIC_ARITH.ALL;
139
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
140
   use ieee.numeric_std.all;
141
library unisim;
142
        use unisim.vcomponents.all;
143
 
144
entity System09 is
145
  port(
146 108 davidgb
    clk_in      : in  Std_Logic;  -- System Clock input
147
         rst_n       : in  Std_logic;  -- Master Reset input (active low)
148 19 dilbert57
    LED         : out std_logic;  -- Diagnostic LED Flasher
149
 
150
    -- Memory Interface signals
151
    ram_csn     : out Std_Logic;
152
    ram_wrln    : out Std_Logic;
153
    ram_wrun    : out Std_Logic;
154
    ram_addr    : out Std_Logic_Vector(16 downto 0);
155
    ram_data    : inout Std_Logic_Vector(15 downto 0);
156
 
157
         -- Stuff on the peripheral board
158
 
159
         -- PS/2 Keyboard
160
         kb_clock    : inout Std_logic;
161
         kb_data     : inout Std_Logic;
162
 
163
         -- PS/2 Mouse interface
164
--       mouse_clock : in  Std_Logic;
165
--       mouse_data  : in  Std_Logic;
166
 
167
         -- Uart Interface
168
    rxbit       : in  Std_Logic;
169
         txbit       : out Std_Logic;
170
    rts_n       : out Std_Logic;
171
    cts_n       : in  Std_Logic;
172
 
173
         -- CRTC output signals
174
         v_drive     : out Std_Logic;
175
    h_drive     : out Std_Logic;
176
    blue_lo     : out std_logic;
177
    blue_hi     : out std_logic;
178
    green_lo    : out std_logic;
179
    green_hi    : out std_logic;
180
    red_lo      : out std_logic;
181
    red_hi      : out std_logic;
182
--         buzzer      : out std_logic;
183
 
184
-- Compact Flash
185
    cf_rst_n     : out std_logic;
186 22 dilbert57
    cf_cs0_n     : out std_logic;
187
    cf_cs1_n     : out std_logic;
188 19 dilbert57
    cf_rd_n      : out std_logic;
189
    cf_wr_n      : out std_logic;
190
    cf_a         : out std_logic_vector(2 downto 0);
191
    cf_d         : inout std_logic_vector(15 downto 0);
192
 
193
-- Parallel I/O port
194
    porta        : inout std_logic_vector(7 downto 0);
195
    portb        : inout std_logic_vector(7 downto 0);
196
 
197
-- CPU bus
198
         bus_clk      : out std_logic;
199
         bus_reset    : out std_logic;
200
         bus_rw       : out std_logic;
201
         bus_cs       : out std_logic;
202
    bus_addr     : out std_logic_vector(15 downto 0);
203 108 davidgb
         bus_data     : inout std_logic_vector(7 downto 0)
204 19 dilbert57
         );
205
end System09;
206
 
207
-------------------------------------------------------------------------------
208
-- Architecture for System09
209
-------------------------------------------------------------------------------
210
architecture rtl of System09 is
211
  -----------------------------------------------------------------------------
212
  -- constants
213
  -----------------------------------------------------------------------------
214 108 davidgb
  constant SYS_CLK_FREQ  : integer := 50000000;  -- FPGA System Clock
215
  constant VGA_CLK_FREQ  : integer := 25000000;  -- VGA Pixel Clock
216
  constant CPU_CLK_FREQ  : integer := 12500000;  -- CPU Clock
217
  constant BAUD_RATE     : integer := 57600;      -- Baud Rate
218
  constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
219 19 dilbert57
 
220
  type hold_state_type is ( hold_release_state, hold_request_state );
221
 
222
  -----------------------------------------------------------------------------
223
  -- Signals
224
  -----------------------------------------------------------------------------
225 108 davidgb
  -- Clock signals
226
  signal sys_clk       : std_logic;
227
  signal vga_clk       : std_logic;
228
 
229
  -- CPU Interface signals
230
  signal cpu_rst       : Std_Logic;
231
  signal cpu_clk       : Std_Logic;
232
  signal cpu_vma       : std_logic;
233
  signal cpu_addr      : std_logic_vector(15 downto 0);
234
  signal cpu_rw        : std_logic;
235
  signal cpu_data_in   : std_logic_vector(7 downto 0);
236
  signal cpu_data_out  : std_logic_vector(7 downto 0);
237
  signal cpu_firq      : std_logic;
238
  signal cpu_irq       : std_logic;
239
  signal cpu_nmi       : std_logic;
240
  signal cpu_halt      : std_logic;
241
  signal cpu_hold      : std_logic;
242
 
243
  -- Dynamic address translation
244
  signal dat_cs       : std_logic;
245
  signal dat_addr     : std_logic_vector(7 downto 0);
246
 
247 19 dilbert57
  -- Monitor ROM
248
  signal rom_data_out  : Std_Logic_Vector(7 downto 0);
249
  signal rom_cs        : std_logic;
250
 
251 108 davidgb
  -- UART/ACIA Interface signals
252 19 dilbert57
  signal uart_data_out : Std_Logic_Vector(7 downto 0);
253
  signal uart_cs       : Std_Logic;
254
  signal uart_irq      : Std_Logic;
255 108 davidgb
  signal uart_clk      : Std_Logic;
256 19 dilbert57
  signal DCD_n         : Std_Logic;
257
 
258 108 davidgb
  -- Keyboard port
259
  signal kbd_data_out  : std_logic_vector(7 downto 0);
260
  signal kbd_cs        : std_logic;
261
  signal kbd_irq       : std_logic;
262
 
263
  -- Video Display Unit
264
  signal vdu_cs        : std_logic;
265
  signal vdu_data_out  : std_logic_vector(7 downto 0);
266
  signal vga_red       : std_logic;
267
  signal vga_green     : std_logic;
268
  signal vga_blue      : std_logic;
269 19 dilbert57
 
270 108 davidgb
  -- Timer
271
  signal tmr_data_out  : std_logic_vector(7 downto 0);
272
  signal tmr_cs        : std_logic;
273
  signal tmr_irq       : std_logic;
274 19 dilbert57
 
275 108 davidgb
  -- Trap Hardware break point
276
  signal trap_cs       : std_logic;
277
  signal trap_data_out : std_logic_vector(7 downto 0);
278
  signal trap_irq      : std_logic;
279
 
280 19 dilbert57
  -- Parallel I/O port
281 108 davidgb
  signal pio_data_out  : std_logic_vector(7 downto 0);
282
  signal pio_cs        : std_logic;
283 19 dilbert57
 
284 108 davidgb
  -- Peripheral bus
285
  signal pb_data_out   : std_logic_vector(7 downto 0);
286
  signal pb_cs         : std_logic;
287
  signal pb_hold       : std_logic;
288
 
289
  -- Compact Flash on peripheral bus
290
  signal cf_cs         : std_logic;
291 19 dilbert57
 
292 108 davidgb
  -- SRAM
293
  signal ram_cs        : std_logic; -- memory chip select
294
  signal ram_data_out  : std_logic_vector(7 downto 0);
295 19 dilbert57
 
296 108 davidgb
-----------------------------------------------------------------
297
--
298
--                     Clock generator
299
--
300
-----------------------------------------------------------------
301
 
302
component clock_div
303
  port(
304
    clk_in      : in  std_Logic;  -- System Clock input
305
         sys_clk     : out std_logic;  -- System Clock Out    (1/1)
306
         vga_clk     : out std_logic;  -- VGA Pixel Clock Out (1/2)
307
    cpu_clk     : out std_logic   -- CPU Clock Out       (1/4)
308
  );
309
end component;
310
 
311
 
312
-----------------------------------------------------------------
313
--
314
--                      LED Flasher
315
--
316
-----------------------------------------------------------------
317 19 dilbert57
 
318 108 davidgb
component flasher
319
  port (
320
    clk      : in  std_logic;           -- Clock input
321
    rst      : in  std_logic;           -- Reset input (active high)
322
    LED      : out Std_Logic            -- LED output        
323
  );
324
end component;
325
 
326
------------------------------------------------------------
327
--
328
--           B5 SRAM interface ($0000 - $DFFF)
329
--
330
------------------------------------------------------------
331
component BED_SRAM
332
  port (
333
    --
334
    -- CPU Interface signals
335
    --
336
    clk       : in  std_logic;                     -- System Clock (twice the CPU clock)
337
    rst       : in  std_logic;                     -- Reset input (active high)
338
    cs        : in  std_logic;                     -- RAM Chip Select
339
    addr      : in  std_logic_vector(17 downto 0); -- RAM address bus
340
    rw        : in  std_logic;                     -- Read / Not Write
341
    data_in   : in  std_logic_vector(7 downto 0);  -- Data Bus In 
342
    data_out  : out std_logic_vector(7 downto 0);  -- Data Bus Out
343
    --
344
    -- BED_SRAM Interface Signals
345
    --
346
    ram_csn   : out   Std_Logic;
347
    ram_wrln  : out   Std_Logic;
348
    ram_wrun  : out   Std_Logic;
349
    ram_addr  : out   Std_Logic_Vector(16 downto 0);
350
    ram_data  : inout Std_Logic_Vector(15 downto 0)
351
 
352
    );
353
end component;
354
 
355 19 dilbert57
 
356
-----------------------------------------------------------------
357
--
358
-- CPU09 CPU core
359
--
360
-----------------------------------------------------------------
361
 
362
component cpu09
363
  port (
364 108 davidgb
         clk      :     in  std_logic;
365
    rst      : in  std_logic;
366
    vma      :  out std_logic;
367
    addr     : out std_logic_vector(15 downto 0);
368
    rw       :  out std_logic;          -- Asynchronous memory interface
369
    data_in  : in  std_logic_vector(7 downto 0);
370
         data_out : out std_logic_vector(7 downto 0);
371
         halt     : in  std_logic;
372
         hold     : in  std_logic;
373
         irq      : in  std_logic;
374
         nmi      : in  std_logic;
375
         firq     : in  std_logic
376 19 dilbert57
  );
377
end component;
378
 
379
----------------------------------------
380
--
381
-- Dynamic Address Translation Registers
382
--
383
----------------------------------------
384
component dat_ram
385
  port (
386
    clk:      in  std_logic;
387
         rst:      in  std_logic;
388
         cs:       in  std_logic;
389
         rw:       in  std_logic;
390
         addr_lo:  in  std_logic_vector(3 downto 0);
391
         addr_hi:  in  std_logic_vector(3 downto 0);
392
    data_in:  in  std_logic_vector(7 downto 0);
393
         data_out: out std_logic_vector(7 downto 0)
394
         );
395
end component;
396
 
397 108 davidgb
----------------------------------------
398
--
399
-- SBUG Block RAM Monitor ROM
400
--
401
----------------------------------------
402
component SYS09BUG_F800
403
    port (
404
       clk      : in  std_logic;
405
       rst      : in  std_logic;
406
       cs       : in  std_logic;
407
       addr     : in  std_logic_vector (10 downto 0);
408
       rw       : in  std_logic;
409
       data_in  : in  std_logic_vector (7 downto 0);
410
       data_out : out std_logic_vector (7 downto 0)
411
    );
412
end component;
413
 
414 19 dilbert57
-----------------------------------------------------------------
415
--
416
-- 6850 ACIA/UART
417
--
418
-----------------------------------------------------------------
419
 
420 108 davidgb
component acia6850
421 19 dilbert57
  port (
422
     clk      : in  Std_Logic;  -- System Clock
423
     rst      : in  Std_Logic;  -- Reset input (active high)
424
     cs       : in  Std_Logic;  -- miniUART Chip Select
425 108 davidgb
     addr     : in  Std_Logic;  -- Register Select
426 19 dilbert57
     rw       : in  Std_Logic;  -- Read / Not Write
427 108 davidgb
     data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
428
     data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
429 19 dilbert57
     irq      : out Std_Logic;  -- Interrupt
430
     RxC      : in  Std_Logic;  -- Receive Baud Clock
431
     TxC      : in  Std_Logic;  -- Transmit Baud Clock
432
     RxD      : in  Std_Logic;  -- Receive Data
433
     TxD      : out Std_Logic;  -- Transmit Data
434
          DCD_n    : in  Std_Logic;  -- Data Carrier Detect
435
     CTS_n    : in  Std_Logic;  -- Clear To Send
436
     RTS_n    : out Std_Logic );  -- Request To send
437
end component;
438
 
439
-----------------------------------------------------------------
440
--
441
-- ACIA Clock divider
442
--
443
-----------------------------------------------------------------
444
 
445
component ACIA_Clock
446
  generic (
447 108 davidgb
     SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
448
          ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
449 19 dilbert57
  );
450
  port (
451
     clk      : in  Std_Logic;  -- System Clock Input
452
          ACIA_clk : out Std_logic   -- ACIA Clock output
453
  );
454
end component;
455 108 davidgb
 
456
----------------------------------------
457
--
458
-- PS/2 Keyboard
459
--
460
----------------------------------------
461 19 dilbert57
 
462 108 davidgb
component keyboard
463
  generic(
464
    KBD_CLK_FREQ : integer := CPU_CLK_FREQ
465
  );
466
  port(
467
    clk             : in    std_logic;
468
    rst             : in    std_logic;
469
    cs              : in    std_logic;
470
    rw              : in    std_logic;
471
    addr            : in    std_logic;
472
    data_in         : in    std_logic_vector(7 downto 0);
473
    data_out        : out   std_logic_vector(7 downto 0);
474
    irq             : out   std_logic;
475
    kbd_clk         : inout std_logic;
476
    kbd_data        : inout std_logic
477
  );
478
end component;
479
 
480 19 dilbert57
----------------------------------------
481
--
482 108 davidgb
-- Video Display Unit.
483
--
484
----------------------------------------
485
component vdu8
486
  generic(
487
    VGA_CLK_FREQ           : integer := VGA_CLK_FREQ; -- 25MHz
488
         VGA_HOR_CHARS          : integer := 80; -- CHARACTERS 25.6us
489
         VGA_HOR_CHAR_PIXELS    : integer := 8;  -- PIXELS 0.32us
490
         VGA_HOR_FRONT_PORCH    : integer := 16; -- PIXELS 0.64us (0.94us)
491
         VGA_HOR_SYNC           : integer := 96; -- PIXELS 3.84us (3.77us)
492
         VGA_HOR_BACK_PORCH     : integer := 48; -- PIXELS 1.92us (1.89us)
493
         VGA_VER_CHARS          : integer := 25; -- CHARACTERS 12.8ms
494
         VGA_VER_CHAR_LINES     : integer := 16; -- LINES 0.512ms
495
         VGA_VER_FRONT_PORCH    : integer := 10; -- LINES 0.320ms
496
         VGA_VER_SYNC           : integer := 2;  -- LINES 0.064ms
497
         VGA_VER_BACK_PORCH     : integer := 34  -- LINES 1.088ms
498
  );
499
  port(
500
    -- control register interface
501
    vdu_clk      : in  std_logic;        -- CPU Clock - 12.5MHz
502
    vdu_rst      : in  std_logic;
503
    vdu_cs       : in  std_logic;
504
    vdu_rw       : in  std_logic;
505
    vdu_addr     : in  std_logic_vector(2 downto 0);
506
    vdu_data_in  : in  std_logic_vector(7 downto 0);
507
    vdu_data_out : out std_logic_vector(7 downto 0);
508
 
509
    -- vga port connections
510
    vga_clk      : in  std_logic;       -- VGA Pixel Clock - 25 MHz
511
    vga_red_o    : out std_logic;
512
    vga_green_o  : out std_logic;
513
    vga_blue_o   : out std_logic;
514
    vga_hsync_o  : out std_logic;
515
    vga_vsync_o  : out std_logic
516
  );
517
end component;
518
 
519
----------------------------------------
520
--
521 19 dilbert57
-- Timer module
522
--
523
----------------------------------------
524
 
525
component timer
526
  port (
527 108 davidgb
    clk       : in std_logic;
528
    rst       : in std_logic;
529
    cs        : in std_logic;
530
    addr      : in std_logic;
531
    rw        : in std_logic;
532
    data_in   : in std_logic_vector(7 downto 0);
533
         data_out  : out std_logic_vector(7 downto 0);
534
         irq       : out std_logic
535
  );
536 19 dilbert57
end component;
537
 
538
------------------------------------------------------------
539
--
540
-- Bus Trap logic
541
--
542
------------------------------------------------------------
543
 
544
component trap
545 108 davidgb
  port (
546
    clk        : in  std_logic;
547 19 dilbert57
    rst        : in  std_logic;
548
    cs         : in  std_logic;
549
    rw         : in  std_logic;
550
    vma        : in  std_logic;
551
    addr       : in  std_logic_vector(15 downto 0);
552
    data_in    : in  std_logic_vector(7 downto 0);
553 108 davidgb
    data_out   : out std_logic_vector(7 downto 0);
554
    irq        : out std_logic
555 19 dilbert57
  );
556
end component;
557
 
558
----------------------------------------
559
--
560
-- Dual 8 bit Parallel I/O module
561
--
562
----------------------------------------
563
component ioport
564 108 davidgb
  port (
565
    clk       : in  std_logic;
566 19 dilbert57
    rst       : in  std_logic;
567
    cs        : in  std_logic;
568
    rw        : in  std_logic;
569
    addr      : in  std_logic_vector(1 downto 0);
570
    data_in   : in  std_logic_vector(7 downto 0);
571 108 davidgb
    data_out  : out std_logic_vector(7 downto 0);
572
    porta_io  : inout std_logic_vector(7 downto 0);
573
    portb_io  : inout std_logic_vector(7 downto 0)
574 19 dilbert57
  );
575
end component;
576
 
577 108 davidgb
------------------------------------------------------------
578
--
579
-- Peripheral Bus interface (IDE CF) ($E100 - $E1FF)
580
--
581
------------------------------------------------------------
582 19 dilbert57
 
583 108 davidgb
component peripheral_bus is
584
  port (
585
    --
586
    -- CPU Interface signals
587
    --
588
    clk      : in  std_logic;                     -- System Clock
589
    rst      : in  std_logic;                     -- Reset input (active high)
590
    cs       : in  std_logic;                     -- Peripheral Bus Chip Select
591
    addr     : in  std_logic_vector(7 downto 0);  -- Register Select
592
    rw       : in  std_logic;                     -- Read / Not Write
593
    data_in  : in  std_logic_vector(7 downto 0);  -- Data Bus In 
594
    data_out : out std_logic_vector(7 downto 0);  -- Data Bus Out
595
    hold     : out std_logic;                     -- Hold bus cycle output
596
    --
597
    -- Peripheral Bus Interface Signals
598
    -- IO + ($00 - $FF) 
599
    -- (for compatibility with XSA-3S1000 / XST 3.0)
600
    --
601
    pb_rd_n  : out   std_logic; -- ide pin 25
602
    pb_wr_n  : out   std_logic; -- ide pin 23
603
    pb_addr  : out   std_logic_vector( 4 downto 0);
604
    pb_data  : inout std_logic_vector(15 downto 0);
605
 
606
    -- Peripheral chip selects on Peripheral Bus 
607
    ide_cs   : out  std_logic;  -- IDE / CF interface ($00 - $3F)
608
    eth_cs   : out  std_logic;  -- Ethernet interface ($40 - $7F)
609
    sl1_cs   : out  std_logic;  -- Expansion slot 1   ($80 - $BF)
610
    sl2_cs   : out  std_logic   -- Expansion slot 2   ($C0 - $FF)
611
    );
612
end component;
613
 
614 19 dilbert57
 
615
component BUFG
616
  port (
617
                i: in  std_logic;
618
                o: out std_logic
619
  );
620
end component;
621
 
622
begin
623 108 davidgb
-----------------------------------------------------------------------------
624
-- Instantiation of internal components
625
-----------------------------------------------------------------------------
626
----------------------------------------
627
--
628
-- Clock generator
629
--
630
----------------------------------------
631
my_clock_div: clock_div port map (
632
    clk_in   => clk_in,   -- Clock input
633
    sys_clk  => sys_clk,  -- System Clock Out    (1/1)
634
    vga_clk  => vga_clk,  -- VGA Pixel Clock Out (1/2)
635
    cpu_clk  => cpu_clk   -- CPU Clock Out       (1/4)
636
  );
637
 
638
-----------------------------------------
639
--
640
-- LED Flasher
641
--
642
-----------------------------------------
643 19 dilbert57
 
644 108 davidgb
my_LED_flasher : flasher port map (
645
    clk      => cpu_clk,
646
    rst      => cpu_rst,
647
    LED      => LED
648
  );
649
 
650
 
651 19 dilbert57
----------------------------------------
652
--
653
-- CPU09 CPU Core
654
--
655
----------------------------------------
656
my_cpu : cpu09  port map (
657
         clk         => cpu_clk,
658 108 davidgb
    rst       => cpu_rst,
659
    vma       => cpu_vma,
660
    addr      => cpu_addr(15 downto 0),
661 19 dilbert57
    rw       => cpu_rw,
662
    data_in   => cpu_data_in,
663
         data_out  => cpu_data_out,
664
         halt      => cpu_halt,
665
         hold      => cpu_hold,
666
         irq       => cpu_irq,
667
         nmi       => cpu_nmi,
668
         firq      => cpu_firq
669
  );
670
 
671
----------------------------------------
672
--
673
-- Dynamic Address Translation Registers
674
--
675
----------------------------------------
676
my_dat : dat_ram port map (
677
    clk        => cpu_clk,
678 108 davidgb
         rst        => cpu_rst,
679 19 dilbert57
         cs         => dat_cs,
680
         rw         => cpu_rw,
681
         addr_hi    => cpu_addr(15 downto 12),
682
         addr_lo    => cpu_addr(3 downto 0),
683
    data_in    => cpu_data_out,
684
         data_out   => dat_addr(7 downto 0)
685
         );
686
 
687
----------------------------------------
688
--
689 108 davidgb
-- SBUG / KBUG / SYS09BUG Monitor ROM
690
--
691
----------------------------------------
692
my_rom : SYS09BUG_F800 port map (
693
       clk      => cpu_clk,
694
                 rst      => cpu_rst,
695
                 cs       => rom_cs,
696
       addr     => cpu_addr(10 downto 0),
697
                 rw       => '1',
698
                 data_in  => cpu_data_out,
699
       data_out => rom_data_out
700
    );
701
 
702
----------------------------------------
703
--
704 19 dilbert57
-- ACIA/UART Serial interface
705
--
706
----------------------------------------
707 108 davidgb
my_acia  : acia6850 port map (
708 19 dilbert57
         clk         => cpu_clk,
709 108 davidgb
         rst       => cpu_rst,
710 19 dilbert57
    cs        => uart_cs,
711 108 davidgb
    addr      => cpu_addr(0),
712 19 dilbert57
         rw        => cpu_rw,
713 108 davidgb
         data_in   => cpu_data_out,
714
         data_out  => uart_data_out,
715 19 dilbert57
    irq       => uart_irq,
716
         RxC       => uart_clk,
717
         TxC       => uart_clk,
718
         RxD       => rxbit,
719
         TxD       => txbit,
720
         DCD_n     => dcd_n,
721
         CTS_n     => cts_n,
722
         RTS_n     => rts_n
723
         );
724
 
725
----------------------------------------
726
--
727
-- ACIA Clock
728
--
729
----------------------------------------
730
my_ACIA_Clock : ACIA_Clock
731
  generic map(
732 108 davidgb
    SYS_CLK_FREQ  => SYS_CLK_FREQ,
733
         ACIA_CLK_FREQ => ACIA_CLK_FREQ
734 19 dilbert57
  )
735
  port map(
736 108 davidgb
    clk        => sys_clk,
737 19 dilbert57
    acia_clk   => uart_clk
738
  );
739
 
740
----------------------------------------
741
--
742
-- PS/2 Keyboard Interface
743
--
744
----------------------------------------
745
my_keyboard : keyboard
746
   generic map (
747 108 davidgb
     KBD_CLK_FREQ => CPU_CLK_FREQ
748 19 dilbert57
        )
749
   port map(
750 108 davidgb
          clk          => cpu_clk,
751
          rst          => cpu_rst,
752
          cs           => kbd_cs,
753
          addr         => cpu_addr(0),
754
          rw           => cpu_rw,
755
          data_in      => cpu_data_out(7 downto 0),
756
          data_out     => kbd_data_out(7 downto 0),
757
          irq          => kbd_irq,
758
          kbd_clk      => kb_clock,
759
          kbd_data     => kb_data
760 19 dilbert57
        );
761 108 davidgb
 
762
 
763
------------------------------------------------
764
--
765
-- Video Display Unit instantiation ($E030-$E03F)
766
--
767
-------------------------------------------------
768
my_vdu : vdu8
769
  generic map(
770
    VGA_CLK_FREQ           => VGA_CLK_FREQ, -- 25MHZ
771
    VGA_HOR_CHARS          => 80, -- CHARACTERS 25.6us
772
    VGA_HOR_CHAR_PIXELS    => 8,  -- PIXELS 0.32us
773
    VGA_HOR_FRONT_PORCH    => 16, -- PIXELS 0.64us
774
    VGA_HOR_SYNC           => 96, -- PIXELS 3.84us
775
    VGA_HOR_BACK_PORCH     => 48, -- PIXELS 1.92us
776
    VGA_VER_CHARS          => 25, -- CHARACTERS 12.8ms
777
    VGA_VER_CHAR_LINES     => 16, -- LINES 0.512ms
778
    VGA_VER_FRONT_PORCH    => 10, -- LINES 0.320ms
779
    VGA_VER_SYNC           => 2,  -- LINES 0.064ms
780
    VGA_VER_BACK_PORCH     => 34  -- LINES 1.088ms
781
  )
782
  port map(
783
 
784
    -- CPU Control Registers interface
785
    vdu_clk       => cpu_clk,                                    -- 12.5 MHz System Clock in
786
    vdu_rst       => cpu_rst,
787
    vdu_cs        => vdu_cs,
788
    vdu_rw        => cpu_rw,
789
    vdu_addr      => cpu_addr(2 downto 0),
790
    vdu_data_in   => cpu_data_out,
791
    vdu_data_out  => vdu_data_out,
792
 
793
    -- vga port connections
794
    vga_clk       => vga_clk,                                    -- 25 MHz VDU pixel clock
795
    vga_red_o     => vga_red,
796
    vga_green_o   => vga_green,
797
    vga_blue_o    => vga_blue,
798
    vga_hsync_o   => h_drive,
799
    vga_vsync_o   => v_drive
800
  );
801 19 dilbert57
 
802
----------------------------------------
803
--
804
-- Timer Module
805
--
806
----------------------------------------
807
my_timer  : timer port map (
808
    clk       => cpu_clk,
809 108 davidgb
         rst       => cpu_rst,
810
    cs        => tmr_cs,
811 19 dilbert57
         rw        => cpu_rw,
812
    addr      => cpu_addr(0),
813
         data_in   => cpu_data_out,
814 108 davidgb
         data_out  => tmr_data_out,
815
    irq       => tmr_irq
816 19 dilbert57
    );
817
 
818
----------------------------------------
819
--
820
-- Bus Trap Interrupt logic
821
--
822
----------------------------------------
823
my_trap : trap port map (
824
         clk        => cpu_clk,
825 108 davidgb
    rst        => cpu_rst,
826 19 dilbert57
    cs         => trap_cs,
827
    rw         => cpu_rw,
828
         vma        => cpu_vma,
829
    addr       => cpu_addr,
830
    data_in    => cpu_data_out,
831
         data_out   => trap_data_out,
832
         irq        => trap_irq
833
    );
834
 
835
----------------------------------------
836
--
837
-- Parallel I/O Port
838
--
839
----------------------------------------
840
my_ioport  : ioport port map (
841
         clk       => cpu_clk,
842 108 davidgb
    rst       => cpu_rst,
843
    cs        => pio_cs,
844 19 dilbert57
    rw        => cpu_rw,
845
    addr      => cpu_addr(1 downto 0),
846
    data_in   => cpu_data_out,
847 108 davidgb
         data_out  => pio_data_out,
848 19 dilbert57
         porta_io  => porta,
849
         portb_io  => portb
850
         );
851 108 davidgb
 
852 19 dilbert57
 
853 108 davidgb
------------------------------------------------
854
--
855
-- 16 bit Peripheral Bus interface ($E100-$E1FF)
856
--
857
------------------------------------------------
858
my_pb : peripheral_bus port map (
859
    --
860
    -- CPU Interface signals
861
    --
862
    clk       => cpu_clk,
863
    rst       => cpu_rst,
864
    cs        => pb_cs,
865
    addr      => cpu_addr(7 downto 0),
866
    rw        => cpu_rw,
867
    data_in   => cpu_data_out,
868
    data_out  => pb_data_out,
869
    hold      => pb_hold,
870
    --
871
    -- Peripheral Bus Interface Signals
872
    -- IO + ($00 - $FF) 
873
    --
874
    pb_rd_n   => cf_rd_n,
875
    pb_wr_n   => cf_wr_n,
876
    pb_addr(2 downto 0) => cf_a,
877
    pb_addr(4 downto 3) => open,
878
    pb_data   => cf_d,
879
 
880
    -- Peripheral chip selects on Peripheral Bus 
881
    ide_cs    => cf_cs,
882
    eth_cs    => open,
883
    sl1_cs    => open,
884
    sl2_cs    => open
885 19 dilbert57
    );
886 108 davidgb
 
887
-----------------------------------------------
888
--
889
-- BED SRAM interface (256KBytes) ($0000-$DFFF)
890
--
891
-----------------------------------------------
892
my_bed_sram : BED_SRAM port map (
893
    --
894
    -- CPU Interface signals
895
    --
896
    clk       => vga_clk,                        -- VGA Clock (twice the CPU clock)
897
    rst       => cpu_rst,                        -- Reset input (active high)
898
    cs        => ram_cs,                         -- RAM Chip Select
899
    addr(17 downto 12) => dat_addr( 5 downto 0), -- High RAM address goes to the DAT
900
    addr(11 downto  0) => cpu_addr(11 downto 0), -- Low RAM address goes to the CPU
901
    rw        => cpu_rw,                         -- Read / Not Write
902
    data_in   => cpu_data_out,                   -- Data Bus In 
903
    data_out  => ram_data_out,                   -- Data Bus Out
904
    --
905
    -- BED_SRAM Interface Signals
906
    --
907
    ram_csn   => ram_csn,
908
    ram_wrln  => ram_wrln,
909
    ram_wrun  => ram_wrun,
910
    ram_addr  => ram_addr,
911
    ram_data  => ram_data
912
    );
913 19 dilbert57
 
914
----------------------------------------------------------------------
915
--
916
-- Process to decode memory map
917
--
918
----------------------------------------------------------------------
919
 
920 108 davidgb
mem_decode: process( dat_addr,
921 19 dilbert57
                     cpu_addr, cpu_rw, cpu_vma,
922
                                              rom_data_out,
923
                                                   uart_data_out,
924 108 davidgb
                                                        kbd_data_out,
925 19 dilbert57
                                                        vdu_data_out,
926 108 davidgb
                                                   tmr_data_out,
927
                                                        trap_data_out,
928
                                                        pio_data_out,
929
                                                        bus_data,
930
                     pb_data_out,
931
                                                        ram_data_out )
932 19 dilbert57
begin
933 108 davidgb
  rom_cs   <= '0';              -- read ROM
934
  dat_cs   <= '0';              -- write DAT
935
  ram_cs   <= '0';
936
  uart_cs  <= '0';
937
  kbd_cs   <= '0';
938
  vdu_cs   <= '0';
939
  tmr_cs   <= '0';
940
  trap_cs  <= '0';
941
  pio_cs   <= '0';
942
  bus_cs   <= '0';
943
  pb_cs    <= '0';
944
 
945
  --
946
  -- ROM / DAT $FF00 - $FFFF
947
  -- 
948
  if cpu_addr( 15 downto 8 ) = "11111111" then
949
    cpu_data_in <= rom_data_out;
950
    rom_cs      <= cpu_vma;              -- read ROM
951
    dat_cs      <= cpu_vma;              -- write DAT
952
  else
953
    --
954
    -- Decode on 4K Byte boundaries
955
    --
956
    case dat_addr(3 downto 0) is
957
    when "1111" => -- $F000 - $FFFF
958
      if cpu_addr(11) = '1' then
959
        --
960
        -- SBUG/KBUG/SYS09BUG Monitor ROM $F800 - $FFFF
961
        --
962
        cpu_data_in <= rom_data_out;
963
        rom_cs      <= cpu_vma;
964
      else
965
        --
966
        -- SRAM $F000 - $F7FF
967
        -- Future use DMAF-2 Floppy Disk controller
968
        -- 
969
        cpu_data_in <= ram_data_out;
970
        ram_cs      <= cpu_vma;
971
      end if;
972
    --
973
    -- IO Devices $EXXX - $EXXX
974
    --
975
    when "1110" =>
976
      --
977
      -- Decode on 256 Byte boundaries
978
      -- IO device $E0XX - $E7XX
979
      --
980
      case cpu_addr(10 downto 8) is
981
      when "000" =>
982
         --
983
         -- Decode I/O Devices on 16 byte boundaries
984
         -- IO device $E00X - $E0FX
985
         --
986 19 dilbert57
                   case cpu_addr(7 downto 4) is
987
                        --
988
                        -- UART / ACIA $E000
989
                        --
990
                        when "0000" => -- $E000
991
                     cpu_data_in <= uart_data_out;
992
                          uart_cs     <= cpu_vma;
993
 
994
                        --
995
                        -- WD1771 FDC sites at $E010-$E01F
996
                        --
997
 
998
         --
999
         -- Keyboard port $E020 - $E02F
1000
                        --
1001
                        when "0010" => -- $E020
1002 108 davidgb
           cpu_data_in <= kbd_data_out;
1003
                          kbd_cs      <= cpu_vma;
1004 19 dilbert57
 
1005
         --
1006
         -- VDU port $E030 - $E03F
1007
                        --
1008
                        when "0011" => -- $E030
1009
           cpu_data_in <= vdu_data_out;
1010
                          vdu_cs      <= cpu_vma;
1011
 
1012
         --
1013 108 davidgb
                        -- Reserved $E040 - $E04F
1014
         --
1015 19 dilbert57
 
1016
         --
1017
         -- Timer $E050 - $E05F
1018
                        --
1019
                        when "0101" => -- $E050
1020 108 davidgb
           cpu_data_in <= tmr_data_out;
1021
           tmr_cs    <= cpu_vma;
1022 19 dilbert57
 
1023
         --
1024
         -- Bus Trap Logic $E060 - $E06F
1025
                        --
1026
                        when "0110" => -- $E060
1027
           cpu_data_in <= trap_data_out;
1028
                          trap_cs     <= cpu_vma;
1029
 
1030
         --
1031 108 davidgb
         -- Parallel I/O port $E070 - $E07F
1032 19 dilbert57
                        --
1033
                        when "0111" => -- $E070
1034 108 davidgb
           cpu_data_in <= pio_data_out;
1035
                          pio_cs       <= cpu_vma;
1036
 
1037
         --
1038
         -- Undefined / Extension Bus $E080 - $E0FF
1039
         --
1040
                        when others => -- $E080 to $E0FF
1041 19 dilbert57
           cpu_data_in <= bus_data;
1042 108 davidgb
           bus_cs      <= cpu_vma;
1043
                   end case;
1044
 
1045
      --
1046
      -- Peripheral Bus $E100 - $E1FF
1047
      --
1048
      when "001" =>
1049
        cpu_data_in <= pb_data_out;
1050
        pb_cs       <= cpu_vma;
1051
 
1052
      --
1053
      -- Map RAM at $E200 - $EFFF Just in case we need driver space.
1054
      --
1055
      when others =>
1056
         cpu_data_in <= ram_data_out;
1057
         ram_cs      <= cpu_vma;
1058
      end case;
1059
    --
1060
    -- Everything else is RAM $0000 - $DFFF
1061
    --
1062
    when others =>
1063
      cpu_data_in <= ram_data_out;
1064
      ram_cs      <= cpu_vma;
1065
    end case;
1066
  end if;
1067 19 dilbert57
end process;
1068
 
1069
--
1070
-- Interrupts and other bus control signals
1071
--
1072 108 davidgb
interrupts : process( rst_n, pb_hold,
1073
                      uart_irq, trap_irq, tmr_irq, kbd_irq )
1074 19 dilbert57
begin
1075 108 davidgb
         cpu_rst   <= not rst_n; -- CPU reset is active high
1076
    cpu_irq   <= uart_irq or kbd_irq;
1077 19 dilbert57
         cpu_nmi   <= trap_irq;
1078 108 davidgb
         cpu_firq  <= tmr_irq;
1079 19 dilbert57
         cpu_halt  <= '0';
1080 108 davidgb
         cpu_hold  <= pb_hold;
1081 19 dilbert57
end process;
1082
 
1083
--
1084
-- CPU bus signals
1085
--
1086 108 davidgb
my_bus : process( cpu_clk, cpu_rst, cpu_rw, cpu_addr, cpu_data_out )
1087 19 dilbert57
begin
1088
        bus_clk   <= cpu_clk;
1089 108 davidgb
   bus_reset <= cpu_rst;
1090 19 dilbert57
        bus_rw    <= cpu_rw;
1091
   bus_addr  <= cpu_addr;
1092
        if( cpu_rw = '1' ) then
1093 108 davidgb
           bus_data <= (others => 'Z');
1094 19 dilbert57
   else
1095
           bus_data <= cpu_data_out;
1096
   end if;
1097
end process;
1098
 
1099
--
1100
-- Assign VDU VGA colour output
1101
-- only 8 colours are handled.
1102
--
1103
my_vga_out: process( vga_red, vga_green, vga_blue )
1104
begin
1105
           red_lo   <= vga_red;
1106
      red_hi   <= vga_red;
1107
      green_lo <= vga_green;
1108
      green_hi <= vga_green;
1109
      blue_lo  <= vga_blue;
1110
      blue_hi  <= vga_blue;
1111
end process;
1112 108 davidgb
 
1113
--
1114
-- CF card chip selects ($E100 - $E13F)
1115
-- Located on peripheral bus
1116
--
1117
my_cf_decode: process( cpu_rst, cpu_addr, cf_cs )
1118
begin
1119
 
1120
  cf_cs0_n  <= not( cf_cs and not cpu_addr(4));
1121
  cf_cs1_n  <= not( cf_cs and     cpu_addr(4));
1122
  cf_rst_n  <= not cpu_rst;
1123
 
1124
end process;
1125 19 dilbert57
 
1126
end rtl; --===================== End of architecture =======================--
1127
 

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