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dilbert57 |
#PACE: Start of Constraints generated by PACE
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#PACE: Start of PACE I/O Pin Assignments
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NET "SysClk" LOC = "T9" ;
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#
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# PUSH BUTTONS
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#
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NET "Reset_sw" LOC = "L14" ;
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NET "nmi_sw" LOC = "L13" ;
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#
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# LEDs
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#
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NET "leds<0>" LOC = "K12";
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NET "leds<1>" LOC = "P14";
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NET "leds<2>" LOC = "L12";
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NET "leds<3>" LOC = "N14";
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NET "leds<4>" LOC = "P13";
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NET "leds<5>" LOC = "N12";
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NET "leds<6>" LOC = "P12";
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NET "leds<7>" LOC = "P11";
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#
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# Switches
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#
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NET "switches<0>" LOC = "F12";
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NET "switches<1>" LOC = "G12";
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NET "switches<2>" LOC = "H14";
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NET "switches<3>" LOC = "H13";
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NET "switches<4>" LOC = "J14";
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NET "switches<5>" LOC = "J13";
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NET "switches<6>" LOC = "K14";
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NET "switches<7>" LOC = "K13";
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#
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# PS/2 KEYBOARD
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#
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NET "ps2c" LOC = "M16" ;
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NET "ps2d" LOC = "M15" ;
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#
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# UART
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#
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NET "rxd" LOC = "T13" ;
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NET "txd" LOC = "R13" ;
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#
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# VDU
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#
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NET "red" LOC = "R12" ;
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NET "green" LOC = "T12" ;
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NET "blue" LOC = "R11" ;
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NET "hs" LOC = "R9" ;
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NET "vs" LOC = "T10" ;
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#
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# 7 SEGMENT DISPLAY
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#
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NET "segments<0>" LOC = "E14";
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NET "segments<1>" LOC = "G13";
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NET "segments<2>" LOC = "N15";
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NET "segments<3>" LOC = "P15";
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NET "segments<4>" LOC = "R16";
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NET "segments<5>" LOC = "F13";
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NET "segments<6>" LOC = "N16";
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NET "segments<7>" LOC = "P16";
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NET "digits<0>" LOC = "D14";
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NET "digits<1>" LOC = "G14";
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NET "digits<2>" LOC = "F14";
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NET "digits<3>" LOC = "E13";
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#
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# RAM Address bus
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#
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NET "ram_addr<0>" LOC = "L5" ;
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NET "ram_addr<1>" LOC = "N3" ;
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NET "ram_addr<2>" LOC = "M4" ;
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NET "ram_addr<3>" LOC = "M3" ;
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NET "ram_addr<4>" LOC = "L4" ;
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NET "ram_addr<5>" LOC = "G4" ;
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NET "ram_addr<6>" LOC = "F3" ;
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NET "ram_addr<7>" LOC = "F4" ;
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NET "ram_addr<8>" LOC = "E3" ;
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NET "ram_addr<9>" LOC = "E4" ;
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NET "ram_addr<10>" LOC = "G5" ;
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NET "ram_addr<11>" LOC = "H3" ;
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NET "ram_addr<12>" LOC = "H4" ;
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NET "ram_addr<13>" LOC = "J4" ;
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NET "ram_addr<14>" LOC = "J3" ;
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NET "ram_addr<15>" LOC = "K3" ;
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NET "ram_addr<16>" LOC = "K5" ;
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NET "ram_addr<17>" LOC = "L3" ;
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NET "ram_oen" LOC = "K4" ;
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NET "ram_wen" LOC = "G3" ;
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#
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# RAM1
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#
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NET "ram1_cen" LOC = "P7" ;
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NET "ram1_lbn" LOC = "P6" ;
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NET "ram1_ubn" LOC = "T4" ;
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NET "ram1_data<0>" LOC = "N7" ;
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NET "ram1_data<1>" LOC = "T8" ;
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NET "ram1_data<2>" LOC = "R6" ;
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NET "ram1_data<3>" LOC = "T5" ;
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NET "ram1_data<4>" LOC = "R5" ;
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NET "ram1_data<5>" LOC = "C2" ;
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NET "ram1_data<6>" LOC = "C1" ;
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NET "ram1_data<7>" LOC = "B1" ;
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NET "ram1_data<8>" LOC = "D3" ;
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NET "ram1_data<9>" LOC = "P8" ;
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NET "ram1_data<10>" LOC = "F2" ;
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NET "ram1_data<11>" LOC = "H1" ;
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NET "ram1_data<12>" LOC = "J2" ;
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NET "ram1_data<13>" LOC = "L2" ;
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NET "ram1_data<14>" LOC = "P1" ;
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NET "ram1_data<15>" LOC = "R1" ;
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#
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# RAM2
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#
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NET "ram2_cen" LOC = "N5" ;
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NET "ram2_lbn" LOC = "P5" ;
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NET "ram2_ubn" LOC = "R4" ;
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NET "ram2_data<0>" LOC = "P2" ;
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NET "ram2_data<1>" LOC = "N2" ;
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NET "ram2_data<2>" LOC = "M2" ;
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NET "ram2_data<3>" LOC = "K1" ;
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NET "ram2_data<4>" LOC = "J1" ;
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NET "ram2_data<5>" LOC = "G2" ;
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NET "ram2_data<6>" LOC = "E1" ;
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NET "ram2_data<7>" LOC = "D1" ;
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NET "ram2_data<8>" LOC = "D2" ;
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NET "ram2_data<9>" LOC = "E2" ;
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NET "ram2_data<10>" LOC = "G1" ;
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NET "ram2_data<11>" LOC = "F5" ;
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NET "ram2_data<12>" LOC = "C3" ;
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NET "ram2_data<13>" LOC = "K2" ;
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NET "ram2_data<14>" LOC = "M1" ;
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NET "ram2_data<15>" LOC = "N1" ;
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#
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# Timing Groups
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#
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INST "ram_oen" TNM = "gram_rw";
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INST "ram_wen" TNM = "gram_rw";
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INST "ram_addr<0>" TNM = "gram_addr";
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INST "ram_addr<1>" TNM = "gram_addr";
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INST "ram_addr<2>" TNM = "gram_addr";
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INST "ram_addr<3>" TNM = "gram_addr";
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INST "ram_addr<4>" TNM = "gram_addr";
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INST "ram_addr<5>" TNM = "gram_addr";
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INST "ram_addr<6>" TNM = "gram_addr";
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INST "ram_addr<7>" TNM = "gram_addr";
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INST "ram_addr<8>" TNM = "gram_addr";
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INST "ram_addr<9>" TNM = "gram_addr";
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INST "ram_addr<10>" TNM = "gram_addr";
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INST "ram_addr<11>" TNM = "gram_addr";
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INST "ram_addr<12>" TNM = "gram_addr";
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INST "ram_addr<13>" TNM = "gram_addr";
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INST "ram_addr<14>" TNM = "gram_addr";
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INST "ram_addr<15>" TNM = "gram_addr";
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INST "ram_addr<16>" TNM = "gram_addr";
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INST "ram_addr<17>" TNM = "gram_addr";
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#
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INST "ram1_cen" TNM = "gram_cs";
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INST "ram1_lbn" TNM = "gram_ds";
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INST "ram1_ubn" TNM = "gram_ds";
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INST "ram1_data<0>" TNM = "gram_data";
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INST "ram1_data<1>" TNM = "gram_data";
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INST "ram1_data<2>" TNM = "gram_data";
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INST "ram1_data<3>" TNM = "gram_data";
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INST "ram1_data<4>" TNM = "gram_data";
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INST "ram1_data<5>" TNM = "gram_data";
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INST "ram1_data<6>" TNM = "gram_data";
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INST "ram1_data<7>" TNM = "gram_data";
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INST "ram1_data<8>" TNM = "gram_data";
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INST "ram1_data<9>" TNM = "gram_data";
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INST "ram1_data<10>" TNM = "gram_data";
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INST "ram1_data<11>" TNM = "gram_data";
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INST "ram1_data<12>" TNM = "gram_data";
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INST "ram1_data<13>" TNM = "gram_data";
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INST "ram1_data<14>" TNM = "gram_data";
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INST "ram1_data<15>" TNM = "gram_data";
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#
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INST "ram2_cen" TNM = "gram_cs";
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INST "ram2_lbn" TNM = "gram_ds";
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INST "ram2_ubn" TNM = "gram_ds";
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INST "ram2_data<0>" TNM = "gram_data";
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INST "ram2_data<1>" TNM = "gram_data";
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INST "ram2_data<2>" TNM = "gram_data";
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INST "ram2_data<3>" TNM = "gram_data";
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INST "ram2_data<4>" TNM = "gram_data";
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INST "ram2_data<5>" TNM = "gram_data";
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INST "ram2_data<6>" TNM = "gram_data";
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INST "ram2_data<7>" TNM = "gram_data";
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INST "ram2_data<8>" TNM = "gram_data";
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INST "ram2_data<9>" TNM = "gram_data";
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INST "ram2_data<10>" TNM = "gram_data";
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INST "ram2_data<11>" TNM = "gram_data";
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INST "ram2_data<12>" TNM = "gram_data";
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INST "ram2_data<13>" TNM = "gram_data";
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INST "ram2_data<14>" TNM = "gram_data";
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INST "ram2_data<15>" TNM = "gram_data";
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#
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# Timing Constraints
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#
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NET "sysclk" TNM_NET = "sysclk";
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TIMESPEC "TS_sysclk" = PERIOD "sysclk" 20 ns LOW 50 %;
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TIMEGRP "gram_cs" OFFSET = OUT 20 ns AFTER "sysclk";
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TIMEGRP "gram_ds" OFFSET = OUT 20 ns AFTER "sysclk";
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TIMEGRP "gram_rw" OFFSET = OUT 20 ns AFTER "sysclk";
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TIMEGRP "gram_addr" OFFSET = OUT 20 ns AFTER "sysclk";
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TIMEGRP "gram_data" OFFSET = OUT 20 ns AFTER "sysclk";
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TIMEGRP "gram_data" OFFSET = IN 10 ns BEFORE "sysclk";
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#PACE: Start of PACE Area Constraints
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#PACE: Start of PACE Prohibit Constraints
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#PACE: End of Constraints generated by PACE
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