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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_Atlys/] [btn_debounce.vhd] - Blame information for rev 185

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1 185 davidgb
----------------------------------------------------------------------------
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--      btn_debounce.vhd -- Button Debouncer
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----------------------------------------------------------------------------
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-- Author:  Sam Bobrowicz
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--          Copyright 2011 Digilent, Inc.
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----------------------------------------------------------------------------
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--
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----------------------------------------------------------------------------
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--      This component is used to debounce signals generated by external push
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-- buttons. It is designed to independently debounce 5 Push button signals.
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-- Debouncing is done by only registering a change in a button state if 
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-- it remains constant for 2^16 clock cycles. 
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--                                      
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-- Port Descriptions:
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--
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--   BTN_I - The input button signals
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--    CLK  - Behavior is optimized for a 100 MHz clock
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--   BTN_O - The debounced button signals
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--                                                                                      
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----------------------------------------------------------------------------
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--
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----------------------------------------------------------------------------
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-- Revision History:
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--  08/08/2011(SamB): Created using Xilinx Tools 13.2
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----------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.std_logic_unsigned.all;
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entity btn_debounce is
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    Port ( BTN_I : in  STD_LOGIC_VECTOR (4 downto 0);
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           CLK : in  STD_LOGIC;
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           BTN_O : out  STD_LOGIC_VECTOR (4 downto 0));
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end btn_debounce;
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architecture Behavioral of btn_debounce is
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constant CNTR_MAX : std_logic_vector(15 downto 0) := (others => '1');
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signal btn0_cntr : std_logic_vector(15 downto 0) := (others => '0');
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signal btn1_cntr : std_logic_vector(15 downto 0) := (others => '0');
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signal btn2_cntr : std_logic_vector(15 downto 0) := (others => '0');
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signal btn3_cntr : std_logic_vector(15 downto 0) := (others => '0');
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signal btn4_cntr : std_logic_vector(15 downto 0) := (others => '0');
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signal btn0_reg : std_logic := '0';
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signal btn1_reg : std_logic := '0';
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signal btn2_reg : std_logic := '0';
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signal btn3_reg : std_logic := '0';
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signal btn4_reg : std_logic := '0';
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begin
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btn0_debounce_process : process (CLK)
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begin
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        if (rising_edge(CLK)) then
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                if (btn0_cntr = CNTR_MAX) then
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                        btn0_reg <= not(btn0_reg);
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                end if;
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        end if;
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end process;
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btn0_counter_process : process (CLK)
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begin
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        if (rising_edge(CLK)) then
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                if ((btn0_reg = '1') xor (BTN_I(0) = '1')) then
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                        if (btn0_cntr = CNTR_MAX) then
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                                btn0_cntr <= (others => '0');
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                        else
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                                btn0_cntr <= btn0_cntr + 1;
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                        end if;
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                else
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                        btn0_cntr <= (others => '0');
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                end if;
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        end if;
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end process;
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btn1_debounce_process : process (CLK)
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begin
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        if (rising_edge(CLK)) then
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                if (btn1_cntr = CNTR_MAX) then
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                        btn1_reg <= not(btn1_reg);
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                end if;
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        end if;
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end process;
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btn1_counter_process : process (CLK)
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begin
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        if (rising_edge(CLK)) then
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                if ((btn1_reg = '1') xor (BTN_I(1) = '1')) then
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                        if (btn1_cntr = CNTR_MAX) then
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                                btn1_cntr <= (others => '0');
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                        else
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                                btn1_cntr <= btn1_cntr + 1;
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                        end if;
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                else
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                        btn1_cntr <= (others => '0');
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                end if;
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        end if;
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end process;
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btn2_debounce_process : process (CLK)
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begin
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        if (rising_edge(CLK)) then
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                if (btn2_cntr = CNTR_MAX) then
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                        btn2_reg <= not(btn2_reg);
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                end if;
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        end if;
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end process;
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btn2_counter_process : process (CLK)
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begin
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        if (rising_edge(CLK)) then
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                if ((btn2_reg = '1') xor (BTN_I(2) = '1')) then
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                        if (btn2_cntr = CNTR_MAX) then
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                                btn2_cntr <= (others => '0');
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                        else
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                                btn2_cntr <= btn2_cntr + 1;
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                        end if;
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                else
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                        btn2_cntr <= (others => '0');
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                end if;
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        end if;
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end process;
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btn3_debounce_process : process (CLK)
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begin
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        if (rising_edge(CLK)) then
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                if (btn3_cntr = CNTR_MAX) then
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                        btn3_reg <= not(btn3_reg);
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                end if;
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        end if;
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end process;
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btn3_counter_process : process (CLK)
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begin
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        if (rising_edge(CLK)) then
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                if ((btn3_reg = '1') xor (BTN_I(3) = '1')) then
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                        if (btn3_cntr = CNTR_MAX) then
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                                btn3_cntr <= (others => '0');
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                        else
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                                btn3_cntr <= btn3_cntr + 1;
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                        end if;
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                else
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                        btn3_cntr <= (others => '0');
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                end if;
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        end if;
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end process;
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btn4_debounce_process : process (CLK)
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begin
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        if (rising_edge(CLK)) then
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                if (btn4_cntr = CNTR_MAX) then
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                        btn4_reg <= not(btn4_reg);
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                end if;
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        end if;
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end process;
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btn4_counter_process : process (CLK)
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begin
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        if (rising_edge(CLK)) then
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                if ((btn4_reg = '1') xor (BTN_I(4) = '1')) then
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                        if (btn4_cntr = CNTR_MAX) then
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                                btn4_cntr <= (others => '0');
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                        else
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                                btn4_cntr <= btn4_cntr + 1;
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                        end if;
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                else
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                        btn4_cntr <= (others => '0');
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                end if;
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        end if;
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end process;
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BTN_O <= btn4_reg & btn3_reg & btn2_reg & btn1_reg & btn0_reg;
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end Behavioral;
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