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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_Atlys/] [system09.vhd] - Blame information for rev 171

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1 141 davidgb
--===========================================================================----
2
--
3
--  S Y N T H E Z I A B L E    System09 - SOC.
4
--
5
--  www.OpenCores.Org - February 2007
6
--  This core adheres to the GNU public license  
7
--
8
-- File name      : System09_Xess_XSA-3S1000.vhd
9
--
10
-- Purpose        : Top level file for 6809 compatible system on a chip
11
--                  Designed with Xilinx XC3S1000 Spartan 3 FPGA.
12
--                  Implemented With XESS XSA-3S1000 FPGA board.
13
--                  *** Note ***
14
--                  This configuration can run Flex9 however it only has
15
--                  32k bytes of user memory and the VDU is monochrome
16
--                  The design needs to be updated to use the SDRAM on 
17
--                  the XSA-3S1000 board.
18
--                  This configuration also lacks a DAT so cannot use
19
--                  the RAM Disk features of SYS09BUG.
20
--
21
-- Dependencies   : ieee.Std_Logic_1164
22
--                  ieee.std_logic_unsigned
23
--                  ieee.std_logic_arith
24
--                  ieee.numeric_std
25
--                  unisim.vcomponents
26
--
27
-- Uses           : mon_rom    (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
28
--                  cpu09      (cpu09.vhd)          CPU core
29
--                  ACIA_6850  (acia6850.vhd)      ACIA / UART
30
--                  ACIA_Clock (ACIA_Clock.vhd)      ACIA clock.
31
--                  timer      (timer.vhd)            Interrupt timer
32
--                  trap       (trap.vhd)             Bus condition trap logic
33
--                  flex_ram   (flex9_ram8k_b16.vhd)  Flex operating system
34
--                  ram_32K    (ram32k_b16.vhd)       32 KBytes of Block RAM
35
--                  
36
-- 
37
-- Author         : John E. Kent      
38
--                  dilbert57@opencores.org      
39
--
40
-- Memory Map     :
41
--
42
-- $0000 - User program RAM (32K Bytes)
43
-- $C000 - Flex Operating System memory (8K Bytes)
44
-- $E000 - ACIA (SWTPc)
45
-- $E010 - Reserved for FD1771 FDC (SWTPc)
46
-- $E050 - Timer
47
-- $E060 - Bus trap
48
-- $E070 - Reserced for Parallel I/O (B5-X300)
49
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
50
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
51
-- $F000 - Sys09Bug monitor Program (4K Bytes)
52
--
53
--===========================================================================----
54
--
55
-- Revision History:
56
--===========================================================================--
57
-- Version 0.1 - 20 March 2003
58
-- Version 0.2 - 30 March 2003
59
-- Version 0.3 - 29 April 2003
60
-- Version 0.4 - 29 June 2003
61
--
62
-- Version 0.5 - 19 July 2003
63
-- prints out "Hello World"
64
--
65
-- Version 0.6 - 5 September 2003
66
-- Runs SBUG
67
--
68
-- Version 1.0- 6 Sep 2003 - John Kent
69
-- Inverted SysClk
70
-- Initial release to Open Cores
71
--
72
-- Version 1.1 - 17 Jan 2004 - John Kent
73
-- Updated miniUart.
74
--
75
-- Version 1.2 - 25 Jan 2004 - John Kent
76
-- removed signals "test_alu" and "test_cc" 
77
-- Trap hardware re-instated.
78
--
79
-- Version 1.3 - 11 Feb 2004 - John Kent
80
-- Designed forked off to produce System09_VDU
81
-- Added VDU component
82
-- VDU runs at 25MHz and divides the clock by 2 for the CPU
83
-- UART Runs at 57.6 Kbps
84
--
85
-- Version 2.0 - 2 September 2004 - John Kent
86
-- ported to Digilent Xilinx Spartan3 starter board
87
-- removed Compact Flash and Trap Logic.
88
-- Replaced SBUG with KBug9s
89
--
90
-- Version 3.0 - 29th August 2006 - John Kent
91
-- Adapted to XSA-3S1000 board.
92
-- Removed DAT and miniUART.
93
-- Used 32KBytes of Block RAM.
94
--
95
-- Version 3.1 - 15th January 2007 - John Kent
96
-- Modified vdu8 interface
97
-- Added a clock divider
98
--
99
-- Version 3.2 - 25th February 2007 - John Kent
100
-- reinstated ACIA_6850 and ACIA_Clock
101
-- Updated VDU8 & Keyboard with generic parameters
102
-- Defined Constants for clock speed calculations
103
--
104
-- Version 3.3 - 1st July 2007 - John Kent
105
-- Made VDU mono to save on one RAMB16
106
-- Used distributed memory for Key Map ROM to save one RAMB16
107
-- Added Flex RAM at $C000 to $DFFF using 4 spare RAMB16s
108
-- Added timer and trap logic
109
-- Added IDE Interface for Compact Flash
110
-- Replaced KBug9s and stack with Sys09Bug.
111
--
112
-- Version 4.0 - 1st February 2008 - John kent
113
-- Replaced Block RAM with SDRAM Interface
114
-- Modified Hold timing for SDRAM
115
-- Added CF and Ethernet interface 
116
-- via the 16 bit peripheral bus at $E100
117
--
118
--===========================================================================--
119
library ieee;
120
   use ieee.std_logic_1164.all;
121
   use IEEE.STD_LOGIC_ARITH.ALL;
122
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
123
   use ieee.numeric_std.all;
124
library work;
125
   use work.common.all;
126
library unisim;
127 162 davidgb
   use unisim.vcomponents.all;
128 141 davidgb
 
129
entity system09 is
130
  port(
131
    CLKA         : in  Std_Logic;  -- 100MHz Clock input
132
    SW2_N        : in  Std_logic;  -- Master Reset input (active low)
133
    SW3_N        : in  Std_logic;  -- Non Maskable Interrupt input (active low)
134
 
135
    -- RS232 Port
136
    RS232_RXD    : in  Std_Logic;
137
    RS232_TXD    : out Std_Logic;
138
 
139
    -- Status 7 segment LED
140 148 davidgb
    S            : out std_logic_vector(7 downto 0)
141 141 davidgb
 
142
-- CPU Debug Interface signals
143
--    cpu_reset_o     : out Std_Logic;
144
--    cpu_clk_o       : out Std_Logic;
145
--    cpu_rw_o        : out std_logic;
146
--    cpu_vma_o       : out std_logic;
147
--    cpu_halt_o      : out std_logic;
148
--    cpu_hold_o      : out std_logic;
149
--    cpu_firq_o      : out std_logic;
150
--    cpu_irq_o       : out std_logic;
151
--    cpu_nmi_o       : out std_logic;
152
--    cpu_addr_o      : out std_logic_vector(15 downto 0);
153
--    cpu_data_in_o   : out std_logic_vector(7 downto 0);
154
--    cpu_data_out_o  : out std_logic_vector(7 downto 0);
155
 
156 148 davidgb
  );
157 141 davidgb
end system09;
158
 
159
-------------------------------------------------------------------------------
160
-- Architecture for System09
161
-------------------------------------------------------------------------------
162
architecture rtl of system09 is
163
 
164
  -----------------------------------------------------------------------------
165
  -- constants
166
  -----------------------------------------------------------------------------
167
 
168
  constant MEM_CLK_FREQ         : natural := 100_000; -- operating frequency of Memory in KHz
169
  constant SYS_CLK_DIV          : real    := 2.0;    -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
170
 
171 170 davidgb
  constant SYS_CLK_FREQ         : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000;  -- FPGA System Clock (in Hz)
172 141 davidgb
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
173
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
174
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
175
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
176
 
177
  constant TRESET               : natural := 300;      -- min initialization interval (us)
178
  constant RST_CYCLES           : natural := 1+(TRESET*(MEM_CLK_FREQ/1_000));  -- SDRAM power-on initialization interval
179
 
180
  type hold_state_type is ( hold_release_state, hold_request_state );
181
 
182
  -----------------------------------------------------------------------------
183
  -- Signals
184
  -----------------------------------------------------------------------------
185
  -- BOOT ROM
186
  signal rom_cs         : Std_logic;
187
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
188
 
189
  -- Flex Memory & Monitor Stack
190
  signal flex_cs        : Std_logic;
191
  signal flex_data_out  : Std_Logic_Vector(7 downto 0);
192
 
193
  -- ACIA/UART Interface signals
194
  signal acia_data_out  : Std_Logic_Vector(7 downto 0);
195
  signal acia_cs        : Std_Logic;
196
  signal acia_irq       : Std_Logic;
197
  signal acia_clk       : Std_Logic;
198
  signal rxd            : Std_Logic;
199
  signal txd            : Std_Logic;
200
  signal DCD_n          : Std_Logic;
201
  signal RTS_n          : Std_Logic;
202
  signal CTS_n          : Std_Logic;
203
 
204
  -- RAM
205 170 davidgb
  signal ram_cs         : std_logic;
206 141 davidgb
  signal ram_data_out   : std_logic_vector(7 downto 0);
207
 
208
  -- CPU Interface signals
209
  signal cpu_reset      : Std_Logic;
210
  signal cpu_clk        : Std_Logic;
211
  signal cpu_rw         : std_logic;
212
  signal cpu_vma        : std_logic;
213
  signal cpu_halt       : std_logic;
214
  signal cpu_hold       : std_logic;
215
  signal cpu_firq       : std_logic;
216
  signal cpu_irq        : std_logic;
217
  signal cpu_nmi        : std_logic;
218
  signal cpu_addr       : std_logic_vector(15 downto 0);
219
  signal cpu_data_in    : std_logic_vector(7 downto 0);
220
  signal cpu_data_out   : std_logic_vector(7 downto 0);
221
 
222
  -- Dynamic Address Translation
223
  signal dat_cs       : std_logic;
224
  signal dat_addr     : std_logic_vector(7 downto 0);
225
 
226
  -- timer
227
  signal timer_data_out : std_logic_vector(7 downto 0);
228
  signal timer_cs       : std_logic;
229
  signal timer_irq      : std_logic;
230
 
231
  -- trap
232
  signal trap_cs        : std_logic;
233
  signal trap_data_out  : std_logic_vector(7 downto 0);
234
  signal trap_irq       : std_logic;
235
 
236
  signal rst_i         : std_logic;     -- internal reset signal
237
  signal clk_i         : std_logic;     -- internal master clock signal
238 170 davidgb
 
239
  signal rs232_cts    :   Std_Logic;
240
  signal rs232_rts    :  Std_Logic;
241 148 davidgb
 
242 141 davidgb
  signal CountL        : std_logic_vector(23 downto 0);
243
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
244
  signal Clk25         : std_logic;
245
 
246
-----------------------------------------------------------------
247
--
248
-- CPU09 CPU core
249
--
250
-----------------------------------------------------------------
251
 
252
component cpu09
253
  port (
254
    clk:      in  std_logic;
255
    rst:      in  std_logic;
256
    vma:      out std_logic;
257
    addr:     out std_logic_vector(15 downto 0);
258
    rw:       out std_logic;     -- Asynchronous memory interface
259
    data_out: out std_logic_vector(7 downto 0);
260
    data_in:  in  std_logic_vector(7 downto 0);
261
    irq:      in  std_logic;
262
    firq:     in  std_logic;
263
    nmi:      in  std_logic;
264
    halt:     in  std_logic;
265
    hold:     in  std_logic
266
  );
267
end component;
268
 
269
----------------------------------------
270
--
271
-- 4K Block RAM Monitor ROM
272 148 davidgb
-- $F000 - $FFFF
273 141 davidgb
--
274
----------------------------------------
275 148 davidgb
 
276 141 davidgb
component mon_rom
277 148 davidgb
  Port (
278
    clk   : in  std_logic;
279
    rst   : in  std_logic;
280
    cs    : in  std_logic;
281
    rw    : in  std_logic;
282
    addr  : in  std_logic_vector (11 downto 0);
283
    data_out : out std_logic_vector (7 downto 0);
284
    data_in : in  std_logic_vector (7 downto 0)
285
  );
286 141 davidgb
end component;
287
 
288
----------------------------------------
289
--
290
-- 8KBytes Block RAM for FLEX9
291
-- $C000 - $DFFF
292
--
293
----------------------------------------
294 148 davidgb
 
295 141 davidgb
component flex_ram
296
  Port (
297
    clk      : in  std_logic;
298
    rst      : in  std_logic;
299
    cs       : in  std_logic;
300
    rw       : in  std_logic;
301
    addr     : in  std_logic_vector (12 downto 0);
302
    data_out    : out std_logic_vector (7 downto 0);
303
    data_in    : in  std_logic_vector (7 downto 0)
304 148 davidgb
  );
305 141 davidgb
end component;
306 170 davidgb
 
307
----------------------------------------
308
--
309
-- 32KBytes Block RAM 0000
310
-- $0000 - $7FFF
311
--
312
----------------------------------------
313 141 davidgb
 
314 170 davidgb
component ram_32k
315
  Port (
316
    clk      : in  std_logic;
317
    rst      : in  std_logic;
318
    cs       : in  std_logic;
319
    rw       : in  std_logic;
320
    addr     : in  std_logic_vector (14 downto 0);
321
    data_out    : out std_logic_vector (7 downto 0);
322
    data_in    : in  std_logic_vector (7 downto 0)
323
  );
324
end component;
325
 
326
 
327 141 davidgb
-----------------------------------------------------------------
328
--
329
-- 6850 Compatible ACIA / UART
330
--
331
-----------------------------------------------------------------
332
 
333
component acia6850
334
  port (
335 148 davidgb
    clk      : in  Std_Logic;  -- System Clock
336
    rst      : in  Std_Logic;  -- Reset input (active high)
337
    cs       : in  Std_Logic;  -- miniUART Chip Select
338
    rw       : in  Std_Logic;  -- Read / Not Write
339
    addr     : in  Std_Logic;  -- Register Select
340
    data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
341
    data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
342
    irq      : out Std_Logic;  -- Interrupt
343
    RxC      : in  Std_Logic;  -- Receive Baud Clock
344
    TxC      : in  Std_Logic;  -- Transmit Baud Clock
345
    RxD      : in  Std_Logic;  -- Receive Data
346
    TxD      : out Std_Logic;  -- Transmit Data
347
    DCD_n    : in  Std_Logic;  -- Data Carrier Detect
348
    CTS_n    : in  Std_Logic;  -- Clear To Send
349
    RTS_n    : out Std_Logic   -- Request To send
350
  );
351 141 davidgb
end component;
352
 
353
-----------------------------------------------------------------
354
--
355
-- ACIA Clock divider
356
--
357
-----------------------------------------------------------------
358
 
359
component ACIA_Clock
360
  generic (
361 148 davidgb
    SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
362
    ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
363 141 davidgb
  );
364
  port (
365 148 davidgb
    clk      : in  Std_Logic;  -- System Clock Input
366
    ACIA_clk : out Std_logic   -- ACIA Clock output
367 141 davidgb
  );
368
end component;
369
 
370
----------------------------------------
371
--
372
-- Timer module
373
--
374
----------------------------------------
375
 
376
component timer
377
  port (
378 148 davidgb
    clk       : in std_logic;
379
    rst       : in std_logic;
380
    cs        : in std_logic;
381
    rw        : in std_logic;
382
    addr      : in std_logic;
383
    data_in   : in std_logic_vector(7 downto 0);
384
    data_out  : out std_logic_vector(7 downto 0);
385
    irq       : out std_logic
386
  );
387 141 davidgb
end component;
388
 
389
------------------------------------------------------------
390
--
391
-- Bus Trap logic
392
--
393
------------------------------------------------------------
394
 
395
component trap
396 148 davidgb
  port (
397 141 davidgb
    clk        : in  std_logic;
398
    rst        : in  std_logic;
399
    cs         : in  std_logic;
400
    rw         : in  std_logic;
401
    vma        : in  std_logic;
402
    addr       : in  std_logic_vector(15 downto 0);
403
    data_in    : in  std_logic_vector(7 downto 0);
404
    data_out   : out std_logic_vector(7 downto 0);
405
    irq        : out std_logic
406
  );
407
end component;
408
 
409
----------------------------------------
410
--
411
-- Dynamic Address Translation Registers
412
--
413
----------------------------------------
414 148 davidgb
 
415 141 davidgb
component dat_ram
416
  port (
417
    clk      : in  std_logic;
418
    rst      : in  std_logic;
419
    cs       : in  std_logic;
420
    rw       : in  std_logic;
421
    addr_lo  : in  std_logic_vector(3 downto 0);
422
    addr_hi  : in  std_logic_vector(3 downto 0);
423
    data_in  : in  std_logic_vector(7 downto 0);
424
    data_out : out std_logic_vector(7 downto 0)
425
  );
426
end component;
427
 
428
 
429
--
430
-- Clock buffer
431
--
432 148 davidgb
 
433 141 davidgb
component BUFG
434
   Port (
435
     i: in std_logic;
436
     o: out std_logic
437
  );
438
end component;
439
 
440
begin
441 169 davidgb
 
442
  clk_i <= CLKA;
443 141 davidgb
  -----------------------------------------------------------------------------
444
  -- Instantiation of internal components
445
  -----------------------------------------------------------------------------
446
 
447 148 davidgb
  my_cpu : cpu09
448
    port map (
449
      clk       => cpu_clk,
450
      rst       => cpu_reset,
451
      vma       => cpu_vma,
452
      addr      => cpu_addr(15 downto 0),
453
      rw        => cpu_rw,
454
      data_out  => cpu_data_out,
455
      data_in   => cpu_data_in,
456
      irq       => cpu_irq,
457
      firq      => cpu_firq,
458
      nmi       => cpu_nmi,
459
      halt      => cpu_halt,
460
      hold      => cpu_hold
461
    );
462 141 davidgb
 
463 148 davidgb
  my_rom : mon_rom
464
    port map (
465
      clk   => cpu_clk,
466
      rst   => cpu_reset,
467
      cs    => rom_cs,
468
      rw    => '1',
469
      addr  => cpu_addr(11 downto 0),
470
      data_in => cpu_data_out,
471
      data_out => rom_data_out
472 141 davidgb
    );
473
 
474 148 davidgb
  my_flex : flex_ram
475
    port map (
476
      clk       => cpu_clk,
477
      rst       => cpu_reset,
478
      cs        => flex_cs,
479
      rw        => cpu_rw,
480
      addr      => cpu_addr(12 downto 0),
481
      data_out     => flex_data_out,
482
      data_in     => cpu_data_out
483 170 davidgb
    );
484
 
485
  my_32k : ram_32k
486
    port map (
487
      clk       => cpu_clk,
488
      rst       => cpu_reset,
489
      cs        => ram_cs,
490
      rw        => cpu_rw,
491
      addr      => cpu_addr(14 downto 0),
492
      data_out     => ram_data_out,
493
      data_in     => cpu_data_out
494
    );
495 141 davidgb
 
496 148 davidgb
  my_acia  : acia6850
497
    port map (
498
      clk       => cpu_clk,
499
      rst       => cpu_reset,
500
      cs        => acia_cs,
501
      rw        => cpu_rw,
502
      addr      => cpu_addr(0),
503
      data_in   => cpu_data_out,
504
      data_out  => acia_data_out,
505
      irq       => acia_irq,
506
      RxC       => acia_clk,
507
      TxC       => acia_clk,
508
      RxD       => rxd,
509
      TxD       => txd,
510
      DCD_n     => dcd_n,
511
      CTS_n     => cts_n,
512
      RTS_n     => rts_n
513 141 davidgb
    );
514
 
515 148 davidgb
  my_ACIA_Clock : ACIA_Clock
516
    generic map(
517
      SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
518
      ACIA_CLK_FREQ => ACIA_CLK_FREQ
519
    )
520
    port map(
521
      clk        => Clk_i,
522
      acia_clk   => acia_clk
523
    );
524 141 davidgb
 
525 148 davidgb
  ----------------------------------------
526
  --
527
  -- Timer Module
528
  --
529
  ----------------------------------------
530
  my_timer  : timer
531
    port map (
532
      clk       => cpu_clk,
533
      rst       => cpu_reset,
534
      cs        => timer_cs,
535
      rw        => cpu_rw,
536
      addr      => cpu_addr(0),
537
      data_in   => cpu_data_out,
538
      data_out  => timer_data_out,
539
      irq       => timer_irq
540
    );
541 141 davidgb
 
542 148 davidgb
  ----------------------------------------
543
  --
544
  -- Bus Trap Interrupt logic
545
  --
546
  ----------------------------------------
547
  my_trap : trap
548
    port map (
549
      clk        => cpu_clk,
550
      rst        => cpu_reset,
551
      cs         => trap_cs,
552
      rw         => cpu_rw,
553
      vma        => cpu_vma,
554
      addr       => cpu_addr,
555
      data_in    => cpu_data_out,
556
      data_out   => trap_data_out,
557
      irq        => trap_irq
558 141 davidgb
    );
559
 
560 148 davidgb
  my_dat : dat_ram
561
    port map (
562
      clk       => cpu_clk,
563
      rst       => cpu_reset,
564
      cs        => dat_cs,
565
      rw        => cpu_rw,
566
      addr_hi   => cpu_addr(15 downto 12),
567
      addr_lo   => cpu_addr(3 downto 0),
568
      data_in   => cpu_data_out,
569
      data_out  => dat_addr(7 downto 0)
570 141 davidgb
    );
571
 
572 148 davidgb
  cpu_clk_buffer : BUFG
573 141 davidgb
    port map(
574 148 davidgb
      i => Clk25,
575
      o => cpu_clk
576 141 davidgb
    );
577 162 davidgb
 
578 148 davidgb
  ----------------------------------------------------------------------
579
  --
580
  -- Process to decode memory map
581
  --
582
  ----------------------------------------------------------------------
583 141 davidgb
 
584 148 davidgb
  mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
585 141 davidgb
                     dat_addr,
586
                     rom_data_out,
587
                     flex_data_out,
588
                     acia_data_out,
589
                     timer_data_out,
590
                     trap_data_out,
591
                     ram_data_out
592
                     )
593 148 davidgb
  begin
594
    cpu_data_in <= (others=>'0');
595
    dat_cs      <= '0';
596
    rom_cs      <= '0';
597
    flex_cs     <= '0';
598
    acia_cs     <= '0';
599
    timer_cs    <= '0';
600
    trap_cs     <= '0';
601
    ram_cs      <= '0';
602 141 davidgb
 
603 148 davidgb
    if cpu_addr( 15 downto 8 ) = "11111111" then  -- $FFxx
604
      cpu_data_in <= rom_data_out;
605
      dat_cs      <= cpu_vma;              -- write DAT
606
      rom_cs      <= cpu_vma;              -- read  ROM
607 141 davidgb
 
608 148 davidgb
    --
609
    -- Sys09Bug Monitor ROM $F000 - $FFFF
610
    --
611
    elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
612
      cpu_data_in <= rom_data_out;
613
      rom_cs      <= cpu_vma;
614 141 davidgb
 
615 148 davidgb
    --
616
    -- IO Devices $E000 - $E7FF
617
    --
618
    elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
619
      case cpu_addr(11 downto 8) is
620
        --
621
        -- SWTPC peripherals from $E000 to $E0FF
622
        --
623
        when "0000" =>
624
          case cpu_addr(7 downto 4) is
625
          --
626
          -- Console Port ACIA $E000 - $E00F
627
          --
628
            when "0000" => -- $E000
629
              cpu_data_in <= acia_data_out;
630
              acia_cs     <= cpu_vma;
631 141 davidgb
 
632 148 davidgb
            --
633
            -- Reserved
634
            -- Floppy Disk Controller port $E010 - $E01F
635
            --
636 141 davidgb
 
637 148 davidgb
            --
638
            -- Reserved SWTPc MP-T Timer $E040 - $E04F
639
            --
640
            when "0100" => -- $E040
641
              cpu_data_in <= (others=> '0');
642 141 davidgb
 
643 148 davidgb
            --
644
            -- Timer $E050 - $E05F
645
            --
646
            when "0101" => -- $E050
647
              cpu_data_in <= timer_data_out;
648
              timer_cs    <= cpu_vma;
649 141 davidgb
 
650 148 davidgb
            --
651
            -- Bus Trap Logic $E060 - $E06F
652
            --
653
            when "0110" => -- $E060
654
              cpu_data_in <= trap_data_out;
655
              trap_cs     <= cpu_vma;
656 141 davidgb
 
657 148 davidgb
            --
658
            -- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
659
            --
660
 
661
            --
662
            -- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
663
            --
664
 
665
            --
666
            -- Remaining 6 slots reserved for non SWTPc Peripherals
667
            --
668
            when others => -- $E0A0 to $E0FF
669
              null;
670
          end case;
671
 
672
        --
673
        -- $E200 to $EFFF reserved for future use
674
        --
675
        when others =>
676 141 davidgb
           null;
677 148 davidgb
      end case;
678 141 davidgb
 
679 148 davidgb
    --
680
    -- Flex RAM $0C000 - $0DFFF
681
    --
682
    elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
683
      cpu_data_in <= flex_data_out;
684
      flex_cs     <= cpu_vma;
685 170 davidgb
 
686
    --
687
    -- 32k RAM $00000 - $07FFF
688
    --
689
    elsif dat_addr(7 downto 1) = "0000000" then -- $00000 - $07FFF
690
      cpu_data_in <= ram_data_out;
691
      ram_cs     <= cpu_vma;
692 141 davidgb
 
693 148 davidgb
    --
694
    -- Everything else is RAM
695
    --
696 141 davidgb
    else
697 148 davidgb
      cpu_data_in <= ram_data_out;
698
      ram_cs      <= cpu_vma;
699 141 davidgb
    end if;
700
 
701 148 davidgb
  end process;
702 141 davidgb
 
703 148 davidgb
  --
704
  -- Interrupts and other bus control signals
705
  --
706
  interrupts : process( SW3_N,
707 141 davidgb
                      acia_irq,
708
                      trap_irq,
709
                      timer_irq
710
                      )
711 148 davidgb
  begin
712 162 davidgb
    cpu_irq    <= acia_irq;
713 141 davidgb
    cpu_nmi    <= trap_irq or not( SW3_N );
714
    cpu_firq   <= timer_irq;
715
    cpu_halt   <= '0';
716 170 davidgb
    cpu_hold   <= '0'; -- pb_hold or ram_hold;
717 148 davidgb
  end process;
718 141 davidgb
 
719 148 davidgb
  --
720
  -- Flash 7 segment LEDS
721
  --
722
  my_led_flasher: process( clk_i, rst_i, CountL )
723
  begin
724 141 davidgb
    if rst_i = '1' then
725
         CountL <= "000000000000000000000000";
726
    elsif rising_edge(clk_i) then
727
         CountL <= CountL + 1;
728
    end if;
729 162 davidgb
    --S(7 downto 0) <= CountL(23 downto 16);
730 148 davidgb
  end process;
731 141 davidgb
 
732 148 davidgb
  --
733
  -- Generate CPU & Pixel Clock from Memory Clock
734
  --
735
  my_prescaler : process( clk_i, clk_count )
736
  begin
737
    if rising_edge( clk_i ) then
738
      if clk_count = 0 then
739
        clk_count <= CPU_CLK_DIV-1;
740
      else
741
        clk_count <= clk_count - 1;
742
      end if;
743
      if clk_count = 0 then
744
         clk25 <= '0';
745
      elsif clk_count = (CPU_CLK_DIV/2) then
746
         clk25 <= '1';
747
      end if;
748 141 davidgb
    end if;
749 148 davidgb
  end process;
750 141 davidgb
 
751 148 davidgb
  --
752
  -- Reset button and reset timer
753
  --
754 162 davidgb
  my_switch_assignments : process( rst_i, SW2_N)
755 148 davidgb
  begin
756 169 davidgb
    rst_i <= SW2_N;
757 162 davidgb
    cpu_reset <= rst_i;
758 148 davidgb
  end process;
759 141 davidgb
 
760 148 davidgb
  --
761
  -- RS232 signals:
762
  --
763
  my_acia_assignments : process( RS232_RXD, RS232_CTS, txd, rts_n )
764
  begin
765
    rxd       <= RS232_RXD;
766
    cts_n     <= RS232_CTS;
767
    dcd_n     <= '0';
768
    RS232_TXD <= txd;
769
    RS232_RTS <= rts_n;
770
  end process;
771 141 davidgb
 
772 170 davidgb
  status_leds : process( rst_i, cpu_reset,cpu_addr, cpu_rw)
773 148 davidgb
  begin
774 170 davidgb
    S(0) <= cpu_addr(0);
775
    S(1) <= cpu_addr(1);
776
    S(2) <= cpu_addr(2);
777
    S(3) <= cpu_addr(3);
778
         S(4) <= cpu_addr(4);
779
         S(5) <= cpu_addr(5);
780
         S(6) <= cpu_rw;
781 169 davidgb
         S(7) <= '0';
782 162 davidgb
    --S(7 downto 4) <= "0000";
783 148 davidgb
  end process;
784 141 davidgb
 
785 148 davidgb
--  debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
786 141 davidgb
--                      cpu_halt, cpu_hold,
787
--                      cpu_firq, cpu_irq, cpu_nmi,
788
--                      cpu_addr, cpu_data_out, cpu_data_in )
789 148 davidgb
--  begin
790
--    cpu_reset_o    <= cpu_reset;
791
--    cpu_clk_o      <= cpu_clk;
792
--    cpu_rw_o       <= cpu_rw;
793
--    cpu_vma_o      <= cpu_vma;
794
--    cpu_halt_o     <= cpu_halt;
795
--    cpu_hold_o     <= cpu_hold;
796
--    cpu_firq_o     <= cpu_firq;
797
--    cpu_irq_o      <= cpu_irq;
798
--    cpu_nmi_o      <= cpu_nmi;
799
--    cpu_addr_o     <= cpu_addr;
800
--    cpu_data_out_o <= cpu_data_out;
801
--    cpu_data_in_o  <= cpu_data_in;
802
--  end process;
803 141 davidgb
 
804
end rtl; --===================== End of architecture =======================--
805
 

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