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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_Atlys/] [system09.vhd] - Blame information for rev 173

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1 141 davidgb
--===========================================================================----
2
--
3
--  S Y N T H E Z I A B L E    System09 - SOC.
4
--
5
--  www.OpenCores.Org - February 2007
6
--  This core adheres to the GNU public license  
7
--
8
-- File name      : System09_Xess_XSA-3S1000.vhd
9
--
10
-- Purpose        : Top level file for 6809 compatible system on a chip
11
--                  Designed with Xilinx XC3S1000 Spartan 3 FPGA.
12
--                  Implemented With XESS XSA-3S1000 FPGA board.
13
--                  *** Note ***
14
--                  This configuration can run Flex9 however it only has
15
--                  32k bytes of user memory and the VDU is monochrome
16
--                  The design needs to be updated to use the SDRAM on 
17
--                  the XSA-3S1000 board.
18
--                  This configuration also lacks a DAT so cannot use
19
--                  the RAM Disk features of SYS09BUG.
20
--
21
-- Dependencies   : ieee.Std_Logic_1164
22
--                  ieee.std_logic_unsigned
23
--                  ieee.std_logic_arith
24
--                  ieee.numeric_std
25
--                  unisim.vcomponents
26
--
27
-- Uses           : mon_rom    (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
28
--                  cpu09      (cpu09.vhd)          CPU core
29
--                  ACIA_6850  (acia6850.vhd)      ACIA / UART
30
--                  ACIA_Clock (ACIA_Clock.vhd)      ACIA clock.
31
--                  timer      (timer.vhd)            Interrupt timer
32
--                  trap       (trap.vhd)             Bus condition trap logic
33
--                  flex_ram   (flex9_ram8k_b16.vhd)  Flex operating system
34
--                  ram_32K    (ram32k_b16.vhd)       32 KBytes of Block RAM
35
--                  
36
-- 
37
-- Author         : John E. Kent      
38
--                  dilbert57@opencores.org      
39
--
40
-- Memory Map     :
41
--
42
-- $0000 - User program RAM (32K Bytes)
43
-- $C000 - Flex Operating System memory (8K Bytes)
44
-- $E000 - ACIA (SWTPc)
45
-- $E010 - Reserved for FD1771 FDC (SWTPc)
46
-- $E050 - Timer
47
-- $E060 - Bus trap
48
-- $E070 - Reserced for Parallel I/O (B5-X300)
49
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
50
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
51
-- $F000 - Sys09Bug monitor Program (4K Bytes)
52
--
53
--===========================================================================----
54
--
55
-- Revision History:
56
--===========================================================================--
57
-- Version 0.1 - 20 March 2003
58
-- Version 0.2 - 30 March 2003
59
-- Version 0.3 - 29 April 2003
60
-- Version 0.4 - 29 June 2003
61
--
62
-- Version 0.5 - 19 July 2003
63
-- prints out "Hello World"
64
--
65
-- Version 0.6 - 5 September 2003
66
-- Runs SBUG
67
--
68
-- Version 1.0- 6 Sep 2003 - John Kent
69
-- Inverted SysClk
70
-- Initial release to Open Cores
71
--
72
-- Version 1.1 - 17 Jan 2004 - John Kent
73
-- Updated miniUart.
74
--
75
-- Version 1.2 - 25 Jan 2004 - John Kent
76
-- removed signals "test_alu" and "test_cc" 
77
-- Trap hardware re-instated.
78
--
79
-- Version 1.3 - 11 Feb 2004 - John Kent
80
-- Designed forked off to produce System09_VDU
81
-- Added VDU component
82
-- VDU runs at 25MHz and divides the clock by 2 for the CPU
83
-- UART Runs at 57.6 Kbps
84
--
85
-- Version 2.0 - 2 September 2004 - John Kent
86
-- ported to Digilent Xilinx Spartan3 starter board
87
-- removed Compact Flash and Trap Logic.
88
-- Replaced SBUG with KBug9s
89
--
90
-- Version 3.0 - 29th August 2006 - John Kent
91
-- Adapted to XSA-3S1000 board.
92
-- Removed DAT and miniUART.
93
-- Used 32KBytes of Block RAM.
94
--
95
-- Version 3.1 - 15th January 2007 - John Kent
96
-- Modified vdu8 interface
97
-- Added a clock divider
98
--
99
-- Version 3.2 - 25th February 2007 - John Kent
100
-- reinstated ACIA_6850 and ACIA_Clock
101
-- Updated VDU8 & Keyboard with generic parameters
102
-- Defined Constants for clock speed calculations
103
--
104
-- Version 3.3 - 1st July 2007 - John Kent
105
-- Made VDU mono to save on one RAMB16
106
-- Used distributed memory for Key Map ROM to save one RAMB16
107
-- Added Flex RAM at $C000 to $DFFF using 4 spare RAMB16s
108
-- Added timer and trap logic
109
-- Added IDE Interface for Compact Flash
110
-- Replaced KBug9s and stack with Sys09Bug.
111
--
112
-- Version 4.0 - 1st February 2008 - John kent
113
-- Replaced Block RAM with SDRAM Interface
114
-- Modified Hold timing for SDRAM
115
-- Added CF and Ethernet interface 
116
-- via the 16 bit peripheral bus at $E100
117
--
118
--===========================================================================--
119
library ieee;
120
   use ieee.std_logic_1164.all;
121
   use IEEE.STD_LOGIC_ARITH.ALL;
122
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
123
   use ieee.numeric_std.all;
124
library work;
125
   use work.common.all;
126
library unisim;
127 162 davidgb
   use unisim.vcomponents.all;
128 141 davidgb
 
129
entity system09 is
130
  port(
131
    CLKA         : in  Std_Logic;  -- 100MHz Clock input
132
    SW2_N        : in  Std_logic;  -- Master Reset input (active low)
133
    SW3_N        : in  Std_logic;  -- Non Maskable Interrupt input (active low)
134
 
135
    -- RS232 Port
136
    RS232_RXD    : in  Std_Logic;
137
    RS232_TXD    : out Std_Logic;
138
 
139
    -- Status 7 segment LED
140 148 davidgb
    S            : out std_logic_vector(7 downto 0)
141 141 davidgb
 
142
-- CPU Debug Interface signals
143
--    cpu_reset_o     : out Std_Logic;
144
--    cpu_clk_o       : out Std_Logic;
145
--    cpu_rw_o        : out std_logic;
146
--    cpu_vma_o       : out std_logic;
147
--    cpu_halt_o      : out std_logic;
148
--    cpu_hold_o      : out std_logic;
149
--    cpu_firq_o      : out std_logic;
150
--    cpu_irq_o       : out std_logic;
151
--    cpu_nmi_o       : out std_logic;
152
--    cpu_addr_o      : out std_logic_vector(15 downto 0);
153
--    cpu_data_in_o   : out std_logic_vector(7 downto 0);
154
--    cpu_data_out_o  : out std_logic_vector(7 downto 0);
155
 
156 148 davidgb
  );
157 141 davidgb
end system09;
158
 
159
-------------------------------------------------------------------------------
160
-- Architecture for System09
161
-------------------------------------------------------------------------------
162
architecture rtl of system09 is
163
 
164
  -----------------------------------------------------------------------------
165
  -- constants
166
  -----------------------------------------------------------------------------
167
 
168
  constant MEM_CLK_FREQ         : natural := 100_000; -- operating frequency of Memory in KHz
169
  constant SYS_CLK_DIV          : real    := 2.0;    -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
170
 
171 170 davidgb
  constant SYS_CLK_FREQ         : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000;  -- FPGA System Clock (in Hz)
172 141 davidgb
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
173
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
174
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
175
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
176
 
177
  constant TRESET               : natural := 300;      -- min initialization interval (us)
178
  constant RST_CYCLES           : natural := 1+(TRESET*(MEM_CLK_FREQ/1_000));  -- SDRAM power-on initialization interval
179
 
180
  type hold_state_type is ( hold_release_state, hold_request_state );
181
 
182
  -----------------------------------------------------------------------------
183
  -- Signals
184
  -----------------------------------------------------------------------------
185
  -- BOOT ROM
186
  signal rom_cs         : Std_logic;
187
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
188
 
189
  -- Flex Memory & Monitor Stack
190
  signal flex_cs        : Std_logic;
191
  signal flex_data_out  : Std_Logic_Vector(7 downto 0);
192
 
193
  -- ACIA/UART Interface signals
194
  signal acia_data_out  : Std_Logic_Vector(7 downto 0);
195
  signal acia_cs        : Std_Logic;
196
  signal acia_irq       : Std_Logic;
197
  signal acia_clk       : Std_Logic;
198
  signal rxd            : Std_Logic;
199
  signal txd            : Std_Logic;
200
  signal DCD_n          : Std_Logic;
201
  signal RTS_n          : Std_Logic;
202
  signal CTS_n          : Std_Logic;
203
 
204
  -- RAM
205 173 davidgb
  signal ram1_cs         : std_logic;
206
  signal ram1_data_out   : std_logic_vector(7 downto 0);
207
  signal ram2_cs         : std_logic;
208
  signal ram2_data_out   : std_logic_vector(7 downto 0);
209
  signal ram3_cs         : std_logic;
210 141 davidgb
 
211
  -- CPU Interface signals
212
  signal cpu_reset      : Std_Logic;
213
  signal cpu_clk        : Std_Logic;
214
  signal cpu_rw         : std_logic;
215
  signal cpu_vma        : std_logic;
216
  signal cpu_halt       : std_logic;
217
  signal cpu_hold       : std_logic;
218
  signal cpu_firq       : std_logic;
219
  signal cpu_irq        : std_logic;
220
  signal cpu_nmi        : std_logic;
221
  signal cpu_addr       : std_logic_vector(15 downto 0);
222
  signal cpu_data_in    : std_logic_vector(7 downto 0);
223
  signal cpu_data_out   : std_logic_vector(7 downto 0);
224
 
225
  -- Dynamic Address Translation
226
  signal dat_cs       : std_logic;
227
  signal dat_addr     : std_logic_vector(7 downto 0);
228
 
229
  -- timer
230
  signal timer_data_out : std_logic_vector(7 downto 0);
231
  signal timer_cs       : std_logic;
232
  signal timer_irq      : std_logic;
233
 
234
  -- trap
235
  signal trap_cs        : std_logic;
236
  signal trap_data_out  : std_logic_vector(7 downto 0);
237
  signal trap_irq       : std_logic;
238
 
239
  signal rst_i         : std_logic;     -- internal reset signal
240
  signal clk_i         : std_logic;     -- internal master clock signal
241 170 davidgb
 
242
  signal rs232_cts    :   Std_Logic;
243
  signal rs232_rts    :  Std_Logic;
244 148 davidgb
 
245 141 davidgb
  signal CountL        : std_logic_vector(23 downto 0);
246
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
247
  signal Clk25         : std_logic;
248
 
249
-----------------------------------------------------------------
250
--
251
-- CPU09 CPU core
252
--
253
-----------------------------------------------------------------
254
 
255
component cpu09
256
  port (
257
    clk:      in  std_logic;
258
    rst:      in  std_logic;
259
    vma:      out std_logic;
260
    addr:     out std_logic_vector(15 downto 0);
261
    rw:       out std_logic;     -- Asynchronous memory interface
262
    data_out: out std_logic_vector(7 downto 0);
263
    data_in:  in  std_logic_vector(7 downto 0);
264
    irq:      in  std_logic;
265
    firq:     in  std_logic;
266
    nmi:      in  std_logic;
267
    halt:     in  std_logic;
268
    hold:     in  std_logic
269
  );
270
end component;
271
 
272
----------------------------------------
273
--
274
-- 4K Block RAM Monitor ROM
275 148 davidgb
-- $F000 - $FFFF
276 141 davidgb
--
277
----------------------------------------
278 148 davidgb
 
279 141 davidgb
component mon_rom
280 148 davidgb
  Port (
281
    clk   : in  std_logic;
282
    rst   : in  std_logic;
283
    cs    : in  std_logic;
284
    rw    : in  std_logic;
285
    addr  : in  std_logic_vector (11 downto 0);
286
    data_out : out std_logic_vector (7 downto 0);
287
    data_in : in  std_logic_vector (7 downto 0)
288
  );
289 141 davidgb
end component;
290
 
291
----------------------------------------
292
--
293
-- 8KBytes Block RAM for FLEX9
294
-- $C000 - $DFFF
295
--
296
----------------------------------------
297 148 davidgb
 
298 141 davidgb
component flex_ram
299
  Port (
300
    clk      : in  std_logic;
301
    rst      : in  std_logic;
302
    cs       : in  std_logic;
303
    rw       : in  std_logic;
304
    addr     : in  std_logic_vector (12 downto 0);
305
    data_out    : out std_logic_vector (7 downto 0);
306
    data_in    : in  std_logic_vector (7 downto 0)
307 148 davidgb
  );
308 141 davidgb
end component;
309 170 davidgb
 
310
----------------------------------------
311
--
312
-- 32KBytes Block RAM 0000
313
-- $0000 - $7FFF
314
--
315
----------------------------------------
316 141 davidgb
 
317 170 davidgb
component ram_32k
318
  Port (
319
    clk      : in  std_logic;
320
    rst      : in  std_logic;
321
    cs       : in  std_logic;
322
    rw       : in  std_logic;
323
    addr     : in  std_logic_vector (14 downto 0);
324
    data_out    : out std_logic_vector (7 downto 0);
325
    data_in    : in  std_logic_vector (7 downto 0)
326
  );
327
end component;
328
 
329 173 davidgb
 
330
----------------------------------------
331
--
332
-- 16KBytes Block RAM 8000
333
-- $8000 - $BFFF
334
--
335
----------------------------------------
336 170 davidgb
 
337 173 davidgb
component ram_16k
338
  Port (
339
    clk      : in  std_logic;
340
    rst      : in  std_logic;
341
    cs       : in  std_logic;
342
    rw       : in  std_logic;
343
    addr     : in  std_logic_vector (13 downto 0);
344
    data_out    : out std_logic_vector (7 downto 0);
345
    data_in    : in  std_logic_vector (7 downto 0)
346
  );
347
end component;
348
 
349 141 davidgb
-----------------------------------------------------------------
350
--
351
-- 6850 Compatible ACIA / UART
352
--
353
-----------------------------------------------------------------
354
 
355
component acia6850
356
  port (
357 148 davidgb
    clk      : in  Std_Logic;  -- System Clock
358
    rst      : in  Std_Logic;  -- Reset input (active high)
359
    cs       : in  Std_Logic;  -- miniUART Chip Select
360
    rw       : in  Std_Logic;  -- Read / Not Write
361
    addr     : in  Std_Logic;  -- Register Select
362
    data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
363
    data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
364
    irq      : out Std_Logic;  -- Interrupt
365
    RxC      : in  Std_Logic;  -- Receive Baud Clock
366
    TxC      : in  Std_Logic;  -- Transmit Baud Clock
367
    RxD      : in  Std_Logic;  -- Receive Data
368
    TxD      : out Std_Logic;  -- Transmit Data
369
    DCD_n    : in  Std_Logic;  -- Data Carrier Detect
370
    CTS_n    : in  Std_Logic;  -- Clear To Send
371
    RTS_n    : out Std_Logic   -- Request To send
372
  );
373 141 davidgb
end component;
374
 
375
-----------------------------------------------------------------
376
--
377
-- ACIA Clock divider
378
--
379
-----------------------------------------------------------------
380
 
381
component ACIA_Clock
382
  generic (
383 148 davidgb
    SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
384
    ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
385 141 davidgb
  );
386
  port (
387 148 davidgb
    clk      : in  Std_Logic;  -- System Clock Input
388
    ACIA_clk : out Std_logic   -- ACIA Clock output
389 141 davidgb
  );
390
end component;
391
 
392
----------------------------------------
393
--
394
-- Timer module
395
--
396
----------------------------------------
397
 
398
component timer
399
  port (
400 148 davidgb
    clk       : in std_logic;
401
    rst       : in std_logic;
402
    cs        : in std_logic;
403
    rw        : in std_logic;
404
    addr      : in std_logic;
405
    data_in   : in std_logic_vector(7 downto 0);
406
    data_out  : out std_logic_vector(7 downto 0);
407
    irq       : out std_logic
408
  );
409 141 davidgb
end component;
410
 
411
------------------------------------------------------------
412
--
413
-- Bus Trap logic
414
--
415
------------------------------------------------------------
416
 
417
component trap
418 148 davidgb
  port (
419 141 davidgb
    clk        : in  std_logic;
420
    rst        : in  std_logic;
421
    cs         : in  std_logic;
422
    rw         : in  std_logic;
423
    vma        : in  std_logic;
424
    addr       : in  std_logic_vector(15 downto 0);
425
    data_in    : in  std_logic_vector(7 downto 0);
426
    data_out   : out std_logic_vector(7 downto 0);
427
    irq        : out std_logic
428
  );
429
end component;
430
 
431
----------------------------------------
432
--
433
-- Dynamic Address Translation Registers
434
--
435
----------------------------------------
436 148 davidgb
 
437 141 davidgb
component dat_ram
438
  port (
439
    clk      : in  std_logic;
440
    rst      : in  std_logic;
441
    cs       : in  std_logic;
442
    rw       : in  std_logic;
443
    addr_lo  : in  std_logic_vector(3 downto 0);
444
    addr_hi  : in  std_logic_vector(3 downto 0);
445
    data_in  : in  std_logic_vector(7 downto 0);
446
    data_out : out std_logic_vector(7 downto 0)
447
  );
448
end component;
449
 
450
 
451
--
452
-- Clock buffer
453
--
454 148 davidgb
 
455 141 davidgb
component BUFG
456
   Port (
457
     i: in std_logic;
458
     o: out std_logic
459
  );
460
end component;
461
 
462
begin
463 169 davidgb
 
464
  clk_i <= CLKA;
465 141 davidgb
  -----------------------------------------------------------------------------
466
  -- Instantiation of internal components
467
  -----------------------------------------------------------------------------
468
 
469 148 davidgb
  my_cpu : cpu09
470
    port map (
471
      clk       => cpu_clk,
472
      rst       => cpu_reset,
473
      vma       => cpu_vma,
474
      addr      => cpu_addr(15 downto 0),
475
      rw        => cpu_rw,
476
      data_out  => cpu_data_out,
477
      data_in   => cpu_data_in,
478
      irq       => cpu_irq,
479
      firq      => cpu_firq,
480
      nmi       => cpu_nmi,
481
      halt      => cpu_halt,
482
      hold      => cpu_hold
483
    );
484 141 davidgb
 
485 148 davidgb
  my_rom : mon_rom
486
    port map (
487
      clk   => cpu_clk,
488
      rst   => cpu_reset,
489
      cs    => rom_cs,
490
      rw    => '1',
491
      addr  => cpu_addr(11 downto 0),
492
      data_in => cpu_data_out,
493
      data_out => rom_data_out
494 141 davidgb
    );
495
 
496 148 davidgb
  my_flex : flex_ram
497
    port map (
498
      clk       => cpu_clk,
499
      rst       => cpu_reset,
500
      cs        => flex_cs,
501
      rw        => cpu_rw,
502
      addr      => cpu_addr(12 downto 0),
503
      data_out     => flex_data_out,
504
      data_in     => cpu_data_out
505 170 davidgb
    );
506
 
507
  my_32k : ram_32k
508
    port map (
509
      clk       => cpu_clk,
510
      rst       => cpu_reset,
511 173 davidgb
      cs        => ram1_cs,
512 170 davidgb
      rw        => cpu_rw,
513
      addr      => cpu_addr(14 downto 0),
514 173 davidgb
      data_out     => ram1_data_out,
515 170 davidgb
      data_in     => cpu_data_out
516
    );
517 173 davidgb
 
518
  my_16k : ram_16k
519
    port map (
520
      clk       => cpu_clk,
521
      rst       => cpu_reset,
522
      cs        => ram2_cs,
523
      rw        => cpu_rw,
524
      addr      => cpu_addr(13 downto 0),
525
      data_out     => ram2_data_out,
526
      data_in     => cpu_data_out
527
    );
528
 
529 148 davidgb
  my_acia  : acia6850
530
    port map (
531
      clk       => cpu_clk,
532
      rst       => cpu_reset,
533
      cs        => acia_cs,
534
      rw        => cpu_rw,
535
      addr      => cpu_addr(0),
536
      data_in   => cpu_data_out,
537
      data_out  => acia_data_out,
538
      irq       => acia_irq,
539
      RxC       => acia_clk,
540
      TxC       => acia_clk,
541
      RxD       => rxd,
542
      TxD       => txd,
543
      DCD_n     => dcd_n,
544
      CTS_n     => cts_n,
545
      RTS_n     => rts_n
546 141 davidgb
    );
547
 
548 148 davidgb
  my_ACIA_Clock : ACIA_Clock
549
    generic map(
550
      SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
551
      ACIA_CLK_FREQ => ACIA_CLK_FREQ
552
    )
553
    port map(
554
      clk        => Clk_i,
555
      acia_clk   => acia_clk
556
    );
557 141 davidgb
 
558 148 davidgb
  ----------------------------------------
559
  --
560
  -- Timer Module
561
  --
562
  ----------------------------------------
563
  my_timer  : timer
564
    port map (
565
      clk       => cpu_clk,
566
      rst       => cpu_reset,
567
      cs        => timer_cs,
568
      rw        => cpu_rw,
569
      addr      => cpu_addr(0),
570
      data_in   => cpu_data_out,
571
      data_out  => timer_data_out,
572
      irq       => timer_irq
573
    );
574 141 davidgb
 
575 148 davidgb
  ----------------------------------------
576
  --
577
  -- Bus Trap Interrupt logic
578
  --
579
  ----------------------------------------
580
  my_trap : trap
581
    port map (
582
      clk        => cpu_clk,
583
      rst        => cpu_reset,
584
      cs         => trap_cs,
585
      rw         => cpu_rw,
586
      vma        => cpu_vma,
587
      addr       => cpu_addr,
588
      data_in    => cpu_data_out,
589
      data_out   => trap_data_out,
590
      irq        => trap_irq
591 141 davidgb
    );
592
 
593 148 davidgb
  my_dat : dat_ram
594
    port map (
595
      clk       => cpu_clk,
596
      rst       => cpu_reset,
597
      cs        => dat_cs,
598
      rw        => cpu_rw,
599
      addr_hi   => cpu_addr(15 downto 12),
600
      addr_lo   => cpu_addr(3 downto 0),
601
      data_in   => cpu_data_out,
602
      data_out  => dat_addr(7 downto 0)
603 141 davidgb
    );
604
 
605 148 davidgb
  cpu_clk_buffer : BUFG
606 141 davidgb
    port map(
607 148 davidgb
      i => Clk25,
608
      o => cpu_clk
609 141 davidgb
    );
610 162 davidgb
 
611 148 davidgb
  ----------------------------------------------------------------------
612
  --
613
  -- Process to decode memory map
614
  --
615
  ----------------------------------------------------------------------
616 141 davidgb
 
617 148 davidgb
  mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
618 141 davidgb
                     dat_addr,
619
                     rom_data_out,
620
                     flex_data_out,
621
                     acia_data_out,
622
                     timer_data_out,
623
                     trap_data_out,
624 173 davidgb
                     ram1_data_out, ram2_data_out
625 141 davidgb
                     )
626 148 davidgb
  begin
627
    cpu_data_in <= (others=>'0');
628
    dat_cs      <= '0';
629
    rom_cs      <= '0';
630
    flex_cs     <= '0';
631
    acia_cs     <= '0';
632
    timer_cs    <= '0';
633
    trap_cs     <= '0';
634 173 davidgb
    ram1_cs      <= '0';
635
    ram2_cs      <= '0';
636
 
637 148 davidgb
    if cpu_addr( 15 downto 8 ) = "11111111" then  -- $FFxx
638
      cpu_data_in <= rom_data_out;
639
      dat_cs      <= cpu_vma;              -- write DAT
640
      rom_cs      <= cpu_vma;              -- read  ROM
641 141 davidgb
 
642 148 davidgb
    --
643
    -- Sys09Bug Monitor ROM $F000 - $FFFF
644
    --
645
    elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
646
      cpu_data_in <= rom_data_out;
647
      rom_cs      <= cpu_vma;
648 141 davidgb
 
649 148 davidgb
    --
650
    -- IO Devices $E000 - $E7FF
651
    --
652
    elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
653
      case cpu_addr(11 downto 8) is
654
        --
655
        -- SWTPC peripherals from $E000 to $E0FF
656
        --
657
        when "0000" =>
658
          case cpu_addr(7 downto 4) is
659
          --
660
          -- Console Port ACIA $E000 - $E00F
661
          --
662
            when "0000" => -- $E000
663
              cpu_data_in <= acia_data_out;
664
              acia_cs     <= cpu_vma;
665 141 davidgb
 
666 148 davidgb
            --
667
            -- Reserved
668
            -- Floppy Disk Controller port $E010 - $E01F
669
            --
670 141 davidgb
 
671 148 davidgb
            --
672
            -- Reserved SWTPc MP-T Timer $E040 - $E04F
673
            --
674
            when "0100" => -- $E040
675
              cpu_data_in <= (others=> '0');
676 141 davidgb
 
677 148 davidgb
            --
678
            -- Timer $E050 - $E05F
679
            --
680
            when "0101" => -- $E050
681
              cpu_data_in <= timer_data_out;
682
              timer_cs    <= cpu_vma;
683 141 davidgb
 
684 148 davidgb
            --
685
            -- Bus Trap Logic $E060 - $E06F
686
            --
687
            when "0110" => -- $E060
688
              cpu_data_in <= trap_data_out;
689
              trap_cs     <= cpu_vma;
690 141 davidgb
 
691 148 davidgb
            --
692
            -- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
693
            --
694
 
695
            --
696
            -- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
697
            --
698
 
699
            --
700
            -- Remaining 6 slots reserved for non SWTPc Peripherals
701
            --
702
            when others => -- $E0A0 to $E0FF
703
              null;
704
          end case;
705
 
706
        --
707
        -- $E200 to $EFFF reserved for future use
708
        --
709
        when others =>
710 141 davidgb
           null;
711 148 davidgb
      end case;
712 141 davidgb
 
713 148 davidgb
    --
714
    -- Flex RAM $0C000 - $0DFFF
715
    --
716
    elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
717
      cpu_data_in <= flex_data_out;
718
      flex_cs     <= cpu_vma;
719 170 davidgb
 
720
    --
721
    -- 32k RAM $00000 - $07FFF
722
    --
723
    elsif dat_addr(7 downto 1) = "0000000" then -- $00000 - $07FFF
724 173 davidgb
      cpu_data_in <= ram1_data_out;
725
      ram1_cs     <= cpu_vma;
726
 
727
    --
728
    -- 16k RAM $08000 - $0BFFF
729
    --
730
    elsif dat_addr(7 downto 1) = "0000100" then -- $08000 - $0BFFF
731
      cpu_data_in <= ram2_data_out;
732
      ram2_cs     <= cpu_vma;
733 141 davidgb
 
734 148 davidgb
    --
735
    -- Everything else is RAM
736
    --
737 141 davidgb
    else
738 173 davidgb
      cpu_data_in <= (others => '0');
739
      ram3_cs      <= cpu_vma;
740 141 davidgb
    end if;
741
 
742 148 davidgb
  end process;
743 141 davidgb
 
744 148 davidgb
  --
745
  -- Interrupts and other bus control signals
746
  --
747
  interrupts : process( SW3_N,
748 141 davidgb
                      acia_irq,
749
                      trap_irq,
750
                      timer_irq
751
                      )
752 148 davidgb
  begin
753 162 davidgb
    cpu_irq    <= acia_irq;
754 141 davidgb
    cpu_nmi    <= trap_irq or not( SW3_N );
755
    cpu_firq   <= timer_irq;
756
    cpu_halt   <= '0';
757 170 davidgb
    cpu_hold   <= '0'; -- pb_hold or ram_hold;
758 148 davidgb
  end process;
759 141 davidgb
 
760 148 davidgb
  --
761
  -- Flash 7 segment LEDS
762
  --
763
  my_led_flasher: process( clk_i, rst_i, CountL )
764
  begin
765 141 davidgb
    if rst_i = '1' then
766
         CountL <= "000000000000000000000000";
767
    elsif rising_edge(clk_i) then
768
         CountL <= CountL + 1;
769
    end if;
770 162 davidgb
    --S(7 downto 0) <= CountL(23 downto 16);
771 148 davidgb
  end process;
772 141 davidgb
 
773 148 davidgb
  --
774
  -- Generate CPU & Pixel Clock from Memory Clock
775
  --
776
  my_prescaler : process( clk_i, clk_count )
777
  begin
778
    if rising_edge( clk_i ) then
779
      if clk_count = 0 then
780
        clk_count <= CPU_CLK_DIV-1;
781
      else
782
        clk_count <= clk_count - 1;
783
      end if;
784
      if clk_count = 0 then
785
         clk25 <= '0';
786
      elsif clk_count = (CPU_CLK_DIV/2) then
787
         clk25 <= '1';
788
      end if;
789 141 davidgb
    end if;
790 148 davidgb
  end process;
791 141 davidgb
 
792 148 davidgb
  --
793
  -- Reset button and reset timer
794
  --
795 162 davidgb
  my_switch_assignments : process( rst_i, SW2_N)
796 148 davidgb
  begin
797 169 davidgb
    rst_i <= SW2_N;
798 162 davidgb
    cpu_reset <= rst_i;
799 148 davidgb
  end process;
800 141 davidgb
 
801 148 davidgb
  --
802
  -- RS232 signals:
803
  --
804
  my_acia_assignments : process( RS232_RXD, RS232_CTS, txd, rts_n )
805
  begin
806
    rxd       <= RS232_RXD;
807
    cts_n     <= RS232_CTS;
808
    dcd_n     <= '0';
809
    RS232_TXD <= txd;
810
    RS232_RTS <= rts_n;
811
  end process;
812 141 davidgb
 
813 170 davidgb
  status_leds : process( rst_i, cpu_reset,cpu_addr, cpu_rw)
814 148 davidgb
  begin
815 170 davidgb
    S(0) <= cpu_addr(0);
816
    S(1) <= cpu_addr(1);
817
    S(2) <= cpu_addr(2);
818
    S(3) <= cpu_addr(3);
819
         S(4) <= cpu_addr(4);
820
         S(5) <= cpu_addr(5);
821
         S(6) <= cpu_rw;
822 169 davidgb
         S(7) <= '0';
823 162 davidgb
    --S(7 downto 4) <= "0000";
824 148 davidgb
  end process;
825 141 davidgb
 
826 148 davidgb
--  debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
827 141 davidgb
--                      cpu_halt, cpu_hold,
828
--                      cpu_firq, cpu_irq, cpu_nmi,
829
--                      cpu_addr, cpu_data_out, cpu_data_in )
830 148 davidgb
--  begin
831
--    cpu_reset_o    <= cpu_reset;
832
--    cpu_clk_o      <= cpu_clk;
833
--    cpu_rw_o       <= cpu_rw;
834
--    cpu_vma_o      <= cpu_vma;
835
--    cpu_halt_o     <= cpu_halt;
836
--    cpu_hold_o     <= cpu_hold;
837
--    cpu_firq_o     <= cpu_firq;
838
--    cpu_irq_o      <= cpu_irq;
839
--    cpu_nmi_o      <= cpu_nmi;
840
--    cpu_addr_o     <= cpu_addr;
841
--    cpu_data_out_o <= cpu_data_out;
842
--    cpu_data_in_o  <= cpu_data_in;
843
--  end process;
844 141 davidgb
 
845
end rtl; --===================== End of architecture =======================--
846
 

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