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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_Atlys/] [system09.vhd] - Blame information for rev 185

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1 141 davidgb
--===========================================================================----
2
--
3
--  S Y N T H E Z I A B L E    System09 - SOC.
4
--
5
--  www.OpenCores.Org - February 2007
6
--  This core adheres to the GNU public license  
7
--
8
-- File name      : System09_Xess_XSA-3S1000.vhd
9
--
10
-- Purpose        : Top level file for 6809 compatible system on a chip
11
--                  Designed with Xilinx XC3S1000 Spartan 3 FPGA.
12
--                  Implemented With XESS XSA-3S1000 FPGA board.
13
--                  *** Note ***
14
--                  This configuration can run Flex9 however it only has
15
--                  32k bytes of user memory and the VDU is monochrome
16
--                  The design needs to be updated to use the SDRAM on 
17
--                  the XSA-3S1000 board.
18
--                  This configuration also lacks a DAT so cannot use
19
--                  the RAM Disk features of SYS09BUG.
20
--
21
-- Dependencies   : ieee.Std_Logic_1164
22
--                  ieee.std_logic_unsigned
23
--                  ieee.std_logic_arith
24
--                  ieee.numeric_std
25
--                  unisim.vcomponents
26
--
27
-- Uses           : mon_rom    (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
28
--                  cpu09      (cpu09.vhd)          CPU core
29
--                  ACIA_6850  (acia6850.vhd)      ACIA / UART
30
--                  ACIA_Clock (ACIA_Clock.vhd)      ACIA clock.
31
--                  timer      (timer.vhd)            Interrupt timer
32
--                  trap       (trap.vhd)             Bus condition trap logic
33
--                  flex_ram   (flex9_ram8k_b16.vhd)  Flex operating system
34
--                  ram_32K    (ram32k_b16.vhd)       32 KBytes of Block RAM
35
--                  
36
-- 
37
-- Author         : John E. Kent      
38
--                  dilbert57@opencores.org      
39
--
40
-- Memory Map     :
41
--
42
-- $0000 - User program RAM (32K Bytes)
43
-- $C000 - Flex Operating System memory (8K Bytes)
44
-- $E000 - ACIA (SWTPc)
45
-- $E010 - Reserved for FD1771 FDC (SWTPc)
46
-- $E050 - Timer
47
-- $E060 - Bus trap
48
-- $E070 - Reserced for Parallel I/O (B5-X300)
49
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
50
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
51
-- $F000 - Sys09Bug monitor Program (4K Bytes)
52
--
53
--===========================================================================----
54
--
55
-- Revision History:
56
--===========================================================================--
57
-- Version 0.1 - 20 March 2003
58
-- Version 0.2 - 30 March 2003
59
-- Version 0.3 - 29 April 2003
60
-- Version 0.4 - 29 June 2003
61
--
62
-- Version 0.5 - 19 July 2003
63
-- prints out "Hello World"
64
--
65
-- Version 0.6 - 5 September 2003
66
-- Runs SBUG
67
--
68
-- Version 1.0- 6 Sep 2003 - John Kent
69
-- Inverted SysClk
70
-- Initial release to Open Cores
71
--
72
-- Version 1.1 - 17 Jan 2004 - John Kent
73
-- Updated miniUart.
74
--
75
-- Version 1.2 - 25 Jan 2004 - John Kent
76
-- removed signals "test_alu" and "test_cc" 
77
-- Trap hardware re-instated.
78
--
79
-- Version 1.3 - 11 Feb 2004 - John Kent
80
-- Designed forked off to produce System09_VDU
81
-- Added VDU component
82
-- VDU runs at 25MHz and divides the clock by 2 for the CPU
83
-- UART Runs at 57.6 Kbps
84
--
85
-- Version 2.0 - 2 September 2004 - John Kent
86
-- ported to Digilent Xilinx Spartan3 starter board
87
-- removed Compact Flash and Trap Logic.
88
-- Replaced SBUG with KBug9s
89
--
90
-- Version 3.0 - 29th August 2006 - John Kent
91
-- Adapted to XSA-3S1000 board.
92
-- Removed DAT and miniUART.
93
-- Used 32KBytes of Block RAM.
94
--
95
-- Version 3.1 - 15th January 2007 - John Kent
96
-- Modified vdu8 interface
97
-- Added a clock divider
98
--
99
-- Version 3.2 - 25th February 2007 - John Kent
100
-- reinstated ACIA_6850 and ACIA_Clock
101
-- Updated VDU8 & Keyboard with generic parameters
102
-- Defined Constants for clock speed calculations
103
--
104
-- Version 3.3 - 1st July 2007 - John Kent
105
-- Made VDU mono to save on one RAMB16
106
-- Used distributed memory for Key Map ROM to save one RAMB16
107
-- Added Flex RAM at $C000 to $DFFF using 4 spare RAMB16s
108
-- Added timer and trap logic
109
-- Added IDE Interface for Compact Flash
110
-- Replaced KBug9s and stack with Sys09Bug.
111
--
112
-- Version 4.0 - 1st February 2008 - John kent
113
-- Replaced Block RAM with SDRAM Interface
114
-- Modified Hold timing for SDRAM
115
-- Added CF and Ethernet interface 
116
-- via the 16 bit peripheral bus at $E100
117
--
118
--===========================================================================--
119
library ieee;
120
   use ieee.std_logic_1164.all;
121
   use IEEE.STD_LOGIC_ARITH.ALL;
122
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
123
   use ieee.numeric_std.all;
124
library work;
125
   use work.common.all;
126
library unisim;
127 162 davidgb
   use unisim.vcomponents.all;
128 141 davidgb
 
129
entity system09 is
130
  port(
131
    CLKA         : in  Std_Logic;  -- 100MHz Clock input
132 185 davidgb
    --SW2_N        : in  Std_logic;  -- Master Reset input (active low)
133
    --SW3_N        : in  Std_logic;  -- Non Maskable Interrupt input (active low)
134 141 davidgb
 
135 185 davidgb
    -- RS232 Port
136
    RS232_RXD    : in  Std_Logic;
137
    RS232_TXD    : out Std_Logic;
138 141 davidgb
 
139 185 davidgb
    -- Status 7 segment LED
140
         sw           : in std_logic_vector(7 downto 0);
141
         btn          : in std_logic_vector(4 downto 0);
142
    S            : out std_logic_vector(7 downto 0)
143
 
144
 
145 141 davidgb
-- CPU Debug Interface signals
146
--    cpu_reset_o     : out Std_Logic;
147
--    cpu_clk_o       : out Std_Logic;
148
--    cpu_rw_o        : out std_logic;
149
--    cpu_vma_o       : out std_logic;
150
--    cpu_halt_o      : out std_logic;
151
--    cpu_hold_o      : out std_logic;
152
--    cpu_firq_o      : out std_logic;
153
--    cpu_irq_o       : out std_logic;
154
--    cpu_nmi_o       : out std_logic;
155
--    cpu_addr_o      : out std_logic_vector(15 downto 0);
156
--    cpu_data_in_o   : out std_logic_vector(7 downto 0);
157
--    cpu_data_out_o  : out std_logic_vector(7 downto 0);
158
 
159 148 davidgb
  );
160 141 davidgb
end system09;
161
 
162
-------------------------------------------------------------------------------
163
-- Architecture for System09
164
-------------------------------------------------------------------------------
165
architecture rtl of system09 is
166
 
167
  -----------------------------------------------------------------------------
168
  -- constants
169
  -----------------------------------------------------------------------------
170 185 davidgb
 
171
  constant MEM_CLK_FREQ         : natural := 100_000; -- operating frequency of Memory in KHz
172
  constant SYS_CLK_DIV          : real    := 2.0;    -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
173
 
174
  constant SYS_CLK_FREQ         : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000;  -- FPGA System Clock (in Hz)
175
  constant CPU_CLK_FREQ         : natural := 1; --25_000_000;  -- CPU Clock (Hz)
176 141 davidgb
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
177
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
178
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
179
 
180 185 davidgb
  constant TRESET               : natural := 300;      -- min initialization interval (us)
181
  constant RST_CYCLES           : natural := 1+(TRESET*(MEM_CLK_FREQ/1_000));  -- SDRAM power-on initialization interval
182
 
183 141 davidgb
  -----------------------------------------------------------------------------
184
  -- Signals
185 174 davidgb
  -----------------------------------------------------------------------------
186 185 davidgb
  signal pbtn           : std_logic_vector(4 downto 0);
187
  signal SW3_N : std_logic;
188
  signal SW2_N : std_logic;
189 141 davidgb
  -- BOOT ROM
190
  signal rom_cs         : Std_logic;
191
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
192
 
193
  -- Flex Memory & Monitor Stack
194
  signal flex_cs        : Std_logic;
195
  signal flex_data_out  : Std_Logic_Vector(7 downto 0);
196
 
197
  -- ACIA/UART Interface signals
198
  signal acia_data_out  : Std_Logic_Vector(7 downto 0);
199
  signal acia_cs        : Std_Logic;
200
  signal acia_irq       : Std_Logic;
201
  signal acia_clk       : Std_Logic;
202
  signal rxd            : Std_Logic;
203
  signal txd            : Std_Logic;
204
  signal DCD_n          : Std_Logic;
205
  signal RTS_n          : Std_Logic;
206
  signal CTS_n          : Std_Logic;
207
 
208
  -- RAM
209 173 davidgb
  signal ram1_cs         : std_logic;
210
  signal ram1_data_out   : std_logic_vector(7 downto 0);
211
  signal ram2_cs         : std_logic;
212
  signal ram2_data_out   : std_logic_vector(7 downto 0);
213
  signal ram3_cs         : std_logic;
214 141 davidgb
 
215
  -- CPU Interface signals
216
  signal cpu_reset      : Std_Logic;
217
  signal cpu_clk        : Std_Logic;
218
  signal cpu_rw         : std_logic;
219
  signal cpu_vma        : std_logic;
220
  signal cpu_halt       : std_logic;
221
  signal cpu_hold       : std_logic;
222
  signal cpu_firq       : std_logic;
223
  signal cpu_irq        : std_logic;
224
  signal cpu_nmi        : std_logic;
225
  signal cpu_addr       : std_logic_vector(15 downto 0);
226
  signal cpu_data_in    : std_logic_vector(7 downto 0);
227
  signal cpu_data_out   : std_logic_vector(7 downto 0);
228
 
229
  -- Dynamic Address Translation
230
  signal dat_cs       : std_logic;
231
  signal dat_addr     : std_logic_vector(7 downto 0);
232
 
233
  -- timer
234
  signal timer_data_out : std_logic_vector(7 downto 0);
235
  signal timer_cs       : std_logic;
236
  signal timer_irq      : std_logic;
237
 
238
  -- trap
239
  signal trap_cs        : std_logic;
240
  signal trap_data_out  : std_logic_vector(7 downto 0);
241
  signal trap_irq       : std_logic;
242
 
243
  signal rst_i         : std_logic;     -- internal reset signal
244
  signal clk_i         : std_logic;     -- internal master clock signal
245 170 davidgb
 
246 174 davidgb
  signal rs232_cts    :  Std_Logic;
247 170 davidgb
  signal rs232_rts    :  Std_Logic;
248 148 davidgb
 
249 185 davidgb
  signal CountL        : std_logic_vector(23 downto 0);
250 141 davidgb
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
251
  signal Clk25         : std_logic;
252 185 davidgb
 
253
 
254
component btn_debounce
255
    Port ( BTN_I : in  STD_LOGIC_VECTOR (4 downto 0);
256
           CLK : in  STD_LOGIC;
257
           BTN_O : out  STD_LOGIC_VECTOR (4 downto 0));
258
end component;
259
 
260 141 davidgb
 
261
-----------------------------------------------------------------
262
--
263
-- CPU09 CPU core
264
--
265
-----------------------------------------------------------------
266
 
267
component cpu09
268
  port (
269
    clk:      in  std_logic;
270
    rst:      in  std_logic;
271
    vma:      out std_logic;
272
    addr:     out std_logic_vector(15 downto 0);
273
    rw:       out std_logic;     -- Asynchronous memory interface
274
    data_out: out std_logic_vector(7 downto 0);
275
    data_in:  in  std_logic_vector(7 downto 0);
276
    irq:      in  std_logic;
277
    firq:     in  std_logic;
278
    nmi:      in  std_logic;
279
    halt:     in  std_logic;
280
    hold:     in  std_logic
281
  );
282
end component;
283
 
284
----------------------------------------
285
--
286
-- 4K Block RAM Monitor ROM
287 148 davidgb
-- $F000 - $FFFF
288 141 davidgb
--
289
----------------------------------------
290 148 davidgb
 
291 141 davidgb
component mon_rom
292 148 davidgb
  Port (
293
    clk   : in  std_logic;
294
    rst   : in  std_logic;
295
    cs    : in  std_logic;
296
    rw    : in  std_logic;
297
    addr  : in  std_logic_vector (11 downto 0);
298
    data_out : out std_logic_vector (7 downto 0);
299
    data_in : in  std_logic_vector (7 downto 0)
300
  );
301 141 davidgb
end component;
302
 
303
----------------------------------------
304
--
305
-- 8KBytes Block RAM for FLEX9
306
-- $C000 - $DFFF
307
--
308
----------------------------------------
309 148 davidgb
 
310 141 davidgb
component flex_ram
311
  Port (
312
    clk      : in  std_logic;
313
    rst      : in  std_logic;
314
    cs       : in  std_logic;
315
    rw       : in  std_logic;
316
    addr     : in  std_logic_vector (12 downto 0);
317
    data_out    : out std_logic_vector (7 downto 0);
318
    data_in    : in  std_logic_vector (7 downto 0)
319 148 davidgb
  );
320 141 davidgb
end component;
321 170 davidgb
 
322
----------------------------------------
323
--
324
-- 32KBytes Block RAM 0000
325
-- $0000 - $7FFF
326
--
327
----------------------------------------
328 141 davidgb
 
329 170 davidgb
component ram_32k
330
  Port (
331
    clk      : in  std_logic;
332
    rst      : in  std_logic;
333
    cs       : in  std_logic;
334
    rw       : in  std_logic;
335
    addr     : in  std_logic_vector (14 downto 0);
336
    data_out    : out std_logic_vector (7 downto 0);
337
    data_in    : in  std_logic_vector (7 downto 0)
338
  );
339
end component;
340
 
341 173 davidgb
 
342
----------------------------------------
343
--
344
-- 16KBytes Block RAM 8000
345
-- $8000 - $BFFF
346
--
347
----------------------------------------
348 170 davidgb
 
349 173 davidgb
component ram_16k
350
  Port (
351
    clk      : in  std_logic;
352
    rst      : in  std_logic;
353
    cs       : in  std_logic;
354
    rw       : in  std_logic;
355
    addr     : in  std_logic_vector (13 downto 0);
356
    data_out    : out std_logic_vector (7 downto 0);
357
    data_in    : in  std_logic_vector (7 downto 0)
358
  );
359
end component;
360
 
361 141 davidgb
-----------------------------------------------------------------
362
--
363
-- 6850 Compatible ACIA / UART
364
--
365
-----------------------------------------------------------------
366
 
367
component acia6850
368
  port (
369 148 davidgb
    clk      : in  Std_Logic;  -- System Clock
370
    rst      : in  Std_Logic;  -- Reset input (active high)
371
    cs       : in  Std_Logic;  -- miniUART Chip Select
372
    rw       : in  Std_Logic;  -- Read / Not Write
373
    addr     : in  Std_Logic;  -- Register Select
374
    data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
375
    data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
376
    irq      : out Std_Logic;  -- Interrupt
377
    RxC      : in  Std_Logic;  -- Receive Baud Clock
378
    TxC      : in  Std_Logic;  -- Transmit Baud Clock
379
    RxD      : in  Std_Logic;  -- Receive Data
380
    TxD      : out Std_Logic;  -- Transmit Data
381
    DCD_n    : in  Std_Logic;  -- Data Carrier Detect
382
    CTS_n    : in  Std_Logic;  -- Clear To Send
383
    RTS_n    : out Std_Logic   -- Request To send
384
  );
385 141 davidgb
end component;
386
 
387
-----------------------------------------------------------------
388
--
389
-- ACIA Clock divider
390
--
391
-----------------------------------------------------------------
392
 
393
component ACIA_Clock
394
  generic (
395 148 davidgb
    SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
396
    ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
397 141 davidgb
  );
398
  port (
399 148 davidgb
    clk      : in  Std_Logic;  -- System Clock Input
400
    ACIA_clk : out Std_logic   -- ACIA Clock output
401 141 davidgb
  );
402
end component;
403
 
404
----------------------------------------
405
--
406
-- Timer module
407
--
408
----------------------------------------
409
 
410
component timer
411
  port (
412 148 davidgb
    clk       : in std_logic;
413
    rst       : in std_logic;
414
    cs        : in std_logic;
415
    rw        : in std_logic;
416
    addr      : in std_logic;
417
    data_in   : in std_logic_vector(7 downto 0);
418
    data_out  : out std_logic_vector(7 downto 0);
419
    irq       : out std_logic
420
  );
421 141 davidgb
end component;
422
 
423
------------------------------------------------------------
424
--
425
-- Bus Trap logic
426
--
427
------------------------------------------------------------
428
 
429
component trap
430 148 davidgb
  port (
431 141 davidgb
    clk        : in  std_logic;
432
    rst        : in  std_logic;
433
    cs         : in  std_logic;
434
    rw         : in  std_logic;
435
    vma        : in  std_logic;
436
    addr       : in  std_logic_vector(15 downto 0);
437
    data_in    : in  std_logic_vector(7 downto 0);
438
    data_out   : out std_logic_vector(7 downto 0);
439
    irq        : out std_logic
440
  );
441
end component;
442
 
443
----------------------------------------
444
--
445
-- Dynamic Address Translation Registers
446
--
447
----------------------------------------
448 148 davidgb
 
449 141 davidgb
component dat_ram
450
  port (
451
    clk      : in  std_logic;
452
    rst      : in  std_logic;
453
    cs       : in  std_logic;
454
    rw       : in  std_logic;
455
    addr_lo  : in  std_logic_vector(3 downto 0);
456
    addr_hi  : in  std_logic_vector(3 downto 0);
457
    data_in  : in  std_logic_vector(7 downto 0);
458
    data_out : out std_logic_vector(7 downto 0)
459
  );
460
end component;
461 185 davidgb
 
462
 
463 141 davidgb
--
464
-- Clock buffer
465
--
466 148 davidgb
 
467 141 davidgb
component BUFG
468
   Port (
469
     i: in std_logic;
470
     o: out std_logic
471
  );
472
end component;
473
 
474 185 davidgb
begin
475 169 davidgb
 
476 185 davidgb
 
477
 
478
 
479
 
480 169 davidgb
  clk_i <= CLKA;
481 141 davidgb
  -----------------------------------------------------------------------------
482
  -- Instantiation of internal components
483
  -----------------------------------------------------------------------------
484
 
485 148 davidgb
  my_cpu : cpu09
486
    port map (
487
      clk       => cpu_clk,
488
      rst       => cpu_reset,
489
      vma       => cpu_vma,
490
      addr      => cpu_addr(15 downto 0),
491
      rw        => cpu_rw,
492
      data_out  => cpu_data_out,
493
      data_in   => cpu_data_in,
494
      irq       => cpu_irq,
495
      firq      => cpu_firq,
496
      nmi       => cpu_nmi,
497
      halt      => cpu_halt,
498
      hold      => cpu_hold
499
    );
500 141 davidgb
 
501 148 davidgb
  my_rom : mon_rom
502
    port map (
503
      clk   => cpu_clk,
504
      rst   => cpu_reset,
505
      cs    => rom_cs,
506
      rw    => '1',
507
      addr  => cpu_addr(11 downto 0),
508
      data_in => cpu_data_out,
509
      data_out => rom_data_out
510 141 davidgb
    );
511
 
512 148 davidgb
  my_flex : flex_ram
513
    port map (
514
      clk       => cpu_clk,
515
      rst       => cpu_reset,
516
      cs        => flex_cs,
517
      rw        => cpu_rw,
518
      addr      => cpu_addr(12 downto 0),
519
      data_out     => flex_data_out,
520
      data_in     => cpu_data_out
521 170 davidgb
    );
522
 
523
  my_32k : ram_32k
524
    port map (
525
      clk       => cpu_clk,
526
      rst       => cpu_reset,
527 173 davidgb
      cs        => ram1_cs,
528 170 davidgb
      rw        => cpu_rw,
529
      addr      => cpu_addr(14 downto 0),
530 173 davidgb
      data_out     => ram1_data_out,
531 170 davidgb
      data_in     => cpu_data_out
532
    );
533 173 davidgb
 
534
  my_16k : ram_16k
535
    port map (
536
      clk       => cpu_clk,
537
      rst       => cpu_reset,
538
      cs        => ram2_cs,
539
      rw        => cpu_rw,
540
      addr      => cpu_addr(13 downto 0),
541
      data_out     => ram2_data_out,
542
      data_in     => cpu_data_out
543
    );
544
 
545 148 davidgb
  my_acia  : acia6850
546
    port map (
547
      clk       => cpu_clk,
548
      rst       => cpu_reset,
549
      cs        => acia_cs,
550
      rw        => cpu_rw,
551
      addr      => cpu_addr(0),
552
      data_in   => cpu_data_out,
553
      data_out  => acia_data_out,
554
      irq       => acia_irq,
555
      RxC       => acia_clk,
556
      TxC       => acia_clk,
557
      RxD       => rxd,
558
      TxD       => txd,
559
      DCD_n     => dcd_n,
560
      CTS_n     => cts_n,
561
      RTS_n     => rts_n
562 141 davidgb
    );
563
 
564 148 davidgb
  my_ACIA_Clock : ACIA_Clock
565
    generic map(
566 185 davidgb
      SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
567 148 davidgb
      ACIA_CLK_FREQ => ACIA_CLK_FREQ
568
    )
569
    port map(
570
      clk        => Clk_i,
571
      acia_clk   => acia_clk
572
    );
573 141 davidgb
 
574 148 davidgb
  ----------------------------------------
575
  --
576
  -- Timer Module
577
  --
578
  ----------------------------------------
579
  my_timer  : timer
580
    port map (
581
      clk       => cpu_clk,
582
      rst       => cpu_reset,
583
      cs        => timer_cs,
584
      rw        => cpu_rw,
585
      addr      => cpu_addr(0),
586
      data_in   => cpu_data_out,
587
      data_out  => timer_data_out,
588
      irq       => timer_irq
589
    );
590 141 davidgb
 
591 148 davidgb
  ----------------------------------------
592
  --
593
  -- Bus Trap Interrupt logic
594
  --
595
  ----------------------------------------
596
  my_trap : trap
597
    port map (
598
      clk        => cpu_clk,
599
      rst        => cpu_reset,
600
      cs         => trap_cs,
601
      rw         => cpu_rw,
602
      vma        => cpu_vma,
603
      addr       => cpu_addr,
604
      data_in    => cpu_data_out,
605
      data_out   => trap_data_out,
606
      irq        => trap_irq
607 141 davidgb
    );
608
 
609 148 davidgb
  my_dat : dat_ram
610
    port map (
611
      clk       => cpu_clk,
612
      rst       => cpu_reset,
613
      cs        => dat_cs,
614
      rw        => cpu_rw,
615
      addr_hi   => cpu_addr(15 downto 12),
616
      addr_lo   => cpu_addr(3 downto 0),
617
      data_in   => cpu_data_out,
618
      data_out  => dat_addr(7 downto 0)
619 141 davidgb
    );
620
 
621 148 davidgb
  cpu_clk_buffer : BUFG
622 141 davidgb
    port map(
623 148 davidgb
      i => Clk25,
624
      o => cpu_clk
625 141 davidgb
    );
626 162 davidgb
 
627 148 davidgb
  ----------------------------------------------------------------------
628
  --
629
  -- Process to decode memory map
630
  --
631
  ----------------------------------------------------------------------
632 141 davidgb
 
633 148 davidgb
  mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
634 141 davidgb
                     dat_addr,
635
                     rom_data_out,
636
                     flex_data_out,
637
                     acia_data_out,
638
                     timer_data_out,
639
                     trap_data_out,
640 173 davidgb
                     ram1_data_out, ram2_data_out
641 141 davidgb
                     )
642 148 davidgb
  begin
643
    cpu_data_in <= (others=>'0');
644
    dat_cs      <= '0';
645
    rom_cs      <= '0';
646
    flex_cs     <= '0';
647
    acia_cs     <= '0';
648
    timer_cs    <= '0';
649
    trap_cs     <= '0';
650 173 davidgb
    ram1_cs      <= '0';
651
    ram2_cs      <= '0';
652
 
653 148 davidgb
    if cpu_addr( 15 downto 8 ) = "11111111" then  -- $FFxx
654
      cpu_data_in <= rom_data_out;
655
      dat_cs      <= cpu_vma;              -- write DAT
656
      rom_cs      <= cpu_vma;              -- read  ROM
657 141 davidgb
 
658 148 davidgb
    --
659
    -- Sys09Bug Monitor ROM $F000 - $FFFF
660
    --
661
    elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
662
      cpu_data_in <= rom_data_out;
663
      rom_cs      <= cpu_vma;
664 141 davidgb
 
665 148 davidgb
    --
666
    -- IO Devices $E000 - $E7FF
667
    --
668
    elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
669
      case cpu_addr(11 downto 8) is
670
        --
671
        -- SWTPC peripherals from $E000 to $E0FF
672
        --
673
        when "0000" =>
674
          case cpu_addr(7 downto 4) is
675
          --
676
          -- Console Port ACIA $E000 - $E00F
677
          --
678
            when "0000" => -- $E000
679
              cpu_data_in <= acia_data_out;
680
              acia_cs     <= cpu_vma;
681 141 davidgb
 
682 148 davidgb
            --
683
            -- Reserved
684
            -- Floppy Disk Controller port $E010 - $E01F
685
            --
686 141 davidgb
 
687 148 davidgb
            --
688
            -- Reserved SWTPc MP-T Timer $E040 - $E04F
689
            --
690
            when "0100" => -- $E040
691
              cpu_data_in <= (others=> '0');
692 141 davidgb
 
693 148 davidgb
            --
694
            -- Timer $E050 - $E05F
695
            --
696
            when "0101" => -- $E050
697
              cpu_data_in <= timer_data_out;
698
              timer_cs    <= cpu_vma;
699 141 davidgb
 
700 148 davidgb
            --
701
            -- Bus Trap Logic $E060 - $E06F
702
            --
703
            when "0110" => -- $E060
704
              cpu_data_in <= trap_data_out;
705
              trap_cs     <= cpu_vma;
706 141 davidgb
 
707 148 davidgb
            --
708
            -- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
709
            --
710
 
711
            --
712
            -- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
713
            --
714
 
715
            --
716
            -- Remaining 6 slots reserved for non SWTPc Peripherals
717
            --
718
            when others => -- $E0A0 to $E0FF
719
              null;
720
          end case;
721
 
722
        --
723
        -- $E200 to $EFFF reserved for future use
724
        --
725
        when others =>
726 141 davidgb
           null;
727 148 davidgb
      end case;
728 141 davidgb
 
729 148 davidgb
    --
730
    -- Flex RAM $0C000 - $0DFFF
731
    --
732
    elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
733
      cpu_data_in <= flex_data_out;
734
      flex_cs     <= cpu_vma;
735 170 davidgb
 
736
    --
737
    -- 32k RAM $00000 - $07FFF
738
    --
739
    elsif dat_addr(7 downto 1) = "0000000" then -- $00000 - $07FFF
740 173 davidgb
      cpu_data_in <= ram1_data_out;
741
      ram1_cs     <= cpu_vma;
742
 
743
    --
744
    -- 16k RAM $08000 - $0BFFF
745
    --
746
    elsif dat_addr(7 downto 1) = "0000100" then -- $08000 - $0BFFF
747
      cpu_data_in <= ram2_data_out;
748
      ram2_cs     <= cpu_vma;
749 141 davidgb
 
750 148 davidgb
    --
751
    -- Everything else is RAM
752
    --
753 141 davidgb
    else
754 173 davidgb
      cpu_data_in <= (others => '0');
755
      ram3_cs      <= cpu_vma;
756 141 davidgb
    end if;
757
 
758 148 davidgb
  end process;
759 141 davidgb
 
760 148 davidgb
  --
761
  -- Interrupts and other bus control signals
762
  --
763 185 davidgb
  interrupts : process( SW3_N,
764 141 davidgb
                      acia_irq,
765
                      trap_irq,
766
                      timer_irq
767
                      )
768 148 davidgb
  begin
769 162 davidgb
    cpu_irq    <= acia_irq;
770 185 davidgb
    cpu_nmi    <= trap_irq or not( SW3_N );
771 141 davidgb
    cpu_firq   <= timer_irq;
772
    cpu_halt   <= '0';
773 170 davidgb
    cpu_hold   <= '0'; -- pb_hold or ram_hold;
774 148 davidgb
  end process;
775 141 davidgb
 
776 148 davidgb
  --
777 185 davidgb
  -- Flash 7 segment LEDS
778 148 davidgb
  --
779 185 davidgb
  my_led_flasher: process( clk_i, rst_i, CountL )
780 148 davidgb
  begin
781 185 davidgb
    if rst_i = '1' then
782
         CountL <= "000000000000000000000000";
783
    elsif rising_edge(clk_i) then
784
         CountL <= CountL + 1;
785 141 davidgb
    end if;
786 185 davidgb
    --S(7 downto 0) <= CountL(23 downto 16);
787
  end process;
788 141 davidgb
 
789 148 davidgb
  --
790 185 davidgb
  -- Generate CPU & Pixel Clock from Memory Clock
791
  --
792
--  my_prescaler : process( clk_i, clk_count )
793
--  begin
794
--    if rising_edge( clk_i ) then
795
--      if clk_count = 0 then
796
--        clk_count <= CPU_CLK_DIV-1;
797
--      else
798
--        clk_count <= clk_count - 1;
799
--      end if;
800
--      if clk_count = 0 then
801
--         clk25 <= '0';
802
--      elsif clk_count = (CPU_CLK_DIV/2) then
803
--         clk25 <= '1';
804
--      end if;
805
--    end if;
806
--  end process;
807
 
808
 
809
  my_singlestep: btn_debounce
810
    port map ( BTN_I => btn, CLK => CLKA, BTN_O => pbtn);
811
  SW2_N <= pbtn(0);
812
  SW3_N <= pbtn(1);
813
  clk25 <= pbtn(2);
814
 
815
  --
816 148 davidgb
  -- Reset button and reset timer
817
  --
818 185 davidgb
  my_switch_assignments : process( rst_i, SW2_N)
819 148 davidgb
  begin
820 185 davidgb
    rst_i <= SW2_N;
821 162 davidgb
    cpu_reset <= rst_i;
822 148 davidgb
  end process;
823 141 davidgb
 
824 148 davidgb
  --
825
  -- RS232 signals:
826
  --
827
  my_acia_assignments : process( RS232_RXD, RS232_CTS, txd, rts_n )
828
  begin
829
    rxd       <= RS232_RXD;
830
    cts_n     <= RS232_CTS;
831
    dcd_n     <= '0';
832
    RS232_TXD <= txd;
833
    RS232_RTS <= rts_n;
834
  end process;
835 141 davidgb
 
836 185 davidgb
  status_leds : process( rst_i, cpu_reset,cpu_addr, cpu_rw, sw)
837
  begin
838
    S(7) <= '0';
839
    S(6) <= cpu_rw;
840
         S(5) <= cpu_vma;
841
         S(4) <= '0';
842
    case sw is
843
         when "00000000" =>
844
           S(3 downto 0) <= cpu_addr(3 downto 0);
845
    when "00000001" =>
846
           S(3 downto 0) <= cpu_addr(7 downto 4);
847
         when "00000010" =>
848
           S(3 downto 0) <= cpu_addr(11 downto 8);
849
    when "00000011" =>
850
           S(3 downto 0) <= cpu_addr(15 downto 12);
851
    when "00000100" =>
852
           S(3 downto 0) <= cpu_data_in(3 downto 0);
853
    when "00000101" =>
854
           S(3 downto 0) <= cpu_data_in(7 downto 4);
855
    when others => S(3 downto 0) <= (others => '0');
856
         end case;
857
  end process;
858
 
859 148 davidgb
--  debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
860 141 davidgb
--                      cpu_halt, cpu_hold,
861
--                      cpu_firq, cpu_irq, cpu_nmi,
862
--                      cpu_addr, cpu_data_out, cpu_data_in )
863 148 davidgb
--  begin
864
--    cpu_reset_o    <= cpu_reset;
865
--    cpu_clk_o      <= cpu_clk;
866
--    cpu_rw_o       <= cpu_rw;
867
--    cpu_vma_o      <= cpu_vma;
868
--    cpu_halt_o     <= cpu_halt;
869
--    cpu_hold_o     <= cpu_hold;
870
--    cpu_firq_o     <= cpu_firq;
871
--    cpu_irq_o      <= cpu_irq;
872
--    cpu_nmi_o      <= cpu_nmi;
873
--    cpu_addr_o     <= cpu_addr;
874
--    cpu_data_out_o <= cpu_data_out;
875
--    cpu_data_in_o  <= cpu_data_in;
876
--  end process;
877 141 davidgb
 
878
end rtl; --===================== End of architecture =======================--
879
 

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