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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_Atlys/] [system09.vhd] - Blame information for rev 195

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1 141 davidgb
--===========================================================================----
2
--
3
--  S Y N T H E Z I A B L E    System09 - SOC.
4
--
5
--  www.OpenCores.Org - February 2007
6
--  This core adheres to the GNU public license  
7
--
8
-- File name      : System09_Xess_XSA-3S1000.vhd
9
--
10
-- Purpose        : Top level file for 6809 compatible system on a chip
11
--                  Designed with Xilinx XC3S1000 Spartan 3 FPGA.
12
--                  Implemented With XESS XSA-3S1000 FPGA board.
13
--                  *** Note ***
14
--                  This configuration can run Flex9 however it only has
15
--                  32k bytes of user memory and the VDU is monochrome
16
--                  The design needs to be updated to use the SDRAM on 
17
--                  the XSA-3S1000 board.
18
--                  This configuration also lacks a DAT so cannot use
19
--                  the RAM Disk features of SYS09BUG.
20
--
21
-- Dependencies   : ieee.Std_Logic_1164
22
--                  ieee.std_logic_unsigned
23
--                  ieee.std_logic_arith
24
--                  ieee.numeric_std
25
--                  unisim.vcomponents
26
--
27
-- Uses           : mon_rom    (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
28
--                  cpu09      (cpu09.vhd)          CPU core
29
--                  ACIA_6850  (acia6850.vhd)      ACIA / UART
30
--                  ACIA_Clock (ACIA_Clock.vhd)      ACIA clock.
31
--                  timer      (timer.vhd)            Interrupt timer
32
--                  trap       (trap.vhd)             Bus condition trap logic
33
--                  flex_ram   (flex9_ram8k_b16.vhd)  Flex operating system
34
--                  ram_32K    (ram32k_b16.vhd)       32 KBytes of Block RAM
35
--                  
36
-- 
37
-- Author         : John E. Kent      
38
--                  dilbert57@opencores.org      
39
--
40
-- Memory Map     :
41
--
42
-- $0000 - User program RAM (32K Bytes)
43
-- $C000 - Flex Operating System memory (8K Bytes)
44
-- $E000 - ACIA (SWTPc)
45
-- $E010 - Reserved for FD1771 FDC (SWTPc)
46
-- $E050 - Timer
47
-- $E060 - Bus trap
48
-- $E070 - Reserced for Parallel I/O (B5-X300)
49
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
50
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
51
-- $F000 - Sys09Bug monitor Program (4K Bytes)
52
--
53
--===========================================================================----
54
--
55
-- Revision History:
56
--===========================================================================--
57
-- Version 0.1 - 20 March 2003
58
-- Version 0.2 - 30 March 2003
59
-- Version 0.3 - 29 April 2003
60
-- Version 0.4 - 29 June 2003
61
--
62
-- Version 0.5 - 19 July 2003
63
-- prints out "Hello World"
64
--
65
-- Version 0.6 - 5 September 2003
66
-- Runs SBUG
67
--
68
-- Version 1.0- 6 Sep 2003 - John Kent
69
-- Inverted SysClk
70
-- Initial release to Open Cores
71
--
72
-- Version 1.1 - 17 Jan 2004 - John Kent
73
-- Updated miniUart.
74
--
75
-- Version 1.2 - 25 Jan 2004 - John Kent
76
-- removed signals "test_alu" and "test_cc" 
77
-- Trap hardware re-instated.
78
--
79
-- Version 1.3 - 11 Feb 2004 - John Kent
80
-- Designed forked off to produce System09_VDU
81
-- Added VDU component
82
-- VDU runs at 25MHz and divides the clock by 2 for the CPU
83
-- UART Runs at 57.6 Kbps
84
--
85
-- Version 2.0 - 2 September 2004 - John Kent
86
-- ported to Digilent Xilinx Spartan3 starter board
87
-- removed Compact Flash and Trap Logic.
88
-- Replaced SBUG with KBug9s
89
--
90
-- Version 3.0 - 29th August 2006 - John Kent
91
-- Adapted to XSA-3S1000 board.
92
-- Removed DAT and miniUART.
93
-- Used 32KBytes of Block RAM.
94
--
95
-- Version 3.1 - 15th January 2007 - John Kent
96
-- Modified vdu8 interface
97
-- Added a clock divider
98
--
99
-- Version 3.2 - 25th February 2007 - John Kent
100
-- reinstated ACIA_6850 and ACIA_Clock
101
-- Updated VDU8 & Keyboard with generic parameters
102
-- Defined Constants for clock speed calculations
103
--
104
-- Version 3.3 - 1st July 2007 - John Kent
105
-- Made VDU mono to save on one RAMB16
106
-- Used distributed memory for Key Map ROM to save one RAMB16
107
-- Added Flex RAM at $C000 to $DFFF using 4 spare RAMB16s
108
-- Added timer and trap logic
109
-- Added IDE Interface for Compact Flash
110
-- Replaced KBug9s and stack with Sys09Bug.
111
--
112
-- Version 4.0 - 1st February 2008 - John kent
113
-- Replaced Block RAM with SDRAM Interface
114
-- Modified Hold timing for SDRAM
115
-- Added CF and Ethernet interface 
116
-- via the 16 bit peripheral bus at $E100
117
--
118
--===========================================================================--
119
library ieee;
120
   use ieee.std_logic_1164.all;
121
   use IEEE.STD_LOGIC_ARITH.ALL;
122
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
123
   use ieee.numeric_std.all;
124
library work;
125
   use work.common.all;
126
library unisim;
127 162 davidgb
   use unisim.vcomponents.all;
128 141 davidgb
 
129
entity system09 is
130
  port(
131
    CLKA         : in  Std_Logic;  -- 100MHz Clock input
132 192 davidgb
    RESET        : in  Std_logic;  -- Master Reset input (active high) -- red "RESET" PB
133
    NMI          : in  Std_logic;  -- Non Maskable Interrupt input (active high) -- Center PB
134 141 davidgb
 
135 192 davidgb
    -- RS232 Port - via Pmod RS232
136 195 davidgb
--  RS232_CTS    : in  Std_Logic;
137
--  RS232_RTS    : out Std_Logic;
138 185 davidgb
    RS232_RXD    : in  Std_Logic;
139
    RS232_TXD    : out Std_Logic;
140 141 davidgb
 
141 186 davidgb
    -- slide switches
142 192 davidgb
         sw           : in std_logic_vector(2 downto 0);
143 186 davidgb
    -- Status 7 segment LED
144 192 davidgb
    S            : out std_logic_vector(7 downto 0)
145 185 davidgb
 
146 141 davidgb
-- CPU Debug Interface signals
147
--    cpu_reset_o     : out Std_Logic;
148
--    cpu_clk_o       : out Std_Logic;
149
--    cpu_rw_o        : out std_logic;
150
--    cpu_vma_o       : out std_logic;
151
--    cpu_halt_o      : out std_logic;
152
--    cpu_hold_o      : out std_logic;
153
--    cpu_firq_o      : out std_logic;
154
--    cpu_irq_o       : out std_logic;
155
--    cpu_nmi_o       : out std_logic;
156
--    cpu_addr_o      : out std_logic_vector(15 downto 0);
157
--    cpu_data_in_o   : out std_logic_vector(7 downto 0);
158
--    cpu_data_out_o  : out std_logic_vector(7 downto 0);
159
 
160 148 davidgb
  );
161 141 davidgb
end system09;
162
 
163
-------------------------------------------------------------------------------
164
-- Architecture for System09
165
-------------------------------------------------------------------------------
166
architecture rtl of system09 is
167
 
168
  -----------------------------------------------------------------------------
169
  -- constants
170
  -----------------------------------------------------------------------------
171 186 davidgb
  constant CLOCK_MODE           : natural := 0; -- 0 means normal, 1 means single-step
172
 
173 192 davidgb
  constant SYS_CLK_FREQ         : natural := 100_000_000;  -- FPGA System Clock (in Hz)
174 186 davidgb
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
175 141 davidgb
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
176
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
177
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
178
 
179
  -----------------------------------------------------------------------------
180
  -- Signals
181 174 davidgb
  -----------------------------------------------------------------------------
182 192 davidgb
 
183 141 davidgb
  -- BOOT ROM
184
  signal rom_cs         : Std_logic;
185
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
186
 
187
  -- Flex Memory & Monitor Stack
188
  signal flex_cs        : Std_logic;
189
  signal flex_data_out  : Std_Logic_Vector(7 downto 0);
190
 
191
  -- ACIA/UART Interface signals
192
  signal acia_data_out  : Std_Logic_Vector(7 downto 0);
193
  signal acia_cs        : Std_Logic;
194
  signal acia_irq       : Std_Logic;
195
  signal acia_clk       : Std_Logic;
196 192 davidgb
  signal RXD            : Std_Logic;
197
  signal TXD            : Std_Logic;
198 141 davidgb
  signal DCD_n          : Std_Logic;
199
  signal RTS_n          : Std_Logic;
200
  signal CTS_n          : Std_Logic;
201
 
202
  -- RAM
203 173 davidgb
  signal ram1_cs         : std_logic;
204
  signal ram1_data_out   : std_logic_vector(7 downto 0);
205
  signal ram2_cs         : std_logic;
206
  signal ram2_data_out   : std_logic_vector(7 downto 0);
207
  signal ram3_cs         : std_logic;
208 141 davidgb
 
209
  -- CPU Interface signals
210
  signal cpu_reset      : Std_Logic;
211
  signal cpu_clk        : Std_Logic;
212
  signal cpu_rw         : std_logic;
213
  signal cpu_vma        : std_logic;
214
  signal cpu_halt       : std_logic;
215
  signal cpu_hold       : std_logic;
216
  signal cpu_firq       : std_logic;
217
  signal cpu_irq        : std_logic;
218
  signal cpu_nmi        : std_logic;
219
  signal cpu_addr       : std_logic_vector(15 downto 0);
220
  signal cpu_data_in    : std_logic_vector(7 downto 0);
221
  signal cpu_data_out   : std_logic_vector(7 downto 0);
222
 
223
  -- Dynamic Address Translation
224
  signal dat_cs       : std_logic;
225
  signal dat_addr     : std_logic_vector(7 downto 0);
226
 
227
  -- timer
228
  signal timer_data_out : std_logic_vector(7 downto 0);
229
  signal timer_cs       : std_logic;
230
  signal timer_irq      : std_logic;
231
 
232
  -- trap
233
  signal trap_cs        : std_logic;
234
  signal trap_data_out  : std_logic_vector(7 downto 0);
235
  signal trap_irq       : std_logic;
236
 
237
  signal rst_i         : std_logic;     -- internal reset signal
238 186 davidgb
  signal clk_i         : std_logic;     -- internal master clock signal
239 148 davidgb
 
240 194 davidgb
  signal CountL        : std_logic_vector(24 downto 0);
241 141 davidgb
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
242
  signal Clk25         : std_logic;
243
 
244
-----------------------------------------------------------------
245
--
246
-- CPU09 CPU core
247
--
248
-----------------------------------------------------------------
249
 
250
component cpu09
251
  port (
252
    clk:      in  std_logic;
253
    rst:      in  std_logic;
254
    vma:      out std_logic;
255
    addr:     out std_logic_vector(15 downto 0);
256
    rw:       out std_logic;     -- Asynchronous memory interface
257
    data_out: out std_logic_vector(7 downto 0);
258
    data_in:  in  std_logic_vector(7 downto 0);
259
    irq:      in  std_logic;
260
    firq:     in  std_logic;
261
    nmi:      in  std_logic;
262
    halt:     in  std_logic;
263
    hold:     in  std_logic
264
  );
265
end component;
266
 
267
----------------------------------------
268
--
269
-- 4K Block RAM Monitor ROM
270 148 davidgb
-- $F000 - $FFFF
271 141 davidgb
--
272
----------------------------------------
273 148 davidgb
 
274 141 davidgb
component mon_rom
275 148 davidgb
  Port (
276
    clk   : in  std_logic;
277
    rst   : in  std_logic;
278
    cs    : in  std_logic;
279
    rw    : in  std_logic;
280
    addr  : in  std_logic_vector (11 downto 0);
281
    data_out : out std_logic_vector (7 downto 0);
282
    data_in : in  std_logic_vector (7 downto 0)
283
  );
284 141 davidgb
end component;
285
 
286
----------------------------------------
287
--
288
-- 8KBytes Block RAM for FLEX9
289
-- $C000 - $DFFF
290
--
291
----------------------------------------
292 148 davidgb
 
293 141 davidgb
component flex_ram
294
  Port (
295
    clk      : in  std_logic;
296
    rst      : in  std_logic;
297
    cs       : in  std_logic;
298
    rw       : in  std_logic;
299
    addr     : in  std_logic_vector (12 downto 0);
300
    data_out    : out std_logic_vector (7 downto 0);
301
    data_in    : in  std_logic_vector (7 downto 0)
302 148 davidgb
  );
303 141 davidgb
end component;
304 170 davidgb
 
305
----------------------------------------
306
--
307
-- 32KBytes Block RAM 0000
308
-- $0000 - $7FFF
309
--
310
----------------------------------------
311 141 davidgb
 
312 170 davidgb
component ram_32k
313
  Port (
314
    clk      : in  std_logic;
315
    rst      : in  std_logic;
316
    cs       : in  std_logic;
317
    rw       : in  std_logic;
318
    addr     : in  std_logic_vector (14 downto 0);
319
    data_out    : out std_logic_vector (7 downto 0);
320
    data_in    : in  std_logic_vector (7 downto 0)
321
  );
322
end component;
323
 
324 173 davidgb
 
325
----------------------------------------
326
--
327
-- 16KBytes Block RAM 8000
328
-- $8000 - $BFFF
329
--
330
----------------------------------------
331 170 davidgb
 
332 173 davidgb
component ram_16k
333
  Port (
334
    clk      : in  std_logic;
335
    rst      : in  std_logic;
336
    cs       : in  std_logic;
337
    rw       : in  std_logic;
338
    addr     : in  std_logic_vector (13 downto 0);
339
    data_out    : out std_logic_vector (7 downto 0);
340
    data_in    : in  std_logic_vector (7 downto 0)
341
  );
342
end component;
343
 
344 141 davidgb
-----------------------------------------------------------------
345
--
346
-- 6850 Compatible ACIA / UART
347
--
348
-----------------------------------------------------------------
349
 
350
component acia6850
351
  port (
352 148 davidgb
    clk      : in  Std_Logic;  -- System Clock
353
    rst      : in  Std_Logic;  -- Reset input (active high)
354
    cs       : in  Std_Logic;  -- miniUART Chip Select
355
    rw       : in  Std_Logic;  -- Read / Not Write
356
    addr     : in  Std_Logic;  -- Register Select
357
    data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
358
    data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
359
    irq      : out Std_Logic;  -- Interrupt
360
    RxC      : in  Std_Logic;  -- Receive Baud Clock
361
    TxC      : in  Std_Logic;  -- Transmit Baud Clock
362
    RxD      : in  Std_Logic;  -- Receive Data
363
    TxD      : out Std_Logic;  -- Transmit Data
364
    DCD_n    : in  Std_Logic;  -- Data Carrier Detect
365
    CTS_n    : in  Std_Logic;  -- Clear To Send
366
    RTS_n    : out Std_Logic   -- Request To send
367
  );
368 141 davidgb
end component;
369
 
370
-----------------------------------------------------------------
371
--
372
-- ACIA Clock divider
373
--
374
-----------------------------------------------------------------
375
 
376
component ACIA_Clock
377
  generic (
378 148 davidgb
    SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
379
    ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
380 141 davidgb
  );
381
  port (
382 148 davidgb
    clk      : in  Std_Logic;  -- System Clock Input
383
    ACIA_clk : out Std_logic   -- ACIA Clock output
384 141 davidgb
  );
385
end component;
386
 
387
----------------------------------------
388
--
389
-- Timer module
390
--
391
----------------------------------------
392
 
393
component timer
394
  port (
395 148 davidgb
    clk       : in std_logic;
396
    rst       : in std_logic;
397
    cs        : in std_logic;
398
    rw        : in std_logic;
399
    addr      : in std_logic;
400
    data_in   : in std_logic_vector(7 downto 0);
401
    data_out  : out std_logic_vector(7 downto 0);
402
    irq       : out std_logic
403
  );
404 141 davidgb
end component;
405
 
406
------------------------------------------------------------
407
--
408
-- Bus Trap logic
409
--
410
------------------------------------------------------------
411
 
412
component trap
413 148 davidgb
  port (
414 141 davidgb
    clk        : in  std_logic;
415
    rst        : in  std_logic;
416
    cs         : in  std_logic;
417
    rw         : in  std_logic;
418
    vma        : in  std_logic;
419
    addr       : in  std_logic_vector(15 downto 0);
420
    data_in    : in  std_logic_vector(7 downto 0);
421
    data_out   : out std_logic_vector(7 downto 0);
422
    irq        : out std_logic
423
  );
424
end component;
425
 
426
----------------------------------------
427
--
428
-- Dynamic Address Translation Registers
429
--
430
----------------------------------------
431 148 davidgb
 
432 141 davidgb
component dat_ram
433
  port (
434
    clk      : in  std_logic;
435
    rst      : in  std_logic;
436
    cs       : in  std_logic;
437
    rw       : in  std_logic;
438
    addr_lo  : in  std_logic_vector(3 downto 0);
439
    addr_hi  : in  std_logic_vector(3 downto 0);
440
    data_in  : in  std_logic_vector(7 downto 0);
441
    data_out : out std_logic_vector(7 downto 0)
442
  );
443
end component;
444 185 davidgb
 
445 141 davidgb
--
446
-- Clock buffer
447
--
448 148 davidgb
 
449 141 davidgb
component BUFG
450
   Port (
451
     i: in std_logic;
452
     o: out std_logic
453
  );
454
end component;
455
 
456 185 davidgb
begin
457
 
458 186 davidgb
  --
459
  -- Generate CPU & Pixel Clock from Memory Clock
460
  --
461 192 davidgb
 
462
  my_prescaler : process( clk_i, clk_count )
463
  begin
464
    if rising_edge( clk_i ) then
465
      if clk_count = 0 then
466
        clk_count <= CPU_CLK_DIV-1;
467
      else
468
        clk_count <= clk_count - 1;
469 186 davidgb
      end if;
470 192 davidgb
      if clk_count = 0 then
471
         clk25 <= '0';
472
      elsif clk_count = (CPU_CLK_DIV/2) then
473
         clk25 <= '1';
474
      end if;
475
    end if;
476
  end process;
477 186 davidgb
 
478
  --
479
  -- Reset button and reset timer
480
  --
481 192 davidgb
  my_switch_assignments : process( rst_i, RESET)
482 186 davidgb
  begin
483 194 davidgb
    rst_i <= not RESET;
484 186 davidgb
    cpu_reset <= rst_i;
485
  end process;
486 185 davidgb
 
487 186 davidgb
  clk_i <= CLKA;
488
 
489 141 davidgb
  -----------------------------------------------------------------------------
490
  -- Instantiation of internal components
491
  -----------------------------------------------------------------------------
492
 
493 148 davidgb
  my_cpu : cpu09
494
    port map (
495
      clk       => cpu_clk,
496
      rst       => cpu_reset,
497
      vma       => cpu_vma,
498
      addr      => cpu_addr(15 downto 0),
499
      rw        => cpu_rw,
500
      data_out  => cpu_data_out,
501
      data_in   => cpu_data_in,
502
      irq       => cpu_irq,
503
      firq      => cpu_firq,
504
      nmi       => cpu_nmi,
505
      halt      => cpu_halt,
506
      hold      => cpu_hold
507
    );
508 141 davidgb
 
509 148 davidgb
  my_rom : mon_rom
510
    port map (
511 192 davidgb
      clk       => cpu_clk,
512
      rst       => cpu_reset,
513
      cs        => rom_cs,
514
      rw        => '1',
515
      addr      => cpu_addr(11 downto 0),
516
      data_in   => cpu_data_out,
517
      data_out  => rom_data_out
518 141 davidgb
    );
519
 
520 148 davidgb
  my_flex : flex_ram
521
    port map (
522
      clk       => cpu_clk,
523
      rst       => cpu_reset,
524
      cs        => flex_cs,
525
      rw        => cpu_rw,
526
      addr      => cpu_addr(12 downto 0),
527 192 davidgb
      data_out  => flex_data_out,
528
      data_in   => cpu_data_out
529 170 davidgb
    );
530
 
531
  my_32k : ram_32k
532
    port map (
533
      clk       => cpu_clk,
534
      rst       => cpu_reset,
535 173 davidgb
      cs        => ram1_cs,
536 170 davidgb
      rw        => cpu_rw,
537
      addr      => cpu_addr(14 downto 0),
538 192 davidgb
      data_out  => ram1_data_out,
539
      data_in   => cpu_data_out
540 170 davidgb
    );
541 173 davidgb
 
542
  my_16k : ram_16k
543
    port map (
544
      clk       => cpu_clk,
545
      rst       => cpu_reset,
546
      cs        => ram2_cs,
547
      rw        => cpu_rw,
548
      addr      => cpu_addr(13 downto 0),
549 192 davidgb
      data_out  => ram2_data_out,
550
      data_in   => cpu_data_out
551 173 davidgb
    );
552
 
553 148 davidgb
  my_acia  : acia6850
554
    port map (
555
      clk       => cpu_clk,
556
      rst       => cpu_reset,
557
      cs        => acia_cs,
558
      rw        => cpu_rw,
559
      addr      => cpu_addr(0),
560
      data_in   => cpu_data_out,
561
      data_out  => acia_data_out,
562
      irq       => acia_irq,
563
      RxC       => acia_clk,
564
      TxC       => acia_clk,
565 192 davidgb
      RxD       => RXD,
566
      TxD       => TXD,
567
      DCD_n     => DCD_n,
568
      CTS_n     => CTS_n,
569
      RTS_n     => RTS_n
570
    );
571
 
572
  --
573
  -- RS232 signals:
574
  --
575 195 davidgb
  my_acia_assignments : process( RS232_RXD, -- RS232_CTS,
576
                                 TXD, RTS_n )
577 192 davidgb
  begin
578
    RXD       <= RS232_RXD;
579 195 davidgb
    CTS_n     <= '0'; -- RS232_CTS;
580 192 davidgb
    DCD_n     <= '0';
581
    RS232_TXD <= TXD;
582 195 davidgb
--  RS232_RTS <= not RTS_n;
583 192 davidgb
  end process;
584 186 davidgb
 
585 148 davidgb
  my_ACIA_Clock : ACIA_Clock
586
    generic map(
587 185 davidgb
      SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
588 148 davidgb
      ACIA_CLK_FREQ => ACIA_CLK_FREQ
589
    )
590
    port map(
591 192 davidgb
      clk        => clk_i,
592 148 davidgb
      acia_clk   => acia_clk
593
    );
594 141 davidgb
 
595 148 davidgb
  ----------------------------------------
596
  --
597
  -- Timer Module
598
  --
599
  ----------------------------------------
600
  my_timer  : timer
601
    port map (
602
      clk       => cpu_clk,
603
      rst       => cpu_reset,
604
      cs        => timer_cs,
605
      rw        => cpu_rw,
606
      addr      => cpu_addr(0),
607
      data_in   => cpu_data_out,
608
      data_out  => timer_data_out,
609
      irq       => timer_irq
610
    );
611 141 davidgb
 
612 148 davidgb
  ----------------------------------------
613
  --
614
  -- Bus Trap Interrupt logic
615
  --
616
  ----------------------------------------
617
  my_trap : trap
618
    port map (
619
      clk        => cpu_clk,
620
      rst        => cpu_reset,
621
      cs         => trap_cs,
622
      rw         => cpu_rw,
623
      vma        => cpu_vma,
624
      addr       => cpu_addr,
625
      data_in    => cpu_data_out,
626
      data_out   => trap_data_out,
627
      irq        => trap_irq
628 141 davidgb
    );
629
 
630 148 davidgb
  my_dat : dat_ram
631
    port map (
632
      clk       => cpu_clk,
633
      rst       => cpu_reset,
634
      cs        => dat_cs,
635
      rw        => cpu_rw,
636
      addr_hi   => cpu_addr(15 downto 12),
637
      addr_lo   => cpu_addr(3 downto 0),
638
      data_in   => cpu_data_out,
639
      data_out  => dat_addr(7 downto 0)
640 141 davidgb
    );
641
 
642 148 davidgb
  cpu_clk_buffer : BUFG
643 141 davidgb
    port map(
644 148 davidgb
      i => Clk25,
645
      o => cpu_clk
646 141 davidgb
    );
647 162 davidgb
 
648 148 davidgb
  ----------------------------------------------------------------------
649
  --
650
  -- Process to decode memory map
651
  --
652
  ----------------------------------------------------------------------
653 141 davidgb
 
654 148 davidgb
  mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
655 141 davidgb
                     dat_addr,
656
                     rom_data_out,
657
                     flex_data_out,
658
                     acia_data_out,
659
                     timer_data_out,
660
                     trap_data_out,
661 173 davidgb
                     ram1_data_out, ram2_data_out
662 141 davidgb
                     )
663 148 davidgb
  begin
664
    cpu_data_in <= (others=>'0');
665
    dat_cs      <= '0';
666
    rom_cs      <= '0';
667
    flex_cs     <= '0';
668
    acia_cs     <= '0';
669
    timer_cs    <= '0';
670
    trap_cs     <= '0';
671 192 davidgb
    ram1_cs     <= '0';
672
    ram2_cs     <= '0';
673
    ram3_cs     <= '0';
674 173 davidgb
 
675 148 davidgb
    if cpu_addr( 15 downto 8 ) = "11111111" then  -- $FFxx
676
      cpu_data_in <= rom_data_out;
677
      dat_cs      <= cpu_vma;              -- write DAT
678
      rom_cs      <= cpu_vma;              -- read  ROM
679 141 davidgb
 
680 148 davidgb
    --
681
    -- Sys09Bug Monitor ROM $F000 - $FFFF
682
    --
683
    elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
684
      cpu_data_in <= rom_data_out;
685
      rom_cs      <= cpu_vma;
686 141 davidgb
 
687 148 davidgb
    --
688
    -- IO Devices $E000 - $E7FF
689
    --
690
    elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
691
      case cpu_addr(11 downto 8) is
692
        --
693
        -- SWTPC peripherals from $E000 to $E0FF
694
        --
695
        when "0000" =>
696
          case cpu_addr(7 downto 4) is
697
          --
698
          -- Console Port ACIA $E000 - $E00F
699
          --
700
            when "0000" => -- $E000
701
              cpu_data_in <= acia_data_out;
702
              acia_cs     <= cpu_vma;
703 141 davidgb
 
704 148 davidgb
            --
705
            -- Reserved
706
            -- Floppy Disk Controller port $E010 - $E01F
707
            --
708 141 davidgb
 
709 148 davidgb
            --
710
            -- Reserved SWTPc MP-T Timer $E040 - $E04F
711
            --
712
            when "0100" => -- $E040
713
              cpu_data_in <= (others=> '0');
714 141 davidgb
 
715 148 davidgb
            --
716
            -- Timer $E050 - $E05F
717
            --
718
            when "0101" => -- $E050
719
              cpu_data_in <= timer_data_out;
720
              timer_cs    <= cpu_vma;
721 141 davidgb
 
722 148 davidgb
            --
723
            -- Bus Trap Logic $E060 - $E06F
724
            --
725
            when "0110" => -- $E060
726
              cpu_data_in <= trap_data_out;
727
              trap_cs     <= cpu_vma;
728 141 davidgb
 
729 148 davidgb
            --
730
            -- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
731
            --
732
 
733
            --
734
            -- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
735
            --
736
 
737
            --
738
            -- Remaining 6 slots reserved for non SWTPc Peripherals
739
            --
740
            when others => -- $E0A0 to $E0FF
741
              null;
742
          end case;
743
 
744
        --
745
        -- $E200 to $EFFF reserved for future use
746
        --
747
        when others =>
748 141 davidgb
           null;
749 148 davidgb
      end case;
750 170 davidgb
 
751
    --
752 192 davidgb
    -- Block RAM (32k) $00000 - $07FFF
753 170 davidgb
    --
754 192 davidgb
    elsif dat_addr(7 downto 3) = "00000"   then -- $00000 - $07FFF
755 173 davidgb
      cpu_data_in <= ram1_data_out;
756
      ram1_cs     <= cpu_vma;
757
 
758
    --
759 192 davidgb
    -- Block RAM (16k) $08000 - $0BFFF
760 173 davidgb
    --
761 192 davidgb
    elsif dat_addr(7 downto 2) = "000010"  then -- $08000 - $0BFFF
762 173 davidgb
      cpu_data_in <= ram2_data_out;
763
      ram2_cs     <= cpu_vma;
764 141 davidgb
 
765 148 davidgb
    --
766 192 davidgb
    -- Flex RAM (8k) $0C000 - $0DFFF
767
    --
768
    elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
769
      cpu_data_in <= flex_data_out;
770
      flex_cs     <= cpu_vma;
771
 
772
    --
773 148 davidgb
    -- Everything else is RAM
774
    --
775 141 davidgb
    else
776 173 davidgb
      cpu_data_in <= (others => '0');
777
      ram3_cs      <= cpu_vma;
778 141 davidgb
    end if;
779
 
780 148 davidgb
  end process;
781 141 davidgb
 
782 148 davidgb
  --
783
  -- Interrupts and other bus control signals
784
  --
785 192 davidgb
  interrupts : process( NMI,
786 141 davidgb
                      acia_irq,
787
                      trap_irq,
788
                      timer_irq
789
                      )
790 148 davidgb
  begin
791 162 davidgb
    cpu_irq    <= acia_irq;
792 192 davidgb
    cpu_nmi    <= trap_irq or NMI;
793 141 davidgb
    cpu_firq   <= timer_irq;
794
    cpu_halt   <= '0';
795 170 davidgb
    cpu_hold   <= '0'; -- pb_hold or ram_hold;
796 148 davidgb
  end process;
797 192 davidgb
 
798 148 davidgb
  --
799 185 davidgb
  -- Flash 7 segment LEDS
800 148 davidgb
  --
801 185 davidgb
  my_led_flasher: process( clk_i, rst_i, CountL )
802 148 davidgb
  begin
803 185 davidgb
    if rst_i = '1' then
804 194 davidgb
         CountL <= "0000000000000000000000000";
805 185 davidgb
    elsif rising_edge(clk_i) then
806
         CountL <= CountL + 1;
807 141 davidgb
    end if;
808 192 davidgb
  end process;
809 141 davidgb
 
810 192 davidgb
  status_leds : process( rst_i, cpu_reset, cpu_addr, NMI, cpu_data_in, cpu_rw, CountL, sw)
811 185 davidgb
  begin
812
    S(7) <= '0';
813 194 davidgb
    S(6) <= CountL(24);
814
         S(5) <= cpu_reset;
815 192 davidgb
         S(4) <= NMI;
816 185 davidgb
    case sw is
817 192 davidgb
         when "000" =>
818 185 davidgb
           S(3 downto 0) <= cpu_addr(3 downto 0);
819 192 davidgb
    when "001" =>
820 185 davidgb
           S(3 downto 0) <= cpu_addr(7 downto 4);
821 192 davidgb
         when "010" =>
822 185 davidgb
           S(3 downto 0) <= cpu_addr(11 downto 8);
823 192 davidgb
    when "011" =>
824 185 davidgb
           S(3 downto 0) <= cpu_addr(15 downto 12);
825 192 davidgb
    when "100" =>
826 185 davidgb
           S(3 downto 0) <= cpu_data_in(3 downto 0);
827 192 davidgb
    when "101" =>
828 185 davidgb
           S(3 downto 0) <= cpu_data_in(7 downto 4);
829
    when others => S(3 downto 0) <= (others => '0');
830
         end case;
831
  end process;
832
 
833 148 davidgb
--  debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
834 141 davidgb
--                      cpu_halt, cpu_hold,
835
--                      cpu_firq, cpu_irq, cpu_nmi,
836
--                      cpu_addr, cpu_data_out, cpu_data_in )
837 148 davidgb
--  begin
838
--    cpu_reset_o    <= cpu_reset;
839
--    cpu_clk_o      <= cpu_clk;
840
--    cpu_rw_o       <= cpu_rw;
841
--    cpu_vma_o      <= cpu_vma;
842
--    cpu_halt_o     <= cpu_halt;
843
--    cpu_hold_o     <= cpu_hold;
844
--    cpu_firq_o     <= cpu_firq;
845
--    cpu_irq_o      <= cpu_irq;
846
--    cpu_nmi_o      <= cpu_nmi;
847
--    cpu_addr_o     <= cpu_addr;
848
--    cpu_data_out_o <= cpu_data_out;
849
--    cpu_data_in_o  <= cpu_data_in;
850
--  end process;
851 141 davidgb
 
852
end rtl; --===================== End of architecture =======================--
853
 

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