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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_Atlys/] [system09.vhd] - Blame information for rev 209

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1 141 davidgb
--===========================================================================----
2
--
3
--  S Y N T H E Z I A B L E    System09 - SOC.
4
--
5
--  www.OpenCores.Org - February 2007
6
--  This core adheres to the GNU public license  
7
--
8
-- File name      : System09_Xess_XSA-3S1000.vhd
9
--
10
-- Purpose        : Top level file for 6809 compatible system on a chip
11
--                  Designed with Xilinx XC3S1000 Spartan 3 FPGA.
12
--                  Implemented With XESS XSA-3S1000 FPGA board.
13
--                  *** Note ***
14
--                  This configuration can run Flex9 however it only has
15
--                  32k bytes of user memory and the VDU is monochrome
16
--                  The design needs to be updated to use the SDRAM on 
17
--                  the XSA-3S1000 board.
18
--                  This configuration also lacks a DAT so cannot use
19
--                  the RAM Disk features of SYS09BUG.
20
--
21
-- Dependencies   : ieee.Std_Logic_1164
22
--                  ieee.std_logic_unsigned
23
--                  ieee.std_logic_arith
24
--                  ieee.numeric_std
25
--                  unisim.vcomponents
26
--
27
-- Uses           : mon_rom    (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
28
--                  cpu09      (cpu09.vhd)          CPU core
29
--                  ACIA_6850  (acia6850.vhd)      ACIA / UART
30
--                  ACIA_Clock (ACIA_Clock.vhd)      ACIA clock.
31
--                  timer      (timer.vhd)            Interrupt timer
32
--                  trap       (trap.vhd)             Bus condition trap logic
33
--                  flex_ram   (flex9_ram8k_b16.vhd)  Flex operating system
34
--                  ram_32K    (ram32k_b16.vhd)       32 KBytes of Block RAM
35
--                  
36
-- 
37
-- Author         : John E. Kent      
38
--                  dilbert57@opencores.org      
39
--
40
-- Memory Map     :
41
--
42
-- $0000 - User program RAM (32K Bytes)
43
-- $C000 - Flex Operating System memory (8K Bytes)
44
-- $E000 - ACIA (SWTPc)
45
-- $E010 - Reserved for FD1771 FDC (SWTPc)
46
-- $E050 - Timer
47
-- $E060 - Bus trap
48
-- $E070 - Reserced for Parallel I/O (B5-X300)
49
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
50
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
51
-- $F000 - Sys09Bug monitor Program (4K Bytes)
52
--
53
--===========================================================================----
54
--
55
-- Revision History:
56
--===========================================================================--
57
-- Version 0.1 - 20 March 2003
58
-- Version 0.2 - 30 March 2003
59
-- Version 0.3 - 29 April 2003
60
-- Version 0.4 - 29 June 2003
61
--
62
-- Version 0.5 - 19 July 2003
63
-- prints out "Hello World"
64
--
65
-- Version 0.6 - 5 September 2003
66
-- Runs SBUG
67
--
68
-- Version 1.0- 6 Sep 2003 - John Kent
69
-- Inverted SysClk
70
-- Initial release to Open Cores
71
--
72
-- Version 1.1 - 17 Jan 2004 - John Kent
73
-- Updated miniUart.
74
--
75
-- Version 1.2 - 25 Jan 2004 - John Kent
76
-- removed signals "test_alu" and "test_cc" 
77
-- Trap hardware re-instated.
78
--
79
-- Version 1.3 - 11 Feb 2004 - John Kent
80
-- Designed forked off to produce System09_VDU
81
-- Added VDU component
82
-- VDU runs at 25MHz and divides the clock by 2 for the CPU
83
-- UART Runs at 57.6 Kbps
84
--
85
-- Version 2.0 - 2 September 2004 - John Kent
86
-- ported to Digilent Xilinx Spartan3 starter board
87
-- removed Compact Flash and Trap Logic.
88
-- Replaced SBUG with KBug9s
89
--
90
-- Version 3.0 - 29th August 2006 - John Kent
91
-- Adapted to XSA-3S1000 board.
92
-- Removed DAT and miniUART.
93
-- Used 32KBytes of Block RAM.
94
--
95
-- Version 3.1 - 15th January 2007 - John Kent
96
-- Modified vdu8 interface
97
-- Added a clock divider
98
--
99
-- Version 3.2 - 25th February 2007 - John Kent
100
-- reinstated ACIA_6850 and ACIA_Clock
101
-- Updated VDU8 & Keyboard with generic parameters
102
-- Defined Constants for clock speed calculations
103
--
104
-- Version 3.3 - 1st July 2007 - John Kent
105
-- Made VDU mono to save on one RAMB16
106
-- Used distributed memory for Key Map ROM to save one RAMB16
107
-- Added Flex RAM at $C000 to $DFFF using 4 spare RAMB16s
108
-- Added timer and trap logic
109
-- Added IDE Interface for Compact Flash
110
-- Replaced KBug9s and stack with Sys09Bug.
111
--
112
-- Version 4.0 - 1st February 2008 - John kent
113
-- Replaced Block RAM with SDRAM Interface
114
-- Modified Hold timing for SDRAM
115
-- Added CF and Ethernet interface 
116
-- via the 16 bit peripheral bus at $E100
117
--
118
--===========================================================================--
119
library ieee;
120
   use ieee.std_logic_1164.all;
121
   use IEEE.STD_LOGIC_ARITH.ALL;
122
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
123
   use ieee.numeric_std.all;
124
library work;
125
   use work.common.all;
126
library unisim;
127 162 davidgb
   use unisim.vcomponents.all;
128 141 davidgb
 
129
entity system09 is
130
  port(
131
    CLKA         : in  Std_Logic;  -- 100MHz Clock input
132 192 davidgb
    RESET        : in  Std_logic;  -- Master Reset input (active high) -- red "RESET" PB
133
    NMI          : in  Std_logic;  -- Non Maskable Interrupt input (active high) -- Center PB
134 141 davidgb
 
135 209 davidgb
    -- PS/2 Keyboard
136
    ps2_clk      : inout Std_logic;
137
    ps2_dat      : inout Std_Logic;
138
 
139
    -- VGA port output
140
--  VGA_red      : out std_logic_vector(3 downto 0);
141
    VGA_green    : out std_logic_vector(3 downto 0);
142
--  VGA_blue     : out std_logic_vector(3 downto 0);
143
    VGA_hsync_n  : out std_logic;
144
    VGA_vsync_n  : out std_logic;
145
 
146
    -- HDMI output
147
--  TMDSp_clock  : out std_logic;
148
--  TMDSn_clock  : out std_logic;
149
--  TMDSp        : out std_logic_vector(2 downto 0);
150
--  TMDSn        : out std_logic_vector(2 downto 0);
151
 
152 192 davidgb
    -- RS232 Port - via Pmod RS232
153 195 davidgb
--  RS232_CTS    : in  Std_Logic;
154
--  RS232_RTS    : out Std_Logic;
155 185 davidgb
    RS232_RXD    : in  Std_Logic;
156
    RS232_TXD    : out Std_Logic;
157 141 davidgb
 
158 186 davidgb
    -- slide switches
159 209 davidgb
    sw           : in std_logic_vector(2 downto 0);
160 186 davidgb
    -- Status 7 segment LED
161 192 davidgb
    S            : out std_logic_vector(7 downto 0)
162 185 davidgb
 
163 141 davidgb
-- CPU Debug Interface signals
164
--    cpu_reset_o     : out Std_Logic;
165
--    cpu_clk_o       : out Std_Logic;
166
--    cpu_rw_o        : out std_logic;
167
--    cpu_vma_o       : out std_logic;
168
--    cpu_halt_o      : out std_logic;
169
--    cpu_hold_o      : out std_logic;
170
--    cpu_firq_o      : out std_logic;
171
--    cpu_irq_o       : out std_logic;
172
--    cpu_nmi_o       : out std_logic;
173
--    cpu_addr_o      : out std_logic_vector(15 downto 0);
174
--    cpu_data_in_o   : out std_logic_vector(7 downto 0);
175
--    cpu_data_out_o  : out std_logic_vector(7 downto 0);
176
 
177 148 davidgb
  );
178 141 davidgb
end system09;
179
 
180
-------------------------------------------------------------------------------
181
-- Architecture for System09
182
-------------------------------------------------------------------------------
183
architecture rtl of system09 is
184
 
185
  -----------------------------------------------------------------------------
186
  -- constants
187
  -----------------------------------------------------------------------------
188 186 davidgb
  constant CLOCK_MODE           : natural := 0; -- 0 means normal, 1 means single-step
189
 
190 192 davidgb
  constant SYS_CLK_FREQ         : natural := 100_000_000;  -- FPGA System Clock (in Hz)
191 186 davidgb
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
192 141 davidgb
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
193 209 davidgb
  constant VGA_CLK_FREQ         : natural := 25_000_000;  -- VGA Pixel Clock
194
  constant VGA_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
195 141 davidgb
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
196
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
197
 
198
  -----------------------------------------------------------------------------
199
  -- Signals
200 174 davidgb
  -----------------------------------------------------------------------------
201 192 davidgb
 
202 141 davidgb
  -- BOOT ROM
203
  signal rom_cs         : Std_logic;
204
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
205
 
206
  -- Flex Memory & Monitor Stack
207
  signal flex_cs        : Std_logic;
208
  signal flex_data_out  : Std_Logic_Vector(7 downto 0);
209
 
210
  -- ACIA/UART Interface signals
211
  signal acia_data_out  : Std_Logic_Vector(7 downto 0);
212
  signal acia_cs        : Std_Logic;
213
  signal acia_irq       : Std_Logic;
214
  signal acia_clk       : Std_Logic;
215 192 davidgb
  signal RXD            : Std_Logic;
216
  signal TXD            : Std_Logic;
217 141 davidgb
  signal DCD_n          : Std_Logic;
218
  signal RTS_n          : Std_Logic;
219
  signal CTS_n          : Std_Logic;
220 209 davidgb
 
221
  -- keyboard port
222
  signal keyboard_data_out : std_logic_vector(7 downto 0);
223
  signal keyboard_cs       : std_logic;
224
  signal keyboard_irq      : std_logic;
225
 
226 141 davidgb
  -- RAM
227 173 davidgb
  signal ram1_cs         : std_logic;
228
  signal ram1_data_out   : std_logic_vector(7 downto 0);
229
  signal ram2_cs         : std_logic;
230
  signal ram2_data_out   : std_logic_vector(7 downto 0);
231
  signal ram3_cs         : std_logic;
232 141 davidgb
 
233
  -- CPU Interface signals
234
  signal cpu_reset      : Std_Logic;
235
  signal cpu_clk        : Std_Logic;
236
  signal cpu_rw         : std_logic;
237
  signal cpu_vma        : std_logic;
238
  signal cpu_halt       : std_logic;
239
  signal cpu_hold       : std_logic;
240
  signal cpu_firq       : std_logic;
241
  signal cpu_irq        : std_logic;
242
  signal cpu_nmi        : std_logic;
243
  signal cpu_addr       : std_logic_vector(15 downto 0);
244
  signal cpu_data_in    : std_logic_vector(7 downto 0);
245
  signal cpu_data_out   : std_logic_vector(7 downto 0);
246
 
247
  -- Dynamic Address Translation
248
  signal dat_cs       : std_logic;
249
  signal dat_addr     : std_logic_vector(7 downto 0);
250
 
251 209 davidgb
  -- Video Display Unit
252
  signal vdu_clk        : std_logic;
253
  signal vdu_cs         : std_logic;
254
  signal vdu_data_out   : std_logic_vector(7 downto 0);
255
  signal vdu_red        : std_logic;
256
  signal vdu_green      : std_logic;
257
  signal vdu_blue       : std_logic;
258
  signal vdu_hsync      : std_logic;
259
  signal vdu_vsync      : std_logic;
260
 
261 141 davidgb
  -- timer
262
  signal timer_data_out : std_logic_vector(7 downto 0);
263
  signal timer_cs       : std_logic;
264
  signal timer_irq      : std_logic;
265
 
266
  -- trap
267
  signal trap_cs        : std_logic;
268
  signal trap_data_out  : std_logic_vector(7 downto 0);
269
  signal trap_irq       : std_logic;
270
 
271
  signal rst_i         : std_logic;     -- internal reset signal
272 186 davidgb
  signal clk_i         : std_logic;     -- internal master clock signal
273 148 davidgb
 
274 194 davidgb
  signal CountL        : std_logic_vector(24 downto 0);
275 141 davidgb
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
276
  signal Clk25         : std_logic;
277
 
278
-----------------------------------------------------------------
279
--
280
-- CPU09 CPU core
281
--
282
-----------------------------------------------------------------
283
 
284
component cpu09
285
  port (
286
    clk:      in  std_logic;
287
    rst:      in  std_logic;
288
    vma:      out std_logic;
289
    addr:     out std_logic_vector(15 downto 0);
290
    rw:       out std_logic;     -- Asynchronous memory interface
291
    data_out: out std_logic_vector(7 downto 0);
292
    data_in:  in  std_logic_vector(7 downto 0);
293
    irq:      in  std_logic;
294
    firq:     in  std_logic;
295
    nmi:      in  std_logic;
296
    halt:     in  std_logic;
297
    hold:     in  std_logic
298
  );
299
end component;
300
 
301
----------------------------------------
302
--
303
-- 4K Block RAM Monitor ROM
304 148 davidgb
-- $F000 - $FFFF
305 141 davidgb
--
306
----------------------------------------
307 148 davidgb
 
308 141 davidgb
component mon_rom
309 148 davidgb
  Port (
310
    clk   : in  std_logic;
311
    rst   : in  std_logic;
312
    cs    : in  std_logic;
313
    rw    : in  std_logic;
314
    addr  : in  std_logic_vector (11 downto 0);
315
    data_out : out std_logic_vector (7 downto 0);
316
    data_in : in  std_logic_vector (7 downto 0)
317
  );
318 141 davidgb
end component;
319
 
320
----------------------------------------
321
--
322
-- 8KBytes Block RAM for FLEX9
323
-- $C000 - $DFFF
324
--
325
----------------------------------------
326 148 davidgb
 
327 141 davidgb
component flex_ram
328
  Port (
329
    clk      : in  std_logic;
330
    rst      : in  std_logic;
331
    cs       : in  std_logic;
332
    rw       : in  std_logic;
333
    addr     : in  std_logic_vector (12 downto 0);
334
    data_out    : out std_logic_vector (7 downto 0);
335
    data_in    : in  std_logic_vector (7 downto 0)
336 148 davidgb
  );
337 141 davidgb
end component;
338 170 davidgb
 
339
----------------------------------------
340
--
341
-- 32KBytes Block RAM 0000
342
-- $0000 - $7FFF
343
--
344
----------------------------------------
345 141 davidgb
 
346 170 davidgb
component ram_32k
347
  Port (
348
    clk      : in  std_logic;
349
    rst      : in  std_logic;
350
    cs       : in  std_logic;
351
    rw       : in  std_logic;
352
    addr     : in  std_logic_vector (14 downto 0);
353
    data_out    : out std_logic_vector (7 downto 0);
354
    data_in    : in  std_logic_vector (7 downto 0)
355
  );
356
end component;
357
 
358 173 davidgb
 
359
----------------------------------------
360
--
361
-- 16KBytes Block RAM 8000
362
-- $8000 - $BFFF
363
--
364
----------------------------------------
365 170 davidgb
 
366 173 davidgb
component ram_16k
367
  Port (
368
    clk      : in  std_logic;
369
    rst      : in  std_logic;
370
    cs       : in  std_logic;
371
    rw       : in  std_logic;
372
    addr     : in  std_logic_vector (13 downto 0);
373
    data_out    : out std_logic_vector (7 downto 0);
374
    data_in    : in  std_logic_vector (7 downto 0)
375
  );
376
end component;
377
 
378 141 davidgb
-----------------------------------------------------------------
379
--
380
-- 6850 Compatible ACIA / UART
381
--
382
-----------------------------------------------------------------
383
 
384
component acia6850
385
  port (
386 148 davidgb
    clk      : in  Std_Logic;  -- System Clock
387
    rst      : in  Std_Logic;  -- Reset input (active high)
388
    cs       : in  Std_Logic;  -- miniUART Chip Select
389
    rw       : in  Std_Logic;  -- Read / Not Write
390
    addr     : in  Std_Logic;  -- Register Select
391
    data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
392
    data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
393
    irq      : out Std_Logic;  -- Interrupt
394
    RxC      : in  Std_Logic;  -- Receive Baud Clock
395
    TxC      : in  Std_Logic;  -- Transmit Baud Clock
396
    RxD      : in  Std_Logic;  -- Receive Data
397
    TxD      : out Std_Logic;  -- Transmit Data
398
    DCD_n    : in  Std_Logic;  -- Data Carrier Detect
399
    CTS_n    : in  Std_Logic;  -- Clear To Send
400
    RTS_n    : out Std_Logic   -- Request To send
401
  );
402 141 davidgb
end component;
403
 
404
-----------------------------------------------------------------
405
--
406
-- ACIA Clock divider
407
--
408
-----------------------------------------------------------------
409
 
410
component ACIA_Clock
411
  generic (
412 148 davidgb
    SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
413
    ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
414 141 davidgb
  );
415
  port (
416 148 davidgb
    clk      : in  Std_Logic;  -- System Clock Input
417
    ACIA_clk : out Std_logic   -- ACIA Clock output
418 141 davidgb
  );
419
end component;
420
 
421
----------------------------------------
422
--
423 209 davidgb
-- PS/2 Keyboard
424
--
425
----------------------------------------
426
 
427
component keyboard
428
  generic(
429
    KBD_CLK_FREQ : integer := CPU_CLK_FREQ
430
  );
431
  port(
432
    clk             : in    std_logic;
433
    rst             : in    std_logic;
434
    cs              : in    std_logic;
435
    rw              : in    std_logic;
436
    addr            : in    std_logic;
437
    data_in         : in    std_logic_vector(7 downto 0);
438
    data_out        : out   std_logic_vector(7 downto 0);
439
    irq             : out   std_logic;
440
    kbd_clk         : inout std_logic;
441
    kbd_data        : inout std_logic
442
  );
443
end component;
444
 
445
 
446
----------------------------------------
447
--
448
-- Video Display Unit.
449
--
450
----------------------------------------
451
 
452
component vdu8
453
  generic(
454
    VDU_CLK_FREQ           : integer := CPU_CLK_FREQ; -- HZ
455
    VGA_CLK_FREQ           : integer := VGA_CLK_FREQ; -- HZ
456
    VGA_HOR_CHARS          : integer := 80; -- CHARACTERS
457
    VGA_VER_CHARS          : integer := 25; -- CHARACTERS
458
    VGA_PIX_PER_CHAR       : integer := 8;  -- PIXELS
459
    VGA_LIN_PER_CHAR       : integer := 16; -- LINES
460
    VGA_HOR_BACK_PORCH     : integer := 40; -- PIXELS
461
    VGA_HOR_SYNC           : integer := 96; -- PIXELS
462
    VGA_HOR_FRONT_PORCH    : integer := 24; -- PIXELS
463
    VGA_VER_BACK_PORCH     : integer := 13; -- LINES
464
    VGA_VER_SYNC           : integer := 2;  -- LINES
465
    VGA_VER_FRONT_PORCH    : integer := 35  -- LINES
466
  );
467
  port(
468
    -- control register interface
469
    vdu_clk      : in  std_logic;  -- CPU Clock - 25MHz
470
    vdu_rst      : in  std_logic;
471
    vdu_cs       : in  std_logic;
472
    vdu_rw       : in  std_logic;
473
    vdu_addr     : in  std_logic_vector(2 downto 0);
474
    vdu_data_in  : in  std_logic_vector(7 downto 0);
475
    vdu_data_out : out std_logic_vector(7 downto 0);
476
 
477
    -- vga port connections
478
    vga_clk      : in  std_logic; -- VGA Pixel Clock - 25 MHz
479
    vga_red_o    : out std_logic;
480
    vga_green_o  : out std_logic;
481
    vga_blue_o   : out std_logic;
482
    vga_hsync_o  : out std_logic;
483
    vga_vsync_o  : out std_logic
484
  );
485
end component;
486
 
487
----------------------------------------
488
--
489 141 davidgb
-- Timer module
490
--
491
----------------------------------------
492
 
493
component timer
494
  port (
495 148 davidgb
    clk       : in std_logic;
496
    rst       : in std_logic;
497
    cs        : in std_logic;
498
    rw        : in std_logic;
499
    addr      : in std_logic;
500
    data_in   : in std_logic_vector(7 downto 0);
501
    data_out  : out std_logic_vector(7 downto 0);
502
    irq       : out std_logic
503
  );
504 141 davidgb
end component;
505
 
506
------------------------------------------------------------
507
--
508
-- Bus Trap logic
509
--
510
------------------------------------------------------------
511
 
512
component trap
513 148 davidgb
  port (
514 141 davidgb
    clk        : in  std_logic;
515
    rst        : in  std_logic;
516
    cs         : in  std_logic;
517
    rw         : in  std_logic;
518
    vma        : in  std_logic;
519
    addr       : in  std_logic_vector(15 downto 0);
520
    data_in    : in  std_logic_vector(7 downto 0);
521
    data_out   : out std_logic_vector(7 downto 0);
522
    irq        : out std_logic
523
  );
524
end component;
525
 
526
----------------------------------------
527
--
528
-- Dynamic Address Translation Registers
529
--
530
----------------------------------------
531 148 davidgb
 
532 141 davidgb
component dat_ram
533
  port (
534
    clk      : in  std_logic;
535
    rst      : in  std_logic;
536
    cs       : in  std_logic;
537
    rw       : in  std_logic;
538
    addr_lo  : in  std_logic_vector(3 downto 0);
539
    addr_hi  : in  std_logic_vector(3 downto 0);
540
    data_in  : in  std_logic_vector(7 downto 0);
541
    data_out : out std_logic_vector(7 downto 0)
542
  );
543
end component;
544 185 davidgb
 
545 141 davidgb
--
546
-- Clock buffer
547
--
548 148 davidgb
 
549 141 davidgb
component BUFG
550
   Port (
551
     i: in std_logic;
552
     o: out std_logic
553
  );
554
end component;
555
 
556 185 davidgb
begin
557
 
558 186 davidgb
  --
559
  -- Generate CPU & Pixel Clock from Memory Clock
560
  --
561 192 davidgb
 
562
  my_prescaler : process( clk_i, clk_count )
563
  begin
564
    if rising_edge( clk_i ) then
565
      if clk_count = 0 then
566
        clk_count <= CPU_CLK_DIV-1;
567
      else
568
        clk_count <= clk_count - 1;
569 186 davidgb
      end if;
570 192 davidgb
      if clk_count = 0 then
571
         clk25 <= '0';
572
      elsif clk_count = (CPU_CLK_DIV/2) then
573
         clk25 <= '1';
574
      end if;
575
    end if;
576
  end process;
577 186 davidgb
 
578
  --
579
  -- Reset button and reset timer
580
  --
581 192 davidgb
  my_switch_assignments : process( rst_i, RESET)
582 186 davidgb
  begin
583 194 davidgb
    rst_i <= not RESET;
584 186 davidgb
    cpu_reset <= rst_i;
585
  end process;
586 185 davidgb
 
587 186 davidgb
  clk_i <= CLKA;
588
 
589 141 davidgb
  -----------------------------------------------------------------------------
590
  -- Instantiation of internal components
591
  -----------------------------------------------------------------------------
592
 
593 148 davidgb
  my_cpu : cpu09
594
    port map (
595
      clk       => cpu_clk,
596
      rst       => cpu_reset,
597
      vma       => cpu_vma,
598
      addr      => cpu_addr(15 downto 0),
599
      rw        => cpu_rw,
600
      data_out  => cpu_data_out,
601
      data_in   => cpu_data_in,
602
      irq       => cpu_irq,
603
      firq      => cpu_firq,
604
      nmi       => cpu_nmi,
605
      halt      => cpu_halt,
606
      hold      => cpu_hold
607
    );
608 141 davidgb
 
609 148 davidgb
  my_rom : mon_rom
610
    port map (
611 192 davidgb
      clk       => cpu_clk,
612
      rst       => cpu_reset,
613
      cs        => rom_cs,
614
      rw        => '1',
615
      addr      => cpu_addr(11 downto 0),
616
      data_in   => cpu_data_out,
617
      data_out  => rom_data_out
618 141 davidgb
    );
619
 
620 148 davidgb
  my_flex : flex_ram
621
    port map (
622
      clk       => cpu_clk,
623
      rst       => cpu_reset,
624
      cs        => flex_cs,
625
      rw        => cpu_rw,
626
      addr      => cpu_addr(12 downto 0),
627 192 davidgb
      data_out  => flex_data_out,
628
      data_in   => cpu_data_out
629 170 davidgb
    );
630
 
631
  my_32k : ram_32k
632
    port map (
633
      clk       => cpu_clk,
634
      rst       => cpu_reset,
635 173 davidgb
      cs        => ram1_cs,
636 170 davidgb
      rw        => cpu_rw,
637
      addr      => cpu_addr(14 downto 0),
638 192 davidgb
      data_out  => ram1_data_out,
639
      data_in   => cpu_data_out
640 170 davidgb
    );
641 173 davidgb
 
642
  my_16k : ram_16k
643
    port map (
644
      clk       => cpu_clk,
645
      rst       => cpu_reset,
646
      cs        => ram2_cs,
647
      rw        => cpu_rw,
648
      addr      => cpu_addr(13 downto 0),
649 192 davidgb
      data_out  => ram2_data_out,
650
      data_in   => cpu_data_out
651 173 davidgb
    );
652
 
653 148 davidgb
  my_acia  : acia6850
654
    port map (
655
      clk       => cpu_clk,
656
      rst       => cpu_reset,
657
      cs        => acia_cs,
658
      rw        => cpu_rw,
659
      addr      => cpu_addr(0),
660
      data_in   => cpu_data_out,
661
      data_out  => acia_data_out,
662
      irq       => acia_irq,
663
      RxC       => acia_clk,
664
      TxC       => acia_clk,
665 192 davidgb
      RxD       => RXD,
666
      TxD       => TXD,
667
      DCD_n     => DCD_n,
668
      CTS_n     => CTS_n,
669
      RTS_n     => RTS_n
670
    );
671
 
672
  --
673
  -- RS232 signals:
674
  --
675 195 davidgb
  my_acia_assignments : process( RS232_RXD, -- RS232_CTS,
676
                                 TXD, RTS_n )
677 192 davidgb
  begin
678
    RXD       <= RS232_RXD;
679 195 davidgb
    CTS_n     <= '0'; -- RS232_CTS;
680 192 davidgb
    DCD_n     <= '0';
681
    RS232_TXD <= TXD;
682 195 davidgb
--  RS232_RTS <= not RTS_n;
683 192 davidgb
  end process;
684 186 davidgb
 
685 148 davidgb
  my_ACIA_Clock : ACIA_Clock
686
    generic map(
687 185 davidgb
      SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
688 148 davidgb
      ACIA_CLK_FREQ => ACIA_CLK_FREQ
689
    )
690
    port map(
691 192 davidgb
      clk        => clk_i,
692 148 davidgb
      acia_clk   => acia_clk
693
    );
694 141 davidgb
 
695 148 davidgb
  ----------------------------------------
696
  --
697 209 davidgb
  -- PS/2 Keyboard Interface
698
  --
699
  ----------------------------------------
700
  my_keyboard : keyboard
701
    generic map (
702
      KBD_CLK_FREQ => CPU_CLK_FREQ
703
    )
704
    port map(
705
      clk          => cpu_clk,
706
      rst          => cpu_reset,
707
      cs           => keyboard_cs,
708
      rw           => cpu_rw,
709
      addr         => cpu_addr(0),
710
      data_in      => cpu_data_out(7 downto 0),
711
      data_out     => keyboard_data_out(7 downto 0),
712
      irq          => keyboard_irq,
713
      kbd_clk      => ps2_clk,
714
      kbd_data     => ps2_dat
715
    );
716
 
717
  ----------------------------------------
718
  --
719
  -- Video Display Unit instantiation
720
  --
721
  ----------------------------------------
722
  vdu_clk_buffer : BUFG
723
    port map(
724
      i => Clk25,
725
      o => vdu_clk
726
    );
727
 
728
  my_vdu : vdu8
729
    generic map(
730
      VDU_CLK_FREQ           => CPU_CLK_FREQ, -- HZ
731
      VGA_CLK_FREQ           => VGA_CLK_FREQ, -- HZ
732
      VGA_HOR_CHARS          => 80, -- CHARACTERS
733
      VGA_VER_CHARS          => 25, -- CHARACTERS
734
      VGA_PIX_PER_CHAR       => 8,  -- PIXELS
735
      VGA_LIN_PER_CHAR       => 16, -- LINES
736
      VGA_HOR_BACK_PORCH     => 40, -- PIXELS
737
      VGA_HOR_SYNC           => 96, -- PIXELS
738
      VGA_HOR_FRONT_PORCH    => 24, -- PIXELS
739
      VGA_VER_BACK_PORCH     => 13, -- LINES
740
      VGA_VER_SYNC           => 2,  -- LINES
741
      VGA_VER_FRONT_PORCH    => 35  -- LINES
742
    )
743
    port map(
744
      -- Control Registers
745
      vdu_clk       => cpu_clk,               -- 12.5 MHz System Clock in
746
      vdu_rst       => cpu_reset,
747
      vdu_cs        => vdu_cs,
748
      vdu_rw        => cpu_rw,
749
      vdu_addr      => cpu_addr(2 downto 0),
750
      vdu_data_in   => cpu_data_out,
751
      vdu_data_out  => vdu_data_out,
752
      -- vga port connections
753
      vga_clk       => vdu_clk,               -- 25 MHz VDU pixel clock
754
      vga_red_o     => vdu_red,
755
      vga_green_o   => vdu_green,
756
      vga_blue_o    => vdu_blue,
757
      vga_hsync_o   => vdu_hsync,
758
      vga_vsync_o   => vdu_vsync
759
   );
760
 
761
  --
762
  -- VGA ouputs
763
  --
764
  my_vga_assignments : process( vdu_red, vdu_green, vdu_blue )
765
  begin
766
    VGA_green(0) <= vdu_green;
767
    VGA_green(1) <= vdu_green;
768
    VGA_green(2) <= vdu_green;
769
    VGA_green(3) <= vdu_green;
770
  end process;
771
  VGA_hsync_n <= vdu_hsync;
772
  VGA_vsync_n <= vdu_vsync;
773
 
774
  ----------------------------------------
775
  --
776 148 davidgb
  -- Timer Module
777
  --
778
  ----------------------------------------
779
  my_timer  : timer
780
    port map (
781
      clk       => cpu_clk,
782
      rst       => cpu_reset,
783
      cs        => timer_cs,
784
      rw        => cpu_rw,
785
      addr      => cpu_addr(0),
786
      data_in   => cpu_data_out,
787
      data_out  => timer_data_out,
788
      irq       => timer_irq
789
    );
790 141 davidgb
 
791 148 davidgb
  ----------------------------------------
792
  --
793
  -- Bus Trap Interrupt logic
794
  --
795
  ----------------------------------------
796
  my_trap : trap
797
    port map (
798
      clk        => cpu_clk,
799
      rst        => cpu_reset,
800
      cs         => trap_cs,
801
      rw         => cpu_rw,
802
      vma        => cpu_vma,
803
      addr       => cpu_addr,
804
      data_in    => cpu_data_out,
805
      data_out   => trap_data_out,
806
      irq        => trap_irq
807 141 davidgb
    );
808
 
809 148 davidgb
  my_dat : dat_ram
810
    port map (
811
      clk       => cpu_clk,
812
      rst       => cpu_reset,
813
      cs        => dat_cs,
814
      rw        => cpu_rw,
815
      addr_hi   => cpu_addr(15 downto 12),
816
      addr_lo   => cpu_addr(3 downto 0),
817
      data_in   => cpu_data_out,
818
      data_out  => dat_addr(7 downto 0)
819 141 davidgb
    );
820
 
821 148 davidgb
  cpu_clk_buffer : BUFG
822 141 davidgb
    port map(
823 148 davidgb
      i => Clk25,
824
      o => cpu_clk
825 141 davidgb
    );
826 162 davidgb
 
827 148 davidgb
  ----------------------------------------------------------------------
828
  --
829
  -- Process to decode memory map
830
  --
831
  ----------------------------------------------------------------------
832 141 davidgb
 
833 148 davidgb
  mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
834 141 davidgb
                     dat_addr,
835
                     rom_data_out,
836
                     flex_data_out,
837
                     acia_data_out,
838 209 davidgb
                     keyboard_data_out,
839
                     vdu_data_out,
840 141 davidgb
                     timer_data_out,
841
                     trap_data_out,
842 173 davidgb
                     ram1_data_out, ram2_data_out
843 141 davidgb
                     )
844 148 davidgb
  begin
845
    cpu_data_in <= (others=>'0');
846
    dat_cs      <= '0';
847
    rom_cs      <= '0';
848
    flex_cs     <= '0';
849
    acia_cs     <= '0';
850 209 davidgb
    keyboard_cs <= '0';
851
    vdu_cs      <= '0';
852 148 davidgb
    timer_cs    <= '0';
853
    trap_cs     <= '0';
854 192 davidgb
    ram1_cs     <= '0';
855
    ram2_cs     <= '0';
856
    ram3_cs     <= '0';
857 173 davidgb
 
858 148 davidgb
    if cpu_addr( 15 downto 8 ) = "11111111" then  -- $FFxx
859
      cpu_data_in <= rom_data_out;
860
      dat_cs      <= cpu_vma;              -- write DAT
861
      rom_cs      <= cpu_vma;              -- read  ROM
862 141 davidgb
 
863 148 davidgb
    --
864
    -- Sys09Bug Monitor ROM $F000 - $FFFF
865
    --
866
    elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
867
      cpu_data_in <= rom_data_out;
868
      rom_cs      <= cpu_vma;
869 141 davidgb
 
870 148 davidgb
    --
871
    -- IO Devices $E000 - $E7FF
872
    --
873
    elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
874
      case cpu_addr(11 downto 8) is
875
        --
876
        -- SWTPC peripherals from $E000 to $E0FF
877
        --
878
        when "0000" =>
879
          case cpu_addr(7 downto 4) is
880
          --
881
          -- Console Port ACIA $E000 - $E00F
882
          --
883
            when "0000" => -- $E000
884
              cpu_data_in <= acia_data_out;
885
              acia_cs     <= cpu_vma;
886 141 davidgb
 
887 148 davidgb
            --
888
            -- Reserved
889
            -- Floppy Disk Controller port $E010 - $E01F
890
            --
891 141 davidgb
 
892 148 davidgb
            --
893 209 davidgb
            -- Keyboard port $E020 - $E02F
894
            --
895
            when "0010" => -- $E020
896
              cpu_data_in <= keyboard_data_out;
897
              keyboard_cs <= cpu_vma;
898
 
899
            --
900
            -- VDU port $E030 - $E03F
901
            --
902
            when "0011" => -- $E030
903
              cpu_data_in <= vdu_data_out;
904
              vdu_cs      <= cpu_vma;
905
 
906
            --
907 148 davidgb
            -- Reserved SWTPc MP-T Timer $E040 - $E04F
908
            --
909
            when "0100" => -- $E040
910
              cpu_data_in <= (others=> '0');
911 141 davidgb
 
912 148 davidgb
            --
913
            -- Timer $E050 - $E05F
914
            --
915
            when "0101" => -- $E050
916
              cpu_data_in <= timer_data_out;
917
              timer_cs    <= cpu_vma;
918 141 davidgb
 
919 148 davidgb
            --
920
            -- Bus Trap Logic $E060 - $E06F
921
            --
922
            when "0110" => -- $E060
923
              cpu_data_in <= trap_data_out;
924
              trap_cs     <= cpu_vma;
925 141 davidgb
 
926 148 davidgb
            --
927
            -- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
928
            --
929
 
930
            --
931
            -- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
932
            --
933
 
934
            --
935
            -- Remaining 6 slots reserved for non SWTPc Peripherals
936
            --
937
            when others => -- $E0A0 to $E0FF
938
              null;
939
          end case;
940
 
941
        --
942
        -- $E200 to $EFFF reserved for future use
943
        --
944
        when others =>
945 141 davidgb
           null;
946 148 davidgb
      end case;
947 170 davidgb
 
948
    --
949 192 davidgb
    -- Block RAM (32k) $00000 - $07FFF
950 170 davidgb
    --
951 192 davidgb
    elsif dat_addr(7 downto 3) = "00000"   then -- $00000 - $07FFF
952 173 davidgb
      cpu_data_in <= ram1_data_out;
953
      ram1_cs     <= cpu_vma;
954
 
955
    --
956 192 davidgb
    -- Block RAM (16k) $08000 - $0BFFF
957 173 davidgb
    --
958 192 davidgb
    elsif dat_addr(7 downto 2) = "000010"  then -- $08000 - $0BFFF
959 173 davidgb
      cpu_data_in <= ram2_data_out;
960
      ram2_cs     <= cpu_vma;
961 141 davidgb
 
962 148 davidgb
    --
963 192 davidgb
    -- Flex RAM (8k) $0C000 - $0DFFF
964
    --
965
    elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
966
      cpu_data_in <= flex_data_out;
967
      flex_cs     <= cpu_vma;
968
 
969
    --
970 148 davidgb
    -- Everything else is RAM
971
    --
972 141 davidgb
    else
973 173 davidgb
      cpu_data_in <= (others => '0');
974
      ram3_cs      <= cpu_vma;
975 141 davidgb
    end if;
976
 
977 148 davidgb
  end process;
978 141 davidgb
 
979 148 davidgb
  --
980
  -- Interrupts and other bus control signals
981
  --
982 192 davidgb
  interrupts : process( NMI,
983 141 davidgb
                      acia_irq,
984 209 davidgb
                      keyboard_irq,
985 141 davidgb
                      trap_irq,
986
                      timer_irq
987
                      )
988 148 davidgb
  begin
989 209 davidgb
    cpu_irq    <= acia_irq or keyboard_irq;
990 192 davidgb
    cpu_nmi    <= trap_irq or NMI;
991 141 davidgb
    cpu_firq   <= timer_irq;
992
    cpu_halt   <= '0';
993 170 davidgb
    cpu_hold   <= '0'; -- pb_hold or ram_hold;
994 148 davidgb
  end process;
995 192 davidgb
 
996 148 davidgb
  --
997 185 davidgb
  -- Flash 7 segment LEDS
998 148 davidgb
  --
999 185 davidgb
  my_led_flasher: process( clk_i, rst_i, CountL )
1000 148 davidgb
  begin
1001 185 davidgb
    if rst_i = '1' then
1002 194 davidgb
         CountL <= "0000000000000000000000000";
1003 185 davidgb
    elsif rising_edge(clk_i) then
1004
         CountL <= CountL + 1;
1005 141 davidgb
    end if;
1006 192 davidgb
  end process;
1007 141 davidgb
 
1008 192 davidgb
  status_leds : process( rst_i, cpu_reset, cpu_addr, NMI, cpu_data_in, cpu_rw, CountL, sw)
1009 185 davidgb
  begin
1010
    S(7) <= '0';
1011 194 davidgb
    S(6) <= CountL(24);
1012
         S(5) <= cpu_reset;
1013 192 davidgb
         S(4) <= NMI;
1014 185 davidgb
    case sw is
1015 192 davidgb
         when "000" =>
1016 185 davidgb
           S(3 downto 0) <= cpu_addr(3 downto 0);
1017 192 davidgb
    when "001" =>
1018 185 davidgb
           S(3 downto 0) <= cpu_addr(7 downto 4);
1019 192 davidgb
         when "010" =>
1020 185 davidgb
           S(3 downto 0) <= cpu_addr(11 downto 8);
1021 192 davidgb
    when "011" =>
1022 185 davidgb
           S(3 downto 0) <= cpu_addr(15 downto 12);
1023 192 davidgb
    when "100" =>
1024 185 davidgb
           S(3 downto 0) <= cpu_data_in(3 downto 0);
1025 192 davidgb
    when "101" =>
1026 185 davidgb
           S(3 downto 0) <= cpu_data_in(7 downto 4);
1027
    when others => S(3 downto 0) <= (others => '0');
1028
         end case;
1029
  end process;
1030
 
1031 148 davidgb
--  debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
1032 141 davidgb
--                      cpu_halt, cpu_hold,
1033
--                      cpu_firq, cpu_irq, cpu_nmi,
1034
--                      cpu_addr, cpu_data_out, cpu_data_in )
1035 148 davidgb
--  begin
1036
--    cpu_reset_o    <= cpu_reset;
1037
--    cpu_clk_o      <= cpu_clk;
1038
--    cpu_rw_o       <= cpu_rw;
1039
--    cpu_vma_o      <= cpu_vma;
1040
--    cpu_halt_o     <= cpu_halt;
1041
--    cpu_hold_o     <= cpu_hold;
1042
--    cpu_firq_o     <= cpu_firq;
1043
--    cpu_irq_o      <= cpu_irq;
1044
--    cpu_nmi_o      <= cpu_nmi;
1045
--    cpu_addr_o     <= cpu_addr;
1046
--    cpu_data_out_o <= cpu_data_out;
1047
--    cpu_data_in_o  <= cpu_data_in;
1048
--  end process;
1049 141 davidgb
 
1050
end rtl; --===================== End of architecture =======================--
1051
 

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