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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_Atlys/] [system09.vhd] - Blame information for rev 217

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1 141 davidgb
--===========================================================================----
2
--
3
--  S Y N T H E Z I A B L E    System09 - SOC.
4
--
5
--  www.OpenCores.Org - February 2007
6
--  This core adheres to the GNU public license  
7
--
8
-- File name      : System09_Xess_XSA-3S1000.vhd
9
--
10
-- Purpose        : Top level file for 6809 compatible system on a chip
11
--                  Designed with Xilinx XC3S1000 Spartan 3 FPGA.
12
--                  Implemented With XESS XSA-3S1000 FPGA board.
13
--                  *** Note ***
14
--                  This configuration can run Flex9 however it only has
15
--                  32k bytes of user memory and the VDU is monochrome
16
--                  The design needs to be updated to use the SDRAM on 
17
--                  the XSA-3S1000 board.
18
--                  This configuration also lacks a DAT so cannot use
19
--                  the RAM Disk features of SYS09BUG.
20
--
21
-- Dependencies   : ieee.Std_Logic_1164
22
--                  ieee.std_logic_unsigned
23
--                  ieee.std_logic_arith
24
--                  ieee.numeric_std
25
--                  unisim.vcomponents
26
--
27
-- Uses           : mon_rom    (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
28
--                  cpu09      (cpu09.vhd)          CPU core
29
--                  ACIA_6850  (acia6850.vhd)      ACIA / UART
30
--                  ACIA_Clock (ACIA_Clock.vhd)      ACIA clock.
31
--                  timer      (timer.vhd)            Interrupt timer
32
--                  trap       (trap.vhd)             Bus condition trap logic
33
--                  flex_ram   (flex9_ram8k_b16.vhd)  Flex operating system
34
--                  ram_32K    (ram32k_b16.vhd)       32 KBytes of Block RAM
35
--                  
36
-- 
37
-- Author         : John E. Kent      
38
--                  dilbert57@opencores.org      
39
--
40
-- Memory Map     :
41
--
42
-- $0000 - User program RAM (32K Bytes)
43
-- $C000 - Flex Operating System memory (8K Bytes)
44
-- $E000 - ACIA (SWTPc)
45
-- $E010 - Reserved for FD1771 FDC (SWTPc)
46
-- $E050 - Timer
47
-- $E060 - Bus trap
48
-- $E070 - Reserced for Parallel I/O (B5-X300)
49
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
50
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
51
-- $F000 - Sys09Bug monitor Program (4K Bytes)
52
--
53
--===========================================================================----
54
--
55
-- Revision History:
56
--===========================================================================--
57
-- Version 0.1 - 20 March 2003
58
-- Version 0.2 - 30 March 2003
59
-- Version 0.3 - 29 April 2003
60
-- Version 0.4 - 29 June 2003
61
--
62
-- Version 0.5 - 19 July 2003
63
-- prints out "Hello World"
64
--
65
-- Version 0.6 - 5 September 2003
66
-- Runs SBUG
67
--
68
-- Version 1.0- 6 Sep 2003 - John Kent
69
-- Inverted SysClk
70
-- Initial release to Open Cores
71
--
72
-- Version 1.1 - 17 Jan 2004 - John Kent
73
-- Updated miniUart.
74
--
75
-- Version 1.2 - 25 Jan 2004 - John Kent
76
-- removed signals "test_alu" and "test_cc" 
77
-- Trap hardware re-instated.
78
--
79
-- Version 1.3 - 11 Feb 2004 - John Kent
80
-- Designed forked off to produce System09_VDU
81
-- Added VDU component
82
-- VDU runs at 25MHz and divides the clock by 2 for the CPU
83
-- UART Runs at 57.6 Kbps
84
--
85
-- Version 2.0 - 2 September 2004 - John Kent
86
-- ported to Digilent Xilinx Spartan3 starter board
87
-- removed Compact Flash and Trap Logic.
88
-- Replaced SBUG with KBug9s
89
--
90
-- Version 3.0 - 29th August 2006 - John Kent
91
-- Adapted to XSA-3S1000 board.
92
-- Removed DAT and miniUART.
93
-- Used 32KBytes of Block RAM.
94
--
95
-- Version 3.1 - 15th January 2007 - John Kent
96
-- Modified vdu8 interface
97
-- Added a clock divider
98
--
99
-- Version 3.2 - 25th February 2007 - John Kent
100
-- reinstated ACIA_6850 and ACIA_Clock
101
-- Updated VDU8 & Keyboard with generic parameters
102
-- Defined Constants for clock speed calculations
103
--
104
-- Version 3.3 - 1st July 2007 - John Kent
105
-- Made VDU mono to save on one RAMB16
106
-- Used distributed memory for Key Map ROM to save one RAMB16
107
-- Added Flex RAM at $C000 to $DFFF using 4 spare RAMB16s
108
-- Added timer and trap logic
109
-- Added IDE Interface for Compact Flash
110
-- Replaced KBug9s and stack with Sys09Bug.
111
--
112
-- Version 4.0 - 1st February 2008 - John kent
113
-- Replaced Block RAM with SDRAM Interface
114
-- Modified Hold timing for SDRAM
115
-- Added CF and Ethernet interface 
116
-- via the 16 bit peripheral bus at $E100
117
--
118
--===========================================================================--
119
library ieee;
120
   use ieee.std_logic_1164.all;
121
   use IEEE.STD_LOGIC_ARITH.ALL;
122
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
123
   use ieee.numeric_std.all;
124
library work;
125
   use work.common.all;
126
library unisim;
127 162 davidgb
   use unisim.vcomponents.all;
128 141 davidgb
 
129
entity system09 is
130
  port(
131
    CLKA         : in  Std_Logic;  -- 100MHz Clock input
132 192 davidgb
    RESET        : in  Std_logic;  -- Master Reset input (active high) -- red "RESET" PB
133
    NMI          : in  Std_logic;  -- Non Maskable Interrupt input (active high) -- Center PB
134 141 davidgb
 
135 209 davidgb
    -- PS/2 Keyboard
136
    ps2_clk      : inout Std_logic;
137
    ps2_dat      : inout Std_Logic;
138
 
139
    -- HDMI output
140 212 davidgb
    TMDSp_clock  : out std_logic;
141
    TMDSn_clock  : out std_logic;
142
    TMDSp        : out std_logic_vector(2 downto 0);
143
    TMDSn        : out std_logic_vector(2 downto 0);
144 209 davidgb
 
145 212 davidgb
    -- RS232 Port - via Atlys UART over USB (no h/w/ handshake available)
146 195 davidgb
--  RS232_CTS    : in  Std_Logic;
147
--  RS232_RTS    : out Std_Logic;
148 185 davidgb
    RS232_RXD    : in  Std_Logic;
149
    RS232_TXD    : out Std_Logic;
150 141 davidgb
 
151 186 davidgb
    -- slide switches
152 209 davidgb
    sw           : in std_logic_vector(2 downto 0);
153 186 davidgb
    -- Status 7 segment LED
154 192 davidgb
    S            : out std_logic_vector(7 downto 0)
155 185 davidgb
 
156 141 davidgb
-- CPU Debug Interface signals
157
--    cpu_reset_o     : out Std_Logic;
158
--    cpu_clk_o       : out Std_Logic;
159
--    cpu_rw_o        : out std_logic;
160
--    cpu_vma_o       : out std_logic;
161
--    cpu_halt_o      : out std_logic;
162
--    cpu_hold_o      : out std_logic;
163
--    cpu_firq_o      : out std_logic;
164
--    cpu_irq_o       : out std_logic;
165
--    cpu_nmi_o       : out std_logic;
166
--    cpu_addr_o      : out std_logic_vector(15 downto 0);
167
--    cpu_data_in_o   : out std_logic_vector(7 downto 0);
168
--    cpu_data_out_o  : out std_logic_vector(7 downto 0);
169
 
170 148 davidgb
  );
171 141 davidgb
end system09;
172
 
173
-------------------------------------------------------------------------------
174
-- Architecture for System09
175
-------------------------------------------------------------------------------
176
architecture rtl of system09 is
177
 
178
  -----------------------------------------------------------------------------
179
  -- constants
180
  -----------------------------------------------------------------------------
181 186 davidgb
  constant CLOCK_MODE           : natural := 0; -- 0 means normal, 1 means single-step
182
 
183 192 davidgb
  constant SYS_CLK_FREQ         : natural := 100_000_000;  -- FPGA System Clock (in Hz)
184 186 davidgb
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
185 141 davidgb
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
186 209 davidgb
  constant VGA_CLK_FREQ         : natural := 25_000_000;  -- VGA Pixel Clock
187
  constant VGA_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
188 141 davidgb
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
189
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
190
 
191
  -----------------------------------------------------------------------------
192
  -- Signals
193 174 davidgb
  -----------------------------------------------------------------------------
194 192 davidgb
 
195 141 davidgb
  -- BOOT ROM
196
  signal rom_cs         : Std_logic;
197
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
198
 
199
  -- Flex Memory & Monitor Stack
200
  signal flex_cs        : Std_logic;
201
  signal flex_data_out  : Std_Logic_Vector(7 downto 0);
202
 
203
  -- ACIA/UART Interface signals
204
  signal acia_data_out  : Std_Logic_Vector(7 downto 0);
205
  signal acia_cs        : Std_Logic;
206
  signal acia_irq       : Std_Logic;
207
  signal acia_clk       : Std_Logic;
208 192 davidgb
  signal RXD            : Std_Logic;
209
  signal TXD            : Std_Logic;
210 141 davidgb
  signal DCD_n          : Std_Logic;
211
  signal RTS_n          : Std_Logic;
212
  signal CTS_n          : Std_Logic;
213 209 davidgb
 
214
  -- keyboard port
215
  signal keyboard_data_out : std_logic_vector(7 downto 0);
216
  signal keyboard_cs       : std_logic;
217
  signal keyboard_irq      : std_logic;
218
 
219 141 davidgb
  -- RAM
220 173 davidgb
  signal ram1_cs         : std_logic;
221
  signal ram1_data_out   : std_logic_vector(7 downto 0);
222
  signal ram2_cs         : std_logic;
223
  signal ram2_data_out   : std_logic_vector(7 downto 0);
224
  signal ram3_cs         : std_logic;
225 141 davidgb
 
226
  -- CPU Interface signals
227
  signal cpu_reset      : Std_Logic;
228
  signal cpu_clk        : Std_Logic;
229
  signal cpu_rw         : std_logic;
230
  signal cpu_vma        : std_logic;
231
  signal cpu_halt       : std_logic;
232
  signal cpu_hold       : std_logic;
233
  signal cpu_firq       : std_logic;
234
  signal cpu_irq        : std_logic;
235
  signal cpu_nmi        : std_logic;
236
  signal cpu_addr       : std_logic_vector(15 downto 0);
237
  signal cpu_data_in    : std_logic_vector(7 downto 0);
238
  signal cpu_data_out   : std_logic_vector(7 downto 0);
239
 
240
  -- Dynamic Address Translation
241
  signal dat_cs       : std_logic;
242
  signal dat_addr     : std_logic_vector(7 downto 0);
243
 
244 209 davidgb
  -- Video Display Unit
245
  signal vdu_clk        : std_logic;
246
  signal vdu_cs         : std_logic;
247 212 davidgb
  signal vdu_data_out   : std_logic_vector(7 downto 0);
248 209 davidgb
 
249 141 davidgb
  -- timer
250
  signal timer_data_out : std_logic_vector(7 downto 0);
251
  signal timer_cs       : std_logic;
252
  signal timer_irq      : std_logic;
253
 
254
  -- trap
255
  signal trap_cs        : std_logic;
256
  signal trap_data_out  : std_logic_vector(7 downto 0);
257
  signal trap_irq       : std_logic;
258
 
259
  signal rst_i         : std_logic;     -- internal reset signal
260 186 davidgb
  signal clk_i         : std_logic;     -- internal master clock signal
261 148 davidgb
 
262 194 davidgb
  signal CountL        : std_logic_vector(24 downto 0);
263 141 davidgb
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
264
  signal Clk25         : std_logic;
265
 
266
-----------------------------------------------------------------
267
--
268
-- CPU09 CPU core
269
--
270
-----------------------------------------------------------------
271
 
272
component cpu09
273
  port (
274
    clk:      in  std_logic;
275
    rst:      in  std_logic;
276
    vma:      out std_logic;
277
    addr:     out std_logic_vector(15 downto 0);
278
    rw:       out std_logic;     -- Asynchronous memory interface
279
    data_out: out std_logic_vector(7 downto 0);
280
    data_in:  in  std_logic_vector(7 downto 0);
281
    irq:      in  std_logic;
282
    firq:     in  std_logic;
283
    nmi:      in  std_logic;
284
    halt:     in  std_logic;
285
    hold:     in  std_logic
286
  );
287
end component;
288
 
289
----------------------------------------
290
--
291
-- 4K Block RAM Monitor ROM
292 148 davidgb
-- $F000 - $FFFF
293 141 davidgb
--
294
----------------------------------------
295 148 davidgb
 
296 141 davidgb
component mon_rom
297 148 davidgb
  Port (
298
    clk   : in  std_logic;
299
    rst   : in  std_logic;
300
    cs    : in  std_logic;
301
    rw    : in  std_logic;
302
    addr  : in  std_logic_vector (11 downto 0);
303
    data_out : out std_logic_vector (7 downto 0);
304
    data_in : in  std_logic_vector (7 downto 0)
305
  );
306 141 davidgb
end component;
307
 
308
----------------------------------------
309
--
310
-- 8KBytes Block RAM for FLEX9
311
-- $C000 - $DFFF
312
--
313
----------------------------------------
314 148 davidgb
 
315 141 davidgb
component flex_ram
316
  Port (
317
    clk      : in  std_logic;
318
    rst      : in  std_logic;
319
    cs       : in  std_logic;
320
    rw       : in  std_logic;
321
    addr     : in  std_logic_vector (12 downto 0);
322
    data_out    : out std_logic_vector (7 downto 0);
323
    data_in    : in  std_logic_vector (7 downto 0)
324 148 davidgb
  );
325 141 davidgb
end component;
326 170 davidgb
 
327
----------------------------------------
328
--
329
-- 32KBytes Block RAM 0000
330
-- $0000 - $7FFF
331
--
332
----------------------------------------
333 141 davidgb
 
334 170 davidgb
component ram_32k
335
  Port (
336
    clk      : in  std_logic;
337
    rst      : in  std_logic;
338
    cs       : in  std_logic;
339
    rw       : in  std_logic;
340
    addr     : in  std_logic_vector (14 downto 0);
341
    data_out    : out std_logic_vector (7 downto 0);
342
    data_in    : in  std_logic_vector (7 downto 0)
343
  );
344
end component;
345
 
346 173 davidgb
 
347
----------------------------------------
348
--
349
-- 16KBytes Block RAM 8000
350
-- $8000 - $BFFF
351
--
352
----------------------------------------
353 170 davidgb
 
354 173 davidgb
component ram_16k
355
  Port (
356
    clk      : in  std_logic;
357
    rst      : in  std_logic;
358
    cs       : in  std_logic;
359
    rw       : in  std_logic;
360
    addr     : in  std_logic_vector (13 downto 0);
361
    data_out    : out std_logic_vector (7 downto 0);
362
    data_in    : in  std_logic_vector (7 downto 0)
363
  );
364
end component;
365
 
366 141 davidgb
-----------------------------------------------------------------
367
--
368
-- 6850 Compatible ACIA / UART
369
--
370
-----------------------------------------------------------------
371
 
372
component acia6850
373
  port (
374 148 davidgb
    clk      : in  Std_Logic;  -- System Clock
375
    rst      : in  Std_Logic;  -- Reset input (active high)
376
    cs       : in  Std_Logic;  -- miniUART Chip Select
377
    rw       : in  Std_Logic;  -- Read / Not Write
378
    addr     : in  Std_Logic;  -- Register Select
379
    data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
380
    data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
381
    irq      : out Std_Logic;  -- Interrupt
382
    RxC      : in  Std_Logic;  -- Receive Baud Clock
383
    TxC      : in  Std_Logic;  -- Transmit Baud Clock
384
    RxD      : in  Std_Logic;  -- Receive Data
385
    TxD      : out Std_Logic;  -- Transmit Data
386
    DCD_n    : in  Std_Logic;  -- Data Carrier Detect
387
    CTS_n    : in  Std_Logic;  -- Clear To Send
388
    RTS_n    : out Std_Logic   -- Request To send
389
  );
390 141 davidgb
end component;
391
 
392
-----------------------------------------------------------------
393
--
394
-- ACIA Clock divider
395
--
396
-----------------------------------------------------------------
397
 
398
component ACIA_Clock
399
  generic (
400 148 davidgb
    SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
401
    ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
402 141 davidgb
  );
403
  port (
404 148 davidgb
    clk      : in  Std_Logic;  -- System Clock Input
405
    ACIA_clk : out Std_logic   -- ACIA Clock output
406 141 davidgb
  );
407
end component;
408
 
409
----------------------------------------
410
--
411 209 davidgb
-- PS/2 Keyboard
412
--
413
----------------------------------------
414
 
415
component keyboard
416
  generic(
417
    KBD_CLK_FREQ : integer := CPU_CLK_FREQ
418
  );
419
  port(
420
    clk             : in    std_logic;
421
    rst             : in    std_logic;
422
    cs              : in    std_logic;
423
    rw              : in    std_logic;
424
    addr            : in    std_logic;
425
    data_in         : in    std_logic_vector(7 downto 0);
426
    data_out        : out   std_logic_vector(7 downto 0);
427
    irq             : out   std_logic;
428
    kbd_clk         : inout std_logic;
429
    kbd_data        : inout std_logic
430
  );
431
end component;
432
 
433
----------------------------------------
434
--
435
-- Video Display Unit.
436
--
437
----------------------------------------
438
 
439 212 davidgb
component vdu8_hdmi
440 209 davidgb
  generic(
441
    VDU_CLK_FREQ           : integer := CPU_CLK_FREQ; -- HZ
442
    VGA_CLK_FREQ           : integer := VGA_CLK_FREQ; -- HZ
443
    VGA_HOR_CHARS          : integer := 80; -- CHARACTERS
444
    VGA_VER_CHARS          : integer := 25; -- CHARACTERS
445
    VGA_PIX_PER_CHAR       : integer := 8;  -- PIXELS
446
    VGA_LIN_PER_CHAR       : integer := 16; -- LINES
447
    VGA_HOR_BACK_PORCH     : integer := 40; -- PIXELS
448
    VGA_HOR_SYNC           : integer := 96; -- PIXELS
449
    VGA_HOR_FRONT_PORCH    : integer := 24; -- PIXELS
450
    VGA_VER_BACK_PORCH     : integer := 13; -- LINES
451
    VGA_VER_SYNC           : integer := 2;  -- LINES
452
    VGA_VER_FRONT_PORCH    : integer := 35  -- LINES
453
  );
454
  port(
455
    -- control register interface
456
    vdu_clk      : in  std_logic;  -- CPU Clock - 25MHz
457
    vdu_rst      : in  std_logic;
458
    vdu_cs       : in  std_logic;
459
    vdu_rw       : in  std_logic;
460
    vdu_addr     : in  std_logic_vector(2 downto 0);
461
    vdu_data_in  : in  std_logic_vector(7 downto 0);
462 212 davidgb
    vdu_data_out : out std_logic_vector(7 downto 0);
463
    -- HDMI TMDS outputs
464
         hdmi_clk     : in std_logic;
465
    TMDSp_clock  : out std_logic;
466
    TMDSn_clock  : out std_logic;
467
    TMDSp        : out std_logic_vector(2 downto 0);
468
    TMDSn        : out std_logic_vector(2 downto 0)
469 209 davidgb
  );
470
end component;
471
 
472
----------------------------------------
473
--
474 141 davidgb
-- Timer module
475
--
476
----------------------------------------
477
 
478
component timer
479
  port (
480 148 davidgb
    clk       : in std_logic;
481
    rst       : in std_logic;
482
    cs        : in std_logic;
483
    rw        : in std_logic;
484
    addr      : in std_logic;
485
    data_in   : in std_logic_vector(7 downto 0);
486
    data_out  : out std_logic_vector(7 downto 0);
487
    irq       : out std_logic
488
  );
489 141 davidgb
end component;
490
 
491
------------------------------------------------------------
492
--
493
-- Bus Trap logic
494
--
495
------------------------------------------------------------
496
 
497
component trap
498 148 davidgb
  port (
499 141 davidgb
    clk        : in  std_logic;
500
    rst        : in  std_logic;
501
    cs         : in  std_logic;
502
    rw         : in  std_logic;
503
    vma        : in  std_logic;
504
    addr       : in  std_logic_vector(15 downto 0);
505
    data_in    : in  std_logic_vector(7 downto 0);
506
    data_out   : out std_logic_vector(7 downto 0);
507
    irq        : out std_logic
508
  );
509
end component;
510
 
511
----------------------------------------
512
--
513
-- Dynamic Address Translation Registers
514
--
515
----------------------------------------
516 148 davidgb
 
517 141 davidgb
component dat_ram
518
  port (
519
    clk      : in  std_logic;
520
    rst      : in  std_logic;
521
    cs       : in  std_logic;
522
    rw       : in  std_logic;
523
    addr_lo  : in  std_logic_vector(3 downto 0);
524
    addr_hi  : in  std_logic_vector(3 downto 0);
525
    data_in  : in  std_logic_vector(7 downto 0);
526
    data_out : out std_logic_vector(7 downto 0)
527
  );
528
end component;
529 185 davidgb
 
530 141 davidgb
--
531
-- Clock buffer
532
--
533 148 davidgb
 
534 141 davidgb
component BUFG
535
   Port (
536
     i: in std_logic;
537
     o: out std_logic
538
  );
539
end component;
540
 
541 185 davidgb
begin
542
 
543 186 davidgb
  --
544
  -- Generate CPU & Pixel Clock from Memory Clock
545
  --
546 192 davidgb
 
547
  my_prescaler : process( clk_i, clk_count )
548
  begin
549
    if rising_edge( clk_i ) then
550
      if clk_count = 0 then
551
        clk_count <= CPU_CLK_DIV-1;
552
      else
553
        clk_count <= clk_count - 1;
554 186 davidgb
      end if;
555 192 davidgb
      if clk_count = 0 then
556
         clk25 <= '0';
557
      elsif clk_count = (CPU_CLK_DIV/2) then
558
         clk25 <= '1';
559
      end if;
560
    end if;
561
  end process;
562 186 davidgb
 
563
  --
564
  -- Reset button and reset timer
565
  --
566 192 davidgb
  my_switch_assignments : process( rst_i, RESET)
567 186 davidgb
  begin
568 194 davidgb
    rst_i <= not RESET;
569 186 davidgb
    cpu_reset <= rst_i;
570
  end process;
571 185 davidgb
 
572 186 davidgb
  clk_i <= CLKA;
573
 
574 141 davidgb
  -----------------------------------------------------------------------------
575
  -- Instantiation of internal components
576
  -----------------------------------------------------------------------------
577
 
578 148 davidgb
  my_cpu : cpu09
579
    port map (
580
      clk       => cpu_clk,
581
      rst       => cpu_reset,
582
      vma       => cpu_vma,
583
      addr      => cpu_addr(15 downto 0),
584
      rw        => cpu_rw,
585
      data_out  => cpu_data_out,
586
      data_in   => cpu_data_in,
587
      irq       => cpu_irq,
588
      firq      => cpu_firq,
589
      nmi       => cpu_nmi,
590
      halt      => cpu_halt,
591
      hold      => cpu_hold
592
    );
593 141 davidgb
 
594 148 davidgb
  my_rom : mon_rom
595
    port map (
596 192 davidgb
      clk       => cpu_clk,
597
      rst       => cpu_reset,
598
      cs        => rom_cs,
599
      rw        => '1',
600
      addr      => cpu_addr(11 downto 0),
601
      data_in   => cpu_data_out,
602
      data_out  => rom_data_out
603 141 davidgb
    );
604
 
605 148 davidgb
  my_flex : flex_ram
606
    port map (
607
      clk       => cpu_clk,
608
      rst       => cpu_reset,
609
      cs        => flex_cs,
610
      rw        => cpu_rw,
611
      addr      => cpu_addr(12 downto 0),
612 192 davidgb
      data_out  => flex_data_out,
613
      data_in   => cpu_data_out
614 170 davidgb
    );
615
 
616
  my_32k : ram_32k
617
    port map (
618
      clk       => cpu_clk,
619
      rst       => cpu_reset,
620 173 davidgb
      cs        => ram1_cs,
621 170 davidgb
      rw        => cpu_rw,
622
      addr      => cpu_addr(14 downto 0),
623 192 davidgb
      data_out  => ram1_data_out,
624
      data_in   => cpu_data_out
625 170 davidgb
    );
626 173 davidgb
 
627
  my_16k : ram_16k
628
    port map (
629
      clk       => cpu_clk,
630
      rst       => cpu_reset,
631
      cs        => ram2_cs,
632
      rw        => cpu_rw,
633
      addr      => cpu_addr(13 downto 0),
634 192 davidgb
      data_out  => ram2_data_out,
635
      data_in   => cpu_data_out
636 173 davidgb
    );
637
 
638 148 davidgb
  my_acia  : acia6850
639
    port map (
640
      clk       => cpu_clk,
641
      rst       => cpu_reset,
642
      cs        => acia_cs,
643
      rw        => cpu_rw,
644
      addr      => cpu_addr(0),
645
      data_in   => cpu_data_out,
646
      data_out  => acia_data_out,
647
      irq       => acia_irq,
648
      RxC       => acia_clk,
649
      TxC       => acia_clk,
650 192 davidgb
      RxD       => RXD,
651
      TxD       => TXD,
652
      DCD_n     => DCD_n,
653
      CTS_n     => CTS_n,
654
      RTS_n     => RTS_n
655
    );
656
 
657
  --
658
  -- RS232 signals:
659
  --
660 195 davidgb
  my_acia_assignments : process( RS232_RXD, -- RS232_CTS,
661
                                 TXD, RTS_n )
662 192 davidgb
  begin
663
    RXD       <= RS232_RXD;
664 195 davidgb
    CTS_n     <= '0'; -- RS232_CTS;
665 192 davidgb
    DCD_n     <= '0';
666
    RS232_TXD <= TXD;
667 195 davidgb
--  RS232_RTS <= not RTS_n;
668 192 davidgb
  end process;
669 186 davidgb
 
670 148 davidgb
  my_ACIA_Clock : ACIA_Clock
671
    generic map(
672 185 davidgb
      SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
673 148 davidgb
      ACIA_CLK_FREQ => ACIA_CLK_FREQ
674
    )
675
    port map(
676 192 davidgb
      clk        => clk_i,
677 148 davidgb
      acia_clk   => acia_clk
678
    );
679 141 davidgb
 
680 148 davidgb
  ----------------------------------------
681
  --
682 209 davidgb
  -- PS/2 Keyboard Interface
683
  --
684
  ----------------------------------------
685
  my_keyboard : keyboard
686
    generic map (
687
      KBD_CLK_FREQ => CPU_CLK_FREQ
688
    )
689
    port map(
690
      clk          => cpu_clk,
691
      rst          => cpu_reset,
692
      cs           => keyboard_cs,
693
      rw           => cpu_rw,
694
      addr         => cpu_addr(0),
695
      data_in      => cpu_data_out(7 downto 0),
696
      data_out     => keyboard_data_out(7 downto 0),
697
      irq          => keyboard_irq,
698
      kbd_clk      => ps2_clk,
699
      kbd_data     => ps2_dat
700
    );
701
 
702
  ----------------------------------------
703
  --
704
  -- Video Display Unit instantiation
705
  --
706
  ----------------------------------------
707
  vdu_clk_buffer : BUFG
708
    port map(
709
      i => Clk25,
710
      o => vdu_clk
711
    );
712
 
713 212 davidgb
  my_vdu : vdu8_hdmi
714 209 davidgb
    generic map(
715
      VDU_CLK_FREQ           => CPU_CLK_FREQ, -- HZ
716
      VGA_CLK_FREQ           => VGA_CLK_FREQ, -- HZ
717
      VGA_HOR_CHARS          => 80, -- CHARACTERS
718
      VGA_VER_CHARS          => 25, -- CHARACTERS
719
      VGA_PIX_PER_CHAR       => 8,  -- PIXELS
720
      VGA_LIN_PER_CHAR       => 16, -- LINES
721
      VGA_HOR_BACK_PORCH     => 40, -- PIXELS
722
      VGA_HOR_SYNC           => 96, -- PIXELS
723
      VGA_HOR_FRONT_PORCH    => 24, -- PIXELS
724
      VGA_VER_BACK_PORCH     => 13, -- LINES
725
      VGA_VER_SYNC           => 2,  -- LINES
726
      VGA_VER_FRONT_PORCH    => 35  -- LINES
727
    )
728
    port map(
729
      -- Control Registers
730
      vdu_clk       => cpu_clk,               -- 12.5 MHz System Clock in
731
      vdu_rst       => cpu_reset,
732
      vdu_cs        => vdu_cs,
733
      vdu_rw        => cpu_rw,
734
      vdu_addr      => cpu_addr(2 downto 0),
735
      vdu_data_in   => cpu_data_out,
736 212 davidgb
      vdu_data_out  => vdu_data_out,
737
                -- HDMI port connections
738
                hdmi_clk    => Clk25,
739
                TMDSp       => TMDSp,
740
                TMDSn       => TMDSn,
741
                TMDSp_clock => TMDSp_clock,
742
                TMDSn_clock => TMDSn_clock
743 209 davidgb
   );
744
 
745
 
746
  ----------------------------------------
747
  --
748 148 davidgb
  -- Timer Module
749
  --
750
  ----------------------------------------
751
  my_timer  : timer
752
    port map (
753
      clk       => cpu_clk,
754
      rst       => cpu_reset,
755
      cs        => timer_cs,
756
      rw        => cpu_rw,
757
      addr      => cpu_addr(0),
758
      data_in   => cpu_data_out,
759
      data_out  => timer_data_out,
760
      irq       => timer_irq
761
    );
762 141 davidgb
 
763 148 davidgb
  ----------------------------------------
764
  --
765
  -- Bus Trap Interrupt logic
766
  --
767
  ----------------------------------------
768
  my_trap : trap
769
    port map (
770
      clk        => cpu_clk,
771
      rst        => cpu_reset,
772
      cs         => trap_cs,
773
      rw         => cpu_rw,
774
      vma        => cpu_vma,
775
      addr       => cpu_addr,
776
      data_in    => cpu_data_out,
777
      data_out   => trap_data_out,
778
      irq        => trap_irq
779 141 davidgb
    );
780
 
781 148 davidgb
  my_dat : dat_ram
782
    port map (
783
      clk       => cpu_clk,
784
      rst       => cpu_reset,
785
      cs        => dat_cs,
786
      rw        => cpu_rw,
787
      addr_hi   => cpu_addr(15 downto 12),
788
      addr_lo   => cpu_addr(3 downto 0),
789
      data_in   => cpu_data_out,
790
      data_out  => dat_addr(7 downto 0)
791 141 davidgb
    );
792
 
793 148 davidgb
  cpu_clk_buffer : BUFG
794 141 davidgb
    port map(
795 148 davidgb
      i => Clk25,
796
      o => cpu_clk
797 141 davidgb
    );
798 162 davidgb
 
799 148 davidgb
  ----------------------------------------------------------------------
800
  --
801
  -- Process to decode memory map
802
  --
803
  ----------------------------------------------------------------------
804 141 davidgb
 
805 148 davidgb
  mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
806 141 davidgb
                     dat_addr,
807
                     rom_data_out,
808
                     flex_data_out,
809
                     acia_data_out,
810 209 davidgb
                     keyboard_data_out,
811
                     vdu_data_out,
812 141 davidgb
                     timer_data_out,
813
                     trap_data_out,
814 173 davidgb
                     ram1_data_out, ram2_data_out
815 141 davidgb
                     )
816 148 davidgb
  begin
817
    cpu_data_in <= (others=>'0');
818
    dat_cs      <= '0';
819
    rom_cs      <= '0';
820
    flex_cs     <= '0';
821
    acia_cs     <= '0';
822 209 davidgb
    keyboard_cs <= '0';
823
    vdu_cs      <= '0';
824 148 davidgb
    timer_cs    <= '0';
825
    trap_cs     <= '0';
826 192 davidgb
    ram1_cs     <= '0';
827
    ram2_cs     <= '0';
828
    ram3_cs     <= '0';
829 173 davidgb
 
830 148 davidgb
    if cpu_addr( 15 downto 8 ) = "11111111" then  -- $FFxx
831
      cpu_data_in <= rom_data_out;
832
      dat_cs      <= cpu_vma;              -- write DAT
833
      rom_cs      <= cpu_vma;              -- read  ROM
834 141 davidgb
 
835 148 davidgb
    --
836
    -- Sys09Bug Monitor ROM $F000 - $FFFF
837
    --
838
    elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
839
      cpu_data_in <= rom_data_out;
840
      rom_cs      <= cpu_vma;
841 141 davidgb
 
842 148 davidgb
    --
843
    -- IO Devices $E000 - $E7FF
844
    --
845
    elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
846
      case cpu_addr(11 downto 8) is
847
        --
848
        -- SWTPC peripherals from $E000 to $E0FF
849
        --
850
        when "0000" =>
851
          case cpu_addr(7 downto 4) is
852
          --
853
          -- Console Port ACIA $E000 - $E00F
854
          --
855
            when "0000" => -- $E000
856
              cpu_data_in <= acia_data_out;
857
              acia_cs     <= cpu_vma;
858 141 davidgb
 
859 148 davidgb
            --
860
            -- Reserved
861
            -- Floppy Disk Controller port $E010 - $E01F
862
            --
863 141 davidgb
 
864 148 davidgb
            --
865 209 davidgb
            -- Keyboard port $E020 - $E02F
866
            --
867
            when "0010" => -- $E020
868
              cpu_data_in <= keyboard_data_out;
869
              keyboard_cs <= cpu_vma;
870
 
871
            --
872
            -- VDU port $E030 - $E03F
873
            --
874
            when "0011" => -- $E030
875
              cpu_data_in <= vdu_data_out;
876
              vdu_cs      <= cpu_vma;
877
 
878
            --
879 148 davidgb
            -- Reserved SWTPc MP-T Timer $E040 - $E04F
880
            --
881
            when "0100" => -- $E040
882
              cpu_data_in <= (others=> '0');
883 141 davidgb
 
884 148 davidgb
            --
885
            -- Timer $E050 - $E05F
886
            --
887
            when "0101" => -- $E050
888
              cpu_data_in <= timer_data_out;
889
              timer_cs    <= cpu_vma;
890 141 davidgb
 
891 148 davidgb
            --
892
            -- Bus Trap Logic $E060 - $E06F
893
            --
894
            when "0110" => -- $E060
895
              cpu_data_in <= trap_data_out;
896
              trap_cs     <= cpu_vma;
897 141 davidgb
 
898 148 davidgb
            --
899
            -- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
900
            --
901
 
902
            --
903
            -- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
904
            --
905
 
906
            --
907
            -- Remaining 6 slots reserved for non SWTPc Peripherals
908
            --
909
            when others => -- $E0A0 to $E0FF
910
              null;
911
          end case;
912
 
913
        --
914
        -- $E200 to $EFFF reserved for future use
915
        --
916
        when others =>
917 141 davidgb
           null;
918 148 davidgb
      end case;
919 170 davidgb
 
920
    --
921 192 davidgb
    -- Block RAM (32k) $00000 - $07FFF
922 170 davidgb
    --
923 192 davidgb
    elsif dat_addr(7 downto 3) = "00000"   then -- $00000 - $07FFF
924 173 davidgb
      cpu_data_in <= ram1_data_out;
925
      ram1_cs     <= cpu_vma;
926
 
927
    --
928 192 davidgb
    -- Block RAM (16k) $08000 - $0BFFF
929 173 davidgb
    --
930 192 davidgb
    elsif dat_addr(7 downto 2) = "000010"  then -- $08000 - $0BFFF
931 173 davidgb
      cpu_data_in <= ram2_data_out;
932
      ram2_cs     <= cpu_vma;
933 141 davidgb
 
934 148 davidgb
    --
935 192 davidgb
    -- Flex RAM (8k) $0C000 - $0DFFF
936
    --
937
    elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
938
      cpu_data_in <= flex_data_out;
939
      flex_cs     <= cpu_vma;
940
 
941
    --
942 148 davidgb
    -- Everything else is RAM
943
    --
944 141 davidgb
    else
945 173 davidgb
      cpu_data_in <= (others => '0');
946
      ram3_cs      <= cpu_vma;
947 141 davidgb
    end if;
948
 
949 148 davidgb
  end process;
950 141 davidgb
 
951 148 davidgb
  --
952
  -- Interrupts and other bus control signals
953
  --
954 192 davidgb
  interrupts : process( NMI,
955 141 davidgb
                      acia_irq,
956 209 davidgb
                      keyboard_irq,
957 141 davidgb
                      trap_irq,
958
                      timer_irq
959
                      )
960 148 davidgb
  begin
961 209 davidgb
    cpu_irq    <= acia_irq or keyboard_irq;
962 192 davidgb
    cpu_nmi    <= trap_irq or NMI;
963 141 davidgb
    cpu_firq   <= timer_irq;
964
    cpu_halt   <= '0';
965 170 davidgb
    cpu_hold   <= '0'; -- pb_hold or ram_hold;
966 148 davidgb
  end process;
967 192 davidgb
 
968 148 davidgb
  --
969 185 davidgb
  -- Flash 7 segment LEDS
970 148 davidgb
  --
971 185 davidgb
  my_led_flasher: process( clk_i, rst_i, CountL )
972 148 davidgb
  begin
973 185 davidgb
    if rst_i = '1' then
974 194 davidgb
         CountL <= "0000000000000000000000000";
975 185 davidgb
    elsif rising_edge(clk_i) then
976
         CountL <= CountL + 1;
977 141 davidgb
    end if;
978 192 davidgb
  end process;
979 141 davidgb
 
980 217 davidgb
  status_leds : process( rst_i, cpu_reset, cpu_addr, NMI, cpu_data_in, cpu_rw, CountL, sw, keyboard_data_out)
981 185 davidgb
  begin
982
    S(7) <= '0';
983 194 davidgb
    S(6) <= CountL(24);
984
         S(5) <= cpu_reset;
985 192 davidgb
         S(4) <= NMI;
986 185 davidgb
    case sw is
987 192 davidgb
         when "000" =>
988 185 davidgb
           S(3 downto 0) <= cpu_addr(3 downto 0);
989 192 davidgb
    when "001" =>
990 185 davidgb
           S(3 downto 0) <= cpu_addr(7 downto 4);
991 192 davidgb
         when "010" =>
992 185 davidgb
           S(3 downto 0) <= cpu_addr(11 downto 8);
993 192 davidgb
    when "011" =>
994 185 davidgb
           S(3 downto 0) <= cpu_addr(15 downto 12);
995 192 davidgb
    when "100" =>
996 185 davidgb
           S(3 downto 0) <= cpu_data_in(3 downto 0);
997 192 davidgb
    when "101" =>
998 185 davidgb
           S(3 downto 0) <= cpu_data_in(7 downto 4);
999 217 davidgb
    when "110" =>
1000
           S(3 downto 0) <= keyboard_data_out(3 downto 0);
1001
    when "111" =>
1002
           S(3 downto 0) <= keyboard_data_out(7 downto 4);
1003 185 davidgb
    when others => S(3 downto 0) <= (others => '0');
1004
         end case;
1005
  end process;
1006
 
1007 148 davidgb
--  debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
1008 141 davidgb
--                      cpu_halt, cpu_hold,
1009
--                      cpu_firq, cpu_irq, cpu_nmi,
1010
--                      cpu_addr, cpu_data_out, cpu_data_in )
1011 148 davidgb
--  begin
1012
--    cpu_reset_o    <= cpu_reset;
1013
--    cpu_clk_o      <= cpu_clk;
1014
--    cpu_rw_o       <= cpu_rw;
1015
--    cpu_vma_o      <= cpu_vma;
1016
--    cpu_halt_o     <= cpu_halt;
1017
--    cpu_hold_o     <= cpu_hold;
1018
--    cpu_firq_o     <= cpu_firq;
1019
--    cpu_irq_o      <= cpu_irq;
1020
--    cpu_nmi_o      <= cpu_nmi;
1021
--    cpu_addr_o     <= cpu_addr;
1022
--    cpu_data_out_o <= cpu_data_out;
1023
--    cpu_data_in_o  <= cpu_data_in;
1024
--  end process;
1025 141 davidgb
 
1026
end rtl; --===================== End of architecture =======================--
1027
 

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