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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_Atlys/] [system09.vhd] - Blame information for rev 223

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1 141 davidgb
--===========================================================================----
2
--
3
--  S Y N T H E Z I A B L E    System09 - SOC.
4
--
5
--  www.OpenCores.Org - February 2007
6
--  This core adheres to the GNU public license  
7
--
8
-- File name      : System09_Xess_XSA-3S1000.vhd
9
--
10
-- Purpose        : Top level file for 6809 compatible system on a chip
11
--                  Designed with Xilinx XC3S1000 Spartan 3 FPGA.
12
--                  Implemented With XESS XSA-3S1000 FPGA board.
13
--                  *** Note ***
14
--                  This configuration can run Flex9 however it only has
15
--                  32k bytes of user memory and the VDU is monochrome
16
--                  The design needs to be updated to use the SDRAM on 
17
--                  the XSA-3S1000 board.
18
--                  This configuration also lacks a DAT so cannot use
19
--                  the RAM Disk features of SYS09BUG.
20
--
21
-- Dependencies   : ieee.Std_Logic_1164
22
--                  ieee.std_logic_unsigned
23
--                  ieee.std_logic_arith
24
--                  ieee.numeric_std
25
--                  unisim.vcomponents
26
--
27
-- Uses           : mon_rom    (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
28
--                  cpu09      (cpu09.vhd)          CPU core
29
--                  ACIA_6850  (acia6850.vhd)      ACIA / UART
30
--                  ACIA_Clock (ACIA_Clock.vhd)      ACIA clock.
31
--                  timer      (timer.vhd)            Interrupt timer
32
--                  trap       (trap.vhd)             Bus condition trap logic
33
--                  flex_ram   (flex9_ram8k_b16.vhd)  Flex operating system
34
--                  ram_32K    (ram32k_b16.vhd)       32 KBytes of Block RAM
35
--                  
36
-- 
37
-- Author         : John E. Kent      
38
--                  dilbert57@opencores.org      
39
--
40
-- Memory Map     :
41
--
42
-- $0000 - User program RAM (32K Bytes)
43
-- $C000 - Flex Operating System memory (8K Bytes)
44
-- $E000 - ACIA (SWTPc)
45
-- $E010 - Reserved for FD1771 FDC (SWTPc)
46
-- $E050 - Timer
47
-- $E060 - Bus trap
48
-- $E070 - Reserced for Parallel I/O (B5-X300)
49
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
50
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
51
-- $F000 - Sys09Bug monitor Program (4K Bytes)
52
--
53
--===========================================================================----
54
--
55
-- Revision History:
56
--===========================================================================--
57
-- Version 0.1 - 20 March 2003
58
-- Version 0.2 - 30 March 2003
59
-- Version 0.3 - 29 April 2003
60
-- Version 0.4 - 29 June 2003
61
--
62
-- Version 0.5 - 19 July 2003
63
-- prints out "Hello World"
64
--
65
-- Version 0.6 - 5 September 2003
66
-- Runs SBUG
67
--
68
-- Version 1.0- 6 Sep 2003 - John Kent
69
-- Inverted SysClk
70
-- Initial release to Open Cores
71
--
72
-- Version 1.1 - 17 Jan 2004 - John Kent
73
-- Updated miniUart.
74
--
75
-- Version 1.2 - 25 Jan 2004 - John Kent
76
-- removed signals "test_alu" and "test_cc" 
77
-- Trap hardware re-instated.
78
--
79
-- Version 1.3 - 11 Feb 2004 - John Kent
80
-- Designed forked off to produce System09_VDU
81
-- Added VDU component
82
-- VDU runs at 25MHz and divides the clock by 2 for the CPU
83
-- UART Runs at 57.6 Kbps
84
--
85
-- Version 2.0 - 2 September 2004 - John Kent
86
-- ported to Digilent Xilinx Spartan3 starter board
87
-- removed Compact Flash and Trap Logic.
88
-- Replaced SBUG with KBug9s
89
--
90
-- Version 3.0 - 29th August 2006 - John Kent
91
-- Adapted to XSA-3S1000 board.
92
-- Removed DAT and miniUART.
93
-- Used 32KBytes of Block RAM.
94
--
95
-- Version 3.1 - 15th January 2007 - John Kent
96
-- Modified vdu8 interface
97
-- Added a clock divider
98
--
99
-- Version 3.2 - 25th February 2007 - John Kent
100
-- reinstated ACIA_6850 and ACIA_Clock
101
-- Updated VDU8 & Keyboard with generic parameters
102
-- Defined Constants for clock speed calculations
103
--
104
-- Version 3.3 - 1st July 2007 - John Kent
105
-- Made VDU mono to save on one RAMB16
106
-- Used distributed memory for Key Map ROM to save one RAMB16
107
-- Added Flex RAM at $C000 to $DFFF using 4 spare RAMB16s
108
-- Added timer and trap logic
109
-- Added IDE Interface for Compact Flash
110
-- Replaced KBug9s and stack with Sys09Bug.
111
--
112
-- Version 4.0 - 1st February 2008 - John kent
113
-- Replaced Block RAM with SDRAM Interface
114
-- Modified Hold timing for SDRAM
115
-- Added CF and Ethernet interface 
116
-- via the 16 bit peripheral bus at $E100
117
--
118
--===========================================================================--
119
library ieee;
120
   use ieee.std_logic_1164.all;
121
   use IEEE.STD_LOGIC_ARITH.ALL;
122
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
123
   use ieee.numeric_std.all;
124
library work;
125
   use work.common.all;
126
library unisim;
127 162 davidgb
   use unisim.vcomponents.all;
128 141 davidgb
 
129
entity system09 is
130
  port(
131
    CLKA         : in  Std_Logic;  -- 100MHz Clock input
132 192 davidgb
    RESET        : in  Std_logic;  -- Master Reset input (active high) -- red "RESET" PB
133
    NMI          : in  Std_logic;  -- Non Maskable Interrupt input (active high) -- Center PB
134 141 davidgb
 
135 209 davidgb
    -- PS/2 Keyboard
136
    ps2_clk      : inout Std_logic;
137
    ps2_dat      : inout Std_Logic;
138
 
139
    -- HDMI output
140 212 davidgb
    TMDSp_clock  : out std_logic;
141
    TMDSn_clock  : out std_logic;
142
    TMDSp        : out std_logic_vector(2 downto 0);
143
    TMDSn        : out std_logic_vector(2 downto 0);
144 209 davidgb
 
145 212 davidgb
    -- RS232 Port - via Atlys UART over USB (no h/w/ handshake available)
146 195 davidgb
--  RS232_CTS    : in  Std_Logic;
147
--  RS232_RTS    : out Std_Logic;
148 185 davidgb
    RS232_RXD    : in  Std_Logic;
149
    RS232_TXD    : out Std_Logic;
150 222 davidgb
 
151
    -- SPI Interface Signals (Pmod-SDCard)
152
    spi_miso           : in  std_logic;
153
    spi_mosi           : out std_logic;
154
    spi_clk            : out std_logic;
155
    spi_cs_n           : out std_logic_vector(7 downto 0);
156
 
157 186 davidgb
    -- slide switches
158 222 davidgb
    sw           : in std_logic_vector(3 downto 0);
159 186 davidgb
    -- Status 7 segment LED
160 192 davidgb
    S            : out std_logic_vector(7 downto 0)
161 185 davidgb
 
162 141 davidgb
-- CPU Debug Interface signals
163
--    cpu_reset_o     : out Std_Logic;
164
--    cpu_clk_o       : out Std_Logic;
165
--    cpu_rw_o        : out std_logic;
166
--    cpu_vma_o       : out std_logic;
167
--    cpu_halt_o      : out std_logic;
168
--    cpu_hold_o      : out std_logic;
169
--    cpu_firq_o      : out std_logic;
170
--    cpu_irq_o       : out std_logic;
171
--    cpu_nmi_o       : out std_logic;
172
--    cpu_addr_o      : out std_logic_vector(15 downto 0);
173
--    cpu_data_in_o   : out std_logic_vector(7 downto 0);
174
--    cpu_data_out_o  : out std_logic_vector(7 downto 0);
175
 
176 148 davidgb
  );
177 141 davidgb
end system09;
178
 
179
-------------------------------------------------------------------------------
180
-- Architecture for System09
181
-------------------------------------------------------------------------------
182
architecture rtl of system09 is
183
 
184
  -----------------------------------------------------------------------------
185
  -- constants
186
  -----------------------------------------------------------------------------
187 186 davidgb
  constant CLOCK_MODE           : natural := 0; -- 0 means normal, 1 means single-step
188
 
189 192 davidgb
  constant SYS_CLK_FREQ         : natural := 100_000_000;  -- FPGA System Clock (in Hz)
190 186 davidgb
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
191 141 davidgb
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
192 209 davidgb
  constant VGA_CLK_FREQ         : natural := 25_000_000;  -- VGA Pixel Clock
193
  constant VGA_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
194 141 davidgb
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
195
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
196
 
197
  -----------------------------------------------------------------------------
198
  -- Signals
199 174 davidgb
  -----------------------------------------------------------------------------
200 192 davidgb
 
201 141 davidgb
  -- BOOT ROM
202
  signal rom_cs         : Std_logic;
203
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
204
 
205
  -- Flex Memory & Monitor Stack
206
  signal flex_cs        : Std_logic;
207
  signal flex_data_out  : Std_Logic_Vector(7 downto 0);
208
 
209
  -- ACIA/UART Interface signals
210
  signal acia_data_out  : Std_Logic_Vector(7 downto 0);
211
  signal acia_cs        : Std_Logic;
212
  signal acia_irq       : Std_Logic;
213
  signal acia_clk       : Std_Logic;
214 192 davidgb
  signal RXD            : Std_Logic;
215
  signal TXD            : Std_Logic;
216 141 davidgb
  signal DCD_n          : Std_Logic;
217
  signal RTS_n          : Std_Logic;
218
  signal CTS_n          : Std_Logic;
219 209 davidgb
 
220
  -- keyboard port
221
  signal keyboard_data_out : std_logic_vector(7 downto 0);
222
  signal keyboard_cs       : std_logic;
223
  signal keyboard_irq      : std_logic;
224
 
225 141 davidgb
  -- RAM
226 173 davidgb
  signal ram1_cs         : std_logic;
227
  signal ram1_data_out   : std_logic_vector(7 downto 0);
228
  signal ram2_cs         : std_logic;
229
  signal ram2_data_out   : std_logic_vector(7 downto 0);
230
  signal ram3_cs         : std_logic;
231 141 davidgb
 
232
  -- CPU Interface signals
233
  signal cpu_reset      : Std_Logic;
234
  signal cpu_clk        : Std_Logic;
235
  signal cpu_rw         : std_logic;
236
  signal cpu_vma        : std_logic;
237
  signal cpu_halt       : std_logic;
238
  signal cpu_hold       : std_logic;
239
  signal cpu_firq       : std_logic;
240
  signal cpu_irq        : std_logic;
241
  signal cpu_nmi        : std_logic;
242
  signal cpu_addr       : std_logic_vector(15 downto 0);
243
  signal cpu_data_in    : std_logic_vector(7 downto 0);
244
  signal cpu_data_out   : std_logic_vector(7 downto 0);
245
 
246
  -- Dynamic Address Translation
247
  signal dat_cs       : std_logic;
248
  signal dat_addr     : std_logic_vector(7 downto 0);
249
 
250 209 davidgb
  -- Video Display Unit
251
  signal vdu_clk        : std_logic;
252
  signal vdu_cs         : std_logic;
253 212 davidgb
  signal vdu_data_out   : std_logic_vector(7 downto 0);
254 222 davidgb
 
255
  -- SPI-master to SDcard
256
  signal spi_data_out   : std_logic_vector(7 downto 0);
257
  signal spi_cs         : std_logic;
258
  signal spi_irq        : std_logic;
259
 
260 141 davidgb
  -- timer
261
  signal timer_data_out : std_logic_vector(7 downto 0);
262
  signal timer_cs       : std_logic;
263
  signal timer_irq      : std_logic;
264
 
265
  -- trap
266
  signal trap_cs        : std_logic;
267
  signal trap_data_out  : std_logic_vector(7 downto 0);
268
  signal trap_irq       : std_logic;
269
 
270
  signal rst_i         : std_logic;     -- internal reset signal
271 186 davidgb
  signal clk_i         : std_logic;     -- internal master clock signal
272 148 davidgb
 
273 194 davidgb
  signal CountL        : std_logic_vector(24 downto 0);
274 141 davidgb
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
275
  signal Clk25         : std_logic;
276
 
277
-----------------------------------------------------------------
278
--
279
-- CPU09 CPU core
280
--
281
-----------------------------------------------------------------
282
 
283
component cpu09
284
  port (
285
    clk:      in  std_logic;
286
    rst:      in  std_logic;
287
    vma:      out std_logic;
288
    addr:     out std_logic_vector(15 downto 0);
289
    rw:       out std_logic;     -- Asynchronous memory interface
290
    data_out: out std_logic_vector(7 downto 0);
291
    data_in:  in  std_logic_vector(7 downto 0);
292
    irq:      in  std_logic;
293
    firq:     in  std_logic;
294
    nmi:      in  std_logic;
295
    halt:     in  std_logic;
296
    hold:     in  std_logic
297
  );
298
end component;
299
 
300
----------------------------------------
301
--
302
-- 4K Block RAM Monitor ROM
303 148 davidgb
-- $F000 - $FFFF
304 141 davidgb
--
305
----------------------------------------
306 148 davidgb
 
307 141 davidgb
component mon_rom
308 148 davidgb
  Port (
309
    clk   : in  std_logic;
310
    rst   : in  std_logic;
311
    cs    : in  std_logic;
312
    rw    : in  std_logic;
313
    addr  : in  std_logic_vector (11 downto 0);
314
    data_out : out std_logic_vector (7 downto 0);
315
    data_in : in  std_logic_vector (7 downto 0)
316
  );
317 141 davidgb
end component;
318
 
319
----------------------------------------
320
--
321
-- 8KBytes Block RAM for FLEX9
322
-- $C000 - $DFFF
323
--
324
----------------------------------------
325 148 davidgb
 
326 141 davidgb
component flex_ram
327
  Port (
328
    clk      : in  std_logic;
329
    rst      : in  std_logic;
330
    cs       : in  std_logic;
331
    rw       : in  std_logic;
332
    addr     : in  std_logic_vector (12 downto 0);
333
    data_out    : out std_logic_vector (7 downto 0);
334
    data_in    : in  std_logic_vector (7 downto 0)
335 148 davidgb
  );
336 141 davidgb
end component;
337 170 davidgb
 
338
----------------------------------------
339
--
340
-- 32KBytes Block RAM 0000
341
-- $0000 - $7FFF
342
--
343
----------------------------------------
344 141 davidgb
 
345 170 davidgb
component ram_32k
346
  Port (
347
    clk      : in  std_logic;
348
    rst      : in  std_logic;
349
    cs       : in  std_logic;
350
    rw       : in  std_logic;
351
    addr     : in  std_logic_vector (14 downto 0);
352
    data_out    : out std_logic_vector (7 downto 0);
353
    data_in    : in  std_logic_vector (7 downto 0)
354
  );
355
end component;
356
 
357 173 davidgb
 
358
----------------------------------------
359
--
360
-- 16KBytes Block RAM 8000
361
-- $8000 - $BFFF
362
--
363
----------------------------------------
364 170 davidgb
 
365 173 davidgb
component ram_16k
366
  Port (
367
    clk      : in  std_logic;
368
    rst      : in  std_logic;
369
    cs       : in  std_logic;
370
    rw       : in  std_logic;
371
    addr     : in  std_logic_vector (13 downto 0);
372
    data_out    : out std_logic_vector (7 downto 0);
373
    data_in    : in  std_logic_vector (7 downto 0)
374
  );
375
end component;
376
 
377 141 davidgb
-----------------------------------------------------------------
378
--
379
-- 6850 Compatible ACIA / UART
380
--
381
-----------------------------------------------------------------
382
 
383
component acia6850
384
  port (
385 148 davidgb
    clk      : in  Std_Logic;  -- System Clock
386
    rst      : in  Std_Logic;  -- Reset input (active high)
387
    cs       : in  Std_Logic;  -- miniUART Chip Select
388
    rw       : in  Std_Logic;  -- Read / Not Write
389
    addr     : in  Std_Logic;  -- Register Select
390
    data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
391
    data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
392
    irq      : out Std_Logic;  -- Interrupt
393
    RxC      : in  Std_Logic;  -- Receive Baud Clock
394
    TxC      : in  Std_Logic;  -- Transmit Baud Clock
395
    RxD      : in  Std_Logic;  -- Receive Data
396
    TxD      : out Std_Logic;  -- Transmit Data
397
    DCD_n    : in  Std_Logic;  -- Data Carrier Detect
398
    CTS_n    : in  Std_Logic;  -- Clear To Send
399
    RTS_n    : out Std_Logic   -- Request To send
400
  );
401 141 davidgb
end component;
402
 
403
-----------------------------------------------------------------
404
--
405
-- ACIA Clock divider
406
--
407
-----------------------------------------------------------------
408
 
409
component ACIA_Clock
410
  generic (
411 148 davidgb
    SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
412
    ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
413 141 davidgb
  );
414
  port (
415 148 davidgb
    clk      : in  Std_Logic;  -- System Clock Input
416
    ACIA_clk : out Std_logic   -- ACIA Clock output
417 141 davidgb
  );
418
end component;
419
 
420
----------------------------------------
421
--
422 209 davidgb
-- PS/2 Keyboard
423
--
424
----------------------------------------
425
 
426
component keyboard
427
  generic(
428
    KBD_CLK_FREQ : integer := CPU_CLK_FREQ
429
  );
430
  port(
431
    clk             : in    std_logic;
432
    rst             : in    std_logic;
433
    cs              : in    std_logic;
434
    rw              : in    std_logic;
435
    addr            : in    std_logic;
436
    data_in         : in    std_logic_vector(7 downto 0);
437
    data_out        : out   std_logic_vector(7 downto 0);
438
    irq             : out   std_logic;
439
    kbd_clk         : inout std_logic;
440
    kbd_data        : inout std_logic
441
  );
442
end component;
443
 
444
----------------------------------------
445
--
446
-- Video Display Unit.
447
--
448
----------------------------------------
449
 
450 212 davidgb
component vdu8_hdmi
451 209 davidgb
  generic(
452
    VDU_CLK_FREQ           : integer := CPU_CLK_FREQ; -- HZ
453
    VGA_CLK_FREQ           : integer := VGA_CLK_FREQ; -- HZ
454
    VGA_HOR_CHARS          : integer := 80; -- CHARACTERS
455
    VGA_VER_CHARS          : integer := 25; -- CHARACTERS
456
    VGA_PIX_PER_CHAR       : integer := 8;  -- PIXELS
457
    VGA_LIN_PER_CHAR       : integer := 16; -- LINES
458
    VGA_HOR_BACK_PORCH     : integer := 40; -- PIXELS
459
    VGA_HOR_SYNC           : integer := 96; -- PIXELS
460
    VGA_HOR_FRONT_PORCH    : integer := 24; -- PIXELS
461
    VGA_VER_BACK_PORCH     : integer := 13; -- LINES
462
    VGA_VER_SYNC           : integer := 2;  -- LINES
463
    VGA_VER_FRONT_PORCH    : integer := 35  -- LINES
464
  );
465
  port(
466
    -- control register interface
467
    vdu_clk      : in  std_logic;  -- CPU Clock - 25MHz
468
    vdu_rst      : in  std_logic;
469
    vdu_cs       : in  std_logic;
470
    vdu_rw       : in  std_logic;
471
    vdu_addr     : in  std_logic_vector(2 downto 0);
472
    vdu_data_in  : in  std_logic_vector(7 downto 0);
473 212 davidgb
    vdu_data_out : out std_logic_vector(7 downto 0);
474
    -- HDMI TMDS outputs
475
         hdmi_clk     : in std_logic;
476
    TMDSp_clock  : out std_logic;
477
    TMDSn_clock  : out std_logic;
478
    TMDSp        : out std_logic_vector(2 downto 0);
479
    TMDSn        : out std_logic_vector(2 downto 0)
480 209 davidgb
  );
481
end component;
482 222 davidgb
 
483
----------------------------------------
484
--
485
-- SPI master module
486
--
487
----------------------------------------
488
 
489
component spi_master
490
  port (
491
    --
492
    -- CPU Interface Signals
493
    --
494
    clk                : in  std_logic;
495
    reset              : in  std_logic;
496
    cs                 : in  std_logic;
497
    rw                 : in  std_logic;
498
    addr               : in  std_logic_vector(1 downto 0);
499
    data_in            : in  std_logic_vector(7 downto 0);
500
    data_out           : out std_logic_vector(7 downto 0);
501
    irq                : out std_logic;
502
    --
503
    -- SPI Interface Signals
504
    --
505
    spi_miso           : in  std_logic;
506
    spi_mosi           : out std_logic;
507
    spi_clk            : out std_logic;
508
    spi_cs_n           : out std_logic_vector(7 downto 0)
509
    );
510
end component;
511 209 davidgb
 
512
----------------------------------------
513
--
514 141 davidgb
-- Timer module
515
--
516
----------------------------------------
517
 
518
component timer
519
  port (
520 148 davidgb
    clk       : in std_logic;
521
    rst       : in std_logic;
522
    cs        : in std_logic;
523
    rw        : in std_logic;
524
    addr      : in std_logic;
525
    data_in   : in std_logic_vector(7 downto 0);
526
    data_out  : out std_logic_vector(7 downto 0);
527
    irq       : out std_logic
528
  );
529 141 davidgb
end component;
530
 
531
------------------------------------------------------------
532
--
533
-- Bus Trap logic
534
--
535
------------------------------------------------------------
536
 
537
component trap
538 148 davidgb
  port (
539 141 davidgb
    clk        : in  std_logic;
540
    rst        : in  std_logic;
541
    cs         : in  std_logic;
542
    rw         : in  std_logic;
543
    vma        : in  std_logic;
544
    addr       : in  std_logic_vector(15 downto 0);
545
    data_in    : in  std_logic_vector(7 downto 0);
546
    data_out   : out std_logic_vector(7 downto 0);
547
    irq        : out std_logic
548
  );
549
end component;
550
 
551
----------------------------------------
552
--
553
-- Dynamic Address Translation Registers
554
--
555
----------------------------------------
556 148 davidgb
 
557 141 davidgb
component dat_ram
558
  port (
559
    clk      : in  std_logic;
560
    rst      : in  std_logic;
561
    cs       : in  std_logic;
562
    rw       : in  std_logic;
563
    addr_lo  : in  std_logic_vector(3 downto 0);
564
    addr_hi  : in  std_logic_vector(3 downto 0);
565
    data_in  : in  std_logic_vector(7 downto 0);
566
    data_out : out std_logic_vector(7 downto 0)
567
  );
568
end component;
569 185 davidgb
 
570 141 davidgb
--
571
-- Clock buffer
572
--
573 148 davidgb
 
574 141 davidgb
component BUFG
575
   Port (
576
     i: in std_logic;
577
     o: out std_logic
578
  );
579
end component;
580
 
581 185 davidgb
begin
582
 
583 186 davidgb
  --
584
  -- Generate CPU & Pixel Clock from Memory Clock
585
  --
586 192 davidgb
 
587
  my_prescaler : process( clk_i, clk_count )
588
  begin
589
    if rising_edge( clk_i ) then
590
      if clk_count = 0 then
591
        clk_count <= CPU_CLK_DIV-1;
592
      else
593
        clk_count <= clk_count - 1;
594 186 davidgb
      end if;
595 192 davidgb
      if clk_count = 0 then
596
         clk25 <= '0';
597
      elsif clk_count = (CPU_CLK_DIV/2) then
598
         clk25 <= '1';
599
      end if;
600
    end if;
601
  end process;
602 186 davidgb
 
603
  --
604
  -- Reset button and reset timer
605
  --
606 192 davidgb
  my_switch_assignments : process( rst_i, RESET)
607 186 davidgb
  begin
608 194 davidgb
    rst_i <= not RESET;
609 186 davidgb
    cpu_reset <= rst_i;
610
  end process;
611 185 davidgb
 
612 186 davidgb
  clk_i <= CLKA;
613
 
614 141 davidgb
  -----------------------------------------------------------------------------
615
  -- Instantiation of internal components
616
  -----------------------------------------------------------------------------
617
 
618 148 davidgb
  my_cpu : cpu09
619
    port map (
620
      clk       => cpu_clk,
621
      rst       => cpu_reset,
622
      vma       => cpu_vma,
623
      addr      => cpu_addr(15 downto 0),
624
      rw        => cpu_rw,
625
      data_out  => cpu_data_out,
626
      data_in   => cpu_data_in,
627
      irq       => cpu_irq,
628
      firq      => cpu_firq,
629
      nmi       => cpu_nmi,
630
      halt      => cpu_halt,
631
      hold      => cpu_hold
632
    );
633 141 davidgb
 
634 148 davidgb
  my_rom : mon_rom
635
    port map (
636 192 davidgb
      clk       => cpu_clk,
637
      rst       => cpu_reset,
638
      cs        => rom_cs,
639
      rw        => '1',
640
      addr      => cpu_addr(11 downto 0),
641
      data_in   => cpu_data_out,
642
      data_out  => rom_data_out
643 141 davidgb
    );
644
 
645 148 davidgb
  my_flex : flex_ram
646
    port map (
647
      clk       => cpu_clk,
648
      rst       => cpu_reset,
649
      cs        => flex_cs,
650
      rw        => cpu_rw,
651
      addr      => cpu_addr(12 downto 0),
652 192 davidgb
      data_out  => flex_data_out,
653
      data_in   => cpu_data_out
654 170 davidgb
    );
655
 
656
  my_32k : ram_32k
657
    port map (
658
      clk       => cpu_clk,
659
      rst       => cpu_reset,
660 173 davidgb
      cs        => ram1_cs,
661 170 davidgb
      rw        => cpu_rw,
662
      addr      => cpu_addr(14 downto 0),
663 192 davidgb
      data_out  => ram1_data_out,
664
      data_in   => cpu_data_out
665 170 davidgb
    );
666 173 davidgb
 
667
  my_16k : ram_16k
668
    port map (
669
      clk       => cpu_clk,
670
      rst       => cpu_reset,
671
      cs        => ram2_cs,
672
      rw        => cpu_rw,
673
      addr      => cpu_addr(13 downto 0),
674 192 davidgb
      data_out  => ram2_data_out,
675
      data_in   => cpu_data_out
676 173 davidgb
    );
677
 
678 148 davidgb
  my_acia  : acia6850
679
    port map (
680
      clk       => cpu_clk,
681
      rst       => cpu_reset,
682
      cs        => acia_cs,
683
      rw        => cpu_rw,
684
      addr      => cpu_addr(0),
685
      data_in   => cpu_data_out,
686
      data_out  => acia_data_out,
687
      irq       => acia_irq,
688
      RxC       => acia_clk,
689
      TxC       => acia_clk,
690 192 davidgb
      RxD       => RXD,
691
      TxD       => TXD,
692
      DCD_n     => DCD_n,
693
      CTS_n     => CTS_n,
694
      RTS_n     => RTS_n
695
    );
696
 
697
  --
698
  -- RS232 signals:
699
  --
700 195 davidgb
  my_acia_assignments : process( RS232_RXD, -- RS232_CTS,
701
                                 TXD, RTS_n )
702 192 davidgb
  begin
703
    RXD       <= RS232_RXD;
704 195 davidgb
    CTS_n     <= '0'; -- RS232_CTS;
705 192 davidgb
    DCD_n     <= '0';
706
    RS232_TXD <= TXD;
707 195 davidgb
--  RS232_RTS <= not RTS_n;
708 192 davidgb
  end process;
709 186 davidgb
 
710 148 davidgb
  my_ACIA_Clock : ACIA_Clock
711
    generic map(
712 185 davidgb
      SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
713 148 davidgb
      ACIA_CLK_FREQ => ACIA_CLK_FREQ
714
    )
715
    port map(
716 192 davidgb
      clk        => clk_i,
717 148 davidgb
      acia_clk   => acia_clk
718
    );
719 141 davidgb
 
720 148 davidgb
  ----------------------------------------
721
  --
722 209 davidgb
  -- PS/2 Keyboard Interface
723
  --
724
  ----------------------------------------
725
  my_keyboard : keyboard
726
    generic map (
727
      KBD_CLK_FREQ => CPU_CLK_FREQ
728
    )
729
    port map(
730
      clk          => cpu_clk,
731
      rst          => cpu_reset,
732
      cs           => keyboard_cs,
733
      rw           => cpu_rw,
734
      addr         => cpu_addr(0),
735
      data_in      => cpu_data_out(7 downto 0),
736
      data_out     => keyboard_data_out(7 downto 0),
737
      irq          => keyboard_irq,
738
      kbd_clk      => ps2_clk,
739
      kbd_data     => ps2_dat
740
    );
741
 
742
  ----------------------------------------
743
  --
744
  -- Video Display Unit instantiation
745
  --
746
  ----------------------------------------
747
  vdu_clk_buffer : BUFG
748
    port map(
749
      i => Clk25,
750
      o => vdu_clk
751
    );
752
 
753 212 davidgb
  my_vdu : vdu8_hdmi
754 209 davidgb
    generic map(
755
      VDU_CLK_FREQ           => CPU_CLK_FREQ, -- HZ
756
      VGA_CLK_FREQ           => VGA_CLK_FREQ, -- HZ
757
      VGA_HOR_CHARS          => 80, -- CHARACTERS
758
      VGA_VER_CHARS          => 25, -- CHARACTERS
759
      VGA_PIX_PER_CHAR       => 8,  -- PIXELS
760
      VGA_LIN_PER_CHAR       => 16, -- LINES
761
      VGA_HOR_BACK_PORCH     => 40, -- PIXELS
762
      VGA_HOR_SYNC           => 96, -- PIXELS
763
      VGA_HOR_FRONT_PORCH    => 24, -- PIXELS
764
      VGA_VER_BACK_PORCH     => 13, -- LINES
765
      VGA_VER_SYNC           => 2,  -- LINES
766
      VGA_VER_FRONT_PORCH    => 35  -- LINES
767
    )
768
    port map(
769
      -- Control Registers
770
      vdu_clk       => cpu_clk,               -- 12.5 MHz System Clock in
771
      vdu_rst       => cpu_reset,
772
      vdu_cs        => vdu_cs,
773
      vdu_rw        => cpu_rw,
774
      vdu_addr      => cpu_addr(2 downto 0),
775
      vdu_data_in   => cpu_data_out,
776 212 davidgb
      vdu_data_out  => vdu_data_out,
777
                -- HDMI port connections
778
                hdmi_clk    => Clk25,
779
                TMDSp       => TMDSp,
780
                TMDSn       => TMDSn,
781
                TMDSp_clock => TMDSp_clock,
782
                TMDSn_clock => TMDSn_clock
783 209 davidgb
   );
784
 
785 222 davidgb
  ----------------------------------------
786
  --
787
  -- SPI-Master to SDcard
788
  --
789
  ----------------------------------------
790
  my_spi_master : spi_master
791
    port map (
792
      clk        => cpu_clk,
793
      reset      => cpu_reset,
794
      cs         => spi_cs,
795
      rw         => cpu_rw,
796
      addr       => cpu_addr(1 downto 0),
797
      data_in    => cpu_data_out,
798
      data_out   => spi_data_out,
799
      irq        => spi_irq,
800
                spi_miso   => spi_miso,
801
                spi_mosi   => spi_mosi,
802
                spi_clk    => spi_clk,
803
                spi_cs_n   => spi_cs_n
804
    );
805 209 davidgb
 
806
  ----------------------------------------
807
  --
808 148 davidgb
  -- Timer Module
809
  --
810
  ----------------------------------------
811
  my_timer  : timer
812
    port map (
813
      clk       => cpu_clk,
814
      rst       => cpu_reset,
815
      cs        => timer_cs,
816
      rw        => cpu_rw,
817
      addr      => cpu_addr(0),
818
      data_in   => cpu_data_out,
819
      data_out  => timer_data_out,
820
      irq       => timer_irq
821
    );
822 141 davidgb
 
823 148 davidgb
  ----------------------------------------
824
  --
825
  -- Bus Trap Interrupt logic
826
  --
827
  ----------------------------------------
828
  my_trap : trap
829
    port map (
830
      clk        => cpu_clk,
831
      rst        => cpu_reset,
832
      cs         => trap_cs,
833
      rw         => cpu_rw,
834
      vma        => cpu_vma,
835
      addr       => cpu_addr,
836
      data_in    => cpu_data_out,
837
      data_out   => trap_data_out,
838
      irq        => trap_irq
839 141 davidgb
    );
840
 
841 148 davidgb
  my_dat : dat_ram
842
    port map (
843
      clk       => cpu_clk,
844
      rst       => cpu_reset,
845
      cs        => dat_cs,
846
      rw        => cpu_rw,
847
      addr_hi   => cpu_addr(15 downto 12),
848
      addr_lo   => cpu_addr(3 downto 0),
849
      data_in   => cpu_data_out,
850
      data_out  => dat_addr(7 downto 0)
851 141 davidgb
    );
852
 
853 148 davidgb
  cpu_clk_buffer : BUFG
854 141 davidgb
    port map(
855 148 davidgb
      i => Clk25,
856
      o => cpu_clk
857 141 davidgb
    );
858 162 davidgb
 
859 148 davidgb
  ----------------------------------------------------------------------
860
  --
861
  -- Process to decode memory map
862
  --
863
  ----------------------------------------------------------------------
864 141 davidgb
 
865 148 davidgb
  mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
866 141 davidgb
                     dat_addr,
867
                     rom_data_out,
868
                     flex_data_out,
869
                     acia_data_out,
870 209 davidgb
                     keyboard_data_out,
871 222 davidgb
                     vdu_data_out,
872
                                                        spi_data_out,
873 141 davidgb
                     timer_data_out,
874
                     trap_data_out,
875 173 davidgb
                     ram1_data_out, ram2_data_out
876 141 davidgb
                     )
877 148 davidgb
  begin
878
    cpu_data_in <= (others=>'0');
879
    dat_cs      <= '0';
880
    rom_cs      <= '0';
881
    flex_cs     <= '0';
882
    acia_cs     <= '0';
883 209 davidgb
    keyboard_cs <= '0';
884 222 davidgb
    vdu_cs      <= '0';
885
    spi_cs     <= '0';
886 148 davidgb
    timer_cs    <= '0';
887
    trap_cs     <= '0';
888 192 davidgb
    ram1_cs     <= '0';
889
    ram2_cs     <= '0';
890
    ram3_cs     <= '0';
891 173 davidgb
 
892 148 davidgb
    if cpu_addr( 15 downto 8 ) = "11111111" then  -- $FFxx
893
      cpu_data_in <= rom_data_out;
894
      dat_cs      <= cpu_vma;              -- write DAT
895
      rom_cs      <= cpu_vma;              -- read  ROM
896 141 davidgb
 
897 148 davidgb
    --
898
    -- Sys09Bug Monitor ROM $F000 - $FFFF
899
    --
900
    elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
901
      cpu_data_in <= rom_data_out;
902
      rom_cs      <= cpu_vma;
903 141 davidgb
 
904 148 davidgb
    --
905
    -- IO Devices $E000 - $E7FF
906
    --
907
    elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
908
      case cpu_addr(11 downto 8) is
909
        --
910
        -- SWTPC peripherals from $E000 to $E0FF
911
        --
912
        when "0000" =>
913
          case cpu_addr(7 downto 4) is
914
          --
915
          -- Console Port ACIA $E000 - $E00F
916
          --
917
            when "0000" => -- $E000
918
              cpu_data_in <= acia_data_out;
919
              acia_cs     <= cpu_vma;
920 141 davidgb
 
921 148 davidgb
            --
922
            -- Reserved
923
            -- Floppy Disk Controller port $E010 - $E01F
924
            --
925 141 davidgb
 
926 148 davidgb
            --
927 209 davidgb
            -- Keyboard port $E020 - $E02F
928
            --
929
            when "0010" => -- $E020
930
              cpu_data_in <= keyboard_data_out;
931
              keyboard_cs <= cpu_vma;
932
 
933
            --
934
            -- VDU port $E030 - $E03F
935
            --
936
            when "0011" => -- $E030
937
              cpu_data_in <= vdu_data_out;
938
              vdu_cs      <= cpu_vma;
939
 
940
            --
941 148 davidgb
            -- Reserved SWTPc MP-T Timer $E040 - $E04F
942
            --
943
            when "0100" => -- $E040
944
              cpu_data_in <= (others=> '0');
945 141 davidgb
 
946 148 davidgb
            --
947
            -- Timer $E050 - $E05F
948
            --
949
            when "0101" => -- $E050
950
              cpu_data_in <= timer_data_out;
951
              timer_cs    <= cpu_vma;
952 141 davidgb
 
953 148 davidgb
            --
954
            -- Bus Trap Logic $E060 - $E06F
955
            --
956
            when "0110" => -- $E060
957
              cpu_data_in <= trap_data_out;
958
              trap_cs     <= cpu_vma;
959 141 davidgb
 
960 148 davidgb
            --
961
            -- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
962
            --
963
 
964
            --
965
            -- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
966 222 davidgb
            --
967
 
968 148 davidgb
            --
969 222 davidgb
            -- SPI-master $E0A0 - $E0AF
970
            --
971
            when "1010" => -- $E0A0
972
              cpu_data_in <= spi_data_out;
973
              spi_cs     <= cpu_vma;
974 148 davidgb
 
975
            --
976
            -- Remaining 6 slots reserved for non SWTPc Peripherals
977
            --
978
            when others => -- $E0A0 to $E0FF
979
              null;
980
          end case;
981
 
982
        --
983
        -- $E200 to $EFFF reserved for future use
984
        --
985
        when others =>
986 141 davidgb
           null;
987 148 davidgb
      end case;
988 170 davidgb
 
989
    --
990 192 davidgb
    -- Block RAM (32k) $00000 - $07FFF
991 170 davidgb
    --
992 192 davidgb
    elsif dat_addr(7 downto 3) = "00000"   then -- $00000 - $07FFF
993 173 davidgb
      cpu_data_in <= ram1_data_out;
994
      ram1_cs     <= cpu_vma;
995
 
996
    --
997 192 davidgb
    -- Block RAM (16k) $08000 - $0BFFF
998 173 davidgb
    --
999 192 davidgb
    elsif dat_addr(7 downto 2) = "000010"  then -- $08000 - $0BFFF
1000 173 davidgb
      cpu_data_in <= ram2_data_out;
1001
      ram2_cs     <= cpu_vma;
1002 141 davidgb
 
1003 148 davidgb
    --
1004 192 davidgb
    -- Flex RAM (8k) $0C000 - $0DFFF
1005
    --
1006
    elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
1007
      cpu_data_in <= flex_data_out;
1008
      flex_cs     <= cpu_vma;
1009
 
1010
    --
1011 148 davidgb
    -- Everything else is RAM
1012
    --
1013 141 davidgb
    else
1014 173 davidgb
      cpu_data_in <= (others => '0');
1015
      ram3_cs      <= cpu_vma;
1016 141 davidgb
    end if;
1017
 
1018 148 davidgb
  end process;
1019 141 davidgb
 
1020 148 davidgb
  --
1021
  -- Interrupts and other bus control signals
1022
  --
1023 192 davidgb
  interrupts : process( NMI,
1024 141 davidgb
                      acia_irq,
1025 222 davidgb
                      keyboard_irq,
1026
                      spi_irq,
1027 141 davidgb
                      trap_irq,
1028
                      timer_irq
1029
                      )
1030 148 davidgb
  begin
1031 222 davidgb
    cpu_irq    <= acia_irq or keyboard_irq or spi_irq;
1032 192 davidgb
    cpu_nmi    <= trap_irq or NMI;
1033 141 davidgb
    cpu_firq   <= timer_irq;
1034
    cpu_halt   <= '0';
1035 170 davidgb
    cpu_hold   <= '0'; -- pb_hold or ram_hold;
1036 148 davidgb
  end process;
1037 192 davidgb
 
1038 148 davidgb
  --
1039 185 davidgb
  -- Flash 7 segment LEDS
1040 148 davidgb
  --
1041 185 davidgb
  my_led_flasher: process( clk_i, rst_i, CountL )
1042 148 davidgb
  begin
1043 185 davidgb
    if rst_i = '1' then
1044 194 davidgb
         CountL <= "0000000000000000000000000";
1045 185 davidgb
    elsif rising_edge(clk_i) then
1046
         CountL <= CountL + 1;
1047 141 davidgb
    end if;
1048 192 davidgb
  end process;
1049 141 davidgb
 
1050 217 davidgb
  status_leds : process( rst_i, cpu_reset, cpu_addr, NMI, cpu_data_in, cpu_rw, CountL, sw, keyboard_data_out)
1051 185 davidgb
  begin
1052
    S(7) <= '0';
1053 194 davidgb
    S(6) <= CountL(24);
1054
         S(5) <= cpu_reset;
1055 192 davidgb
         S(4) <= NMI;
1056 185 davidgb
    case sw is
1057 222 davidgb
         when "0000" =>
1058 185 davidgb
           S(3 downto 0) <= cpu_addr(3 downto 0);
1059 222 davidgb
    when "0001" =>
1060 185 davidgb
           S(3 downto 0) <= cpu_addr(7 downto 4);
1061 222 davidgb
         when "0010" =>
1062 185 davidgb
           S(3 downto 0) <= cpu_addr(11 downto 8);
1063 222 davidgb
    when "0011" =>
1064 185 davidgb
           S(3 downto 0) <= cpu_addr(15 downto 12);
1065 222 davidgb
    when "0100" =>
1066 185 davidgb
           S(3 downto 0) <= cpu_data_in(3 downto 0);
1067 222 davidgb
    when "0101" =>
1068 185 davidgb
           S(3 downto 0) <= cpu_data_in(7 downto 4);
1069 222 davidgb
    when "0110" =>
1070 217 davidgb
           S(3 downto 0) <= keyboard_data_out(3 downto 0);
1071 222 davidgb
    when "0111" =>
1072
           S(3 downto 0) <= keyboard_data_out(7 downto 4);
1073
    when "1000" =>
1074
           S(3 downto 0) <= spi_data_out(3 downto 0);
1075
    when "1001" =>
1076
           S(3 downto 0) <= spi_data_out(7 downto 4);
1077 185 davidgb
    when others => S(3 downto 0) <= (others => '0');
1078
         end case;
1079
  end process;
1080
 
1081 148 davidgb
--  debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
1082 141 davidgb
--                      cpu_halt, cpu_hold,
1083
--                      cpu_firq, cpu_irq, cpu_nmi,
1084
--                      cpu_addr, cpu_data_out, cpu_data_in )
1085 148 davidgb
--  begin
1086
--    cpu_reset_o    <= cpu_reset;
1087
--    cpu_clk_o      <= cpu_clk;
1088
--    cpu_rw_o       <= cpu_rw;
1089
--    cpu_vma_o      <= cpu_vma;
1090
--    cpu_halt_o     <= cpu_halt;
1091
--    cpu_hold_o     <= cpu_hold;
1092
--    cpu_firq_o     <= cpu_firq;
1093
--    cpu_irq_o      <= cpu_irq;
1094
--    cpu_nmi_o      <= cpu_nmi;
1095
--    cpu_addr_o     <= cpu_addr;
1096
--    cpu_data_out_o <= cpu_data_out;
1097
--    cpu_data_in_o  <= cpu_data_in;
1098
--  end process;
1099 141 davidgb
 
1100
end rtl; --===================== End of architecture =======================--
1101
 

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