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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_ZyboZ20/] [system09.ucf] - Blame information for rev 166

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Line No. Rev Author Line
1 165 davidgb
#####################################################
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#
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# XSA-3S1000 Board FPGA pin assignment constraints
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#
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#####################################################
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#
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# Clocks
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#
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# clock pin for Zybo Z7
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 NET "CLKA"   LOC = "K17";
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#
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# Push button switches
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#
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 NET "SW2_N" LOC = "G15";
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 NET "SW3_N" LOC = "P15";
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#
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# Status LED
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#
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 NET "S<0>" LOC = "K18";
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 NET "S<1>" LOC = "P16";
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 NET "S<2>" LOC = "K19";
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 NET "S<3>" LOC = "Y16";
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#
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# PMod JC
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#
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 NET "RS232_RXD" LOC = "V8";
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 NET "RS232_TXD" LOC = "W8";
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#
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# Timing Constraints
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#
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NET "CLKA" TNM_NET="CLKA";
36 166 davidgb
TIMESPEC "TS_clk"=PERIOD "CLKA" 8 ns HIGH 50 %;

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