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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_ZyboZ20/] [system09.vhd] - Blame information for rev 178

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1 165 davidgb
--===========================================================================----
2
--
3
--  S Y N T H E Z I A B L E    System09 - SOC.
4
--
5
--  www.OpenCores.Org - February 2007
6
--  This core adheres to the GNU public license  
7
--
8
-- File name      : System09_Xess_XSA-3S1000.vhd
9
--
10
-- Purpose        : Top level file for 6809 compatible system on a chip
11
--                  Designed with Xilinx XC3S1000 Spartan 3 FPGA.
12
--                  Implemented With XESS XSA-3S1000 FPGA board.
13
--                  *** Note ***
14
--                  This configuration can run Flex9 however it only has
15
--                  32k bytes of user memory and the VDU is monochrome
16
--                  The design needs to be updated to use the SDRAM on 
17
--                  the XSA-3S1000 board.
18
--                  This configuration also lacks a DAT so cannot use
19
--                  the RAM Disk features of SYS09BUG.
20
--
21
-- Dependencies   : ieee.Std_Logic_1164
22
--                  ieee.std_logic_unsigned
23
--                  ieee.std_logic_arith
24
--                  ieee.numeric_std
25
--                  unisim.vcomponents
26
--
27
-- Uses           : mon_rom    (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
28
--                  cpu09      (cpu09.vhd)          CPU core
29
--                  ACIA_6850  (acia6850.vhd)      ACIA / UART
30
--                  ACIA_Clock (ACIA_Clock.vhd)      ACIA clock.
31
--                  timer      (timer.vhd)            Interrupt timer
32
--                  trap       (trap.vhd)             Bus condition trap logic
33
--                  flex_ram   (flex9_ram8k_b16.vhd)  Flex operating system
34
--                  ram_32K    (ram32k_b16.vhd)       32 KBytes of Block RAM
35
--                  
36
-- 
37
-- Author         : John E. Kent      
38
--                  dilbert57@opencores.org      
39
--
40
-- Memory Map     :
41
--
42
-- $0000 - User program RAM (32K Bytes)
43
-- $C000 - Flex Operating System memory (8K Bytes)
44
-- $E000 - ACIA (SWTPc)
45
-- $E010 - Reserved for FD1771 FDC (SWTPc)
46
-- $E050 - Timer
47
-- $E060 - Bus trap
48
-- $E070 - Reserced for Parallel I/O (B5-X300)
49
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
50
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
51
-- $F000 - Sys09Bug monitor Program (4K Bytes)
52
--
53
--===========================================================================----
54
--
55
-- Revision History:
56
--===========================================================================--
57
-- Version 0.1 - 20 March 2003
58
-- Version 0.2 - 30 March 2003
59
-- Version 0.3 - 29 April 2003
60
-- Version 0.4 - 29 June 2003
61
--
62
-- Version 0.5 - 19 July 2003
63
-- prints out "Hello World"
64
--
65
-- Version 0.6 - 5 September 2003
66
-- Runs SBUG
67
--
68
-- Version 1.0- 6 Sep 2003 - John Kent
69
-- Inverted SysClk
70
-- Initial release to Open Cores
71
--
72
-- Version 1.1 - 17 Jan 2004 - John Kent
73
-- Updated miniUart.
74
--
75
-- Version 1.2 - 25 Jan 2004 - John Kent
76
-- removed signals "test_alu" and "test_cc" 
77
-- Trap hardware re-instated.
78
--
79
-- Version 1.3 - 11 Feb 2004 - John Kent
80
-- Designed forked off to produce System09_VDU
81
-- Added VDU component
82
-- VDU runs at 25MHz and divides the clock by 2 for the CPU
83
-- UART Runs at 57.6 Kbps
84
--
85
-- Version 2.0 - 2 September 2004 - John Kent
86
-- ported to Digilent Xilinx Spartan3 starter board
87
-- removed Compact Flash and Trap Logic.
88
-- Replaced SBUG with KBug9s
89
--
90
-- Version 3.0 - 29th August 2006 - John Kent
91
-- Adapted to XSA-3S1000 board.
92
-- Removed DAT and miniUART.
93
-- Used 32KBytes of Block RAM.
94
--
95
-- Version 3.1 - 15th January 2007 - John Kent
96
-- Modified vdu8 interface
97
-- Added a clock divider
98
--
99
-- Version 3.2 - 25th February 2007 - John Kent
100
-- reinstated ACIA_6850 and ACIA_Clock
101
-- Updated VDU8 & Keyboard with generic parameters
102
-- Defined Constants for clock speed calculations
103
--
104
-- Version 3.3 - 1st July 2007 - John Kent
105
-- Made VDU mono to save on one RAMB16
106
-- Used distributed memory for Key Map ROM to save one RAMB16
107
-- Added Flex RAM at $C000 to $DFFF using 4 spare RAMB16s
108
-- Added timer and trap logic
109
-- Added IDE Interface for Compact Flash
110
-- Replaced KBug9s and stack with Sys09Bug.
111
--
112
-- Version 4.0 - 1st February 2008 - John kent
113
-- Replaced Block RAM with SDRAM Interface
114
-- Modified Hold timing for SDRAM
115
-- Added CF and Ethernet interface 
116
-- via the 16 bit peripheral bus at $E100
117
--
118
--===========================================================================--
119
library ieee;
120
   use ieee.std_logic_1164.all;
121
   use IEEE.STD_LOGIC_ARITH.ALL;
122
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
123
   use ieee.numeric_std.all;
124
library work;
125
   use work.common.all;
126
library unisim;
127
   use unisim.vcomponents.all;
128
 
129
entity system09 is
130
  port(
131 178 davidgb
    sysclk         : in  Std_Logic;  -- 125MHz Clock input
132 177 davidgb
    RESET_N      : in  Std_logic;  -- Master Reset input (active low)
133
    NMI_N        : in  Std_logic;  -- Non Maskable Interrupt input (active low)
134 165 davidgb
 
135 177 davidgb
    -- RS232 Port
136
  --RS232_CTS    : in  std_logic;       
137
  --RS232_RTS    : out std_logic;  
138
    RS232_RXD    : in  Std_Logic;  -- RS-232 data in
139
    RS232_TXD    : out Std_Logic   -- RS-232 data out
140 165 davidgb
 
141
-- CPU Debug Interface signals
142
--    cpu_reset_o     : out Std_Logic;
143
--    cpu_clk_o       : out Std_Logic;
144
--    cpu_rw_o        : out std_logic;
145
--    cpu_vma_o       : out std_logic;
146
--    cpu_halt_o      : out std_logic;
147
--    cpu_hold_o      : out std_logic;
148
--    cpu_firq_o      : out std_logic;
149
--    cpu_irq_o       : out std_logic;
150
--    cpu_nmi_o       : out std_logic;
151
--    cpu_addr_o      : out std_logic_vector(15 downto 0);
152
--    cpu_data_in_o   : out std_logic_vector(7 downto 0);
153
--    cpu_data_out_o  : out std_logic_vector(7 downto 0);
154
 
155
  );
156
end system09;
157
 
158
-------------------------------------------------------------------------------
159
-- Architecture for System09
160
-------------------------------------------------------------------------------
161
architecture rtl of system09 is
162
 
163
  -----------------------------------------------------------------------------
164
  -- constants
165
  -----------------------------------------------------------------------------
166 178 davidgb
  constant SYS_CLK_FREQ         : natural := 125_000_000; -- FPGA System Clock (in Hz)
167 165 davidgb
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
168
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
169
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
170
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
171
 
172
  -----------------------------------------------------------------------------
173
  -- Signals
174 177 davidgb
  -----------------------------------------------------------------------------
175
 
176 165 davidgb
  -- BOOT ROM
177
  signal rom_cs         : Std_logic;
178
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
179
 
180
  -- Flex Memory & Monitor Stack
181
  signal flex_cs        : Std_logic;
182
  signal flex_data_out  : Std_Logic_Vector(7 downto 0);
183
 
184
  -- ACIA/UART Interface signals
185
  signal acia_data_out  : Std_Logic_Vector(7 downto 0);
186
  signal acia_cs        : Std_Logic;
187
  signal acia_irq       : Std_Logic;
188
  signal acia_clk       : Std_Logic;
189
  signal rxd            : Std_Logic;
190
  signal txd            : Std_Logic;
191
  signal DCD_n          : Std_Logic;
192
  signal RTS_n          : Std_Logic;
193
  signal CTS_n          : Std_Logic;
194
 
195
  -- RAM
196 177 davidgb
  signal ram1_cs         : std_logic;
197
  signal ram1_data_out   : std_logic_vector(7 downto 0);
198
  signal ram2_cs         : std_logic;
199
  signal ram2_data_out   : std_logic_vector(7 downto 0);
200
  signal ram3_cs         : std_logic;
201 165 davidgb
 
202
  -- CPU Interface signals
203
  signal cpu_reset      : Std_Logic;
204
  signal cpu_clk        : Std_Logic;
205
  signal cpu_rw         : std_logic;
206
  signal cpu_vma        : std_logic;
207
  signal cpu_halt       : std_logic;
208
  signal cpu_hold       : std_logic;
209
  signal cpu_firq       : std_logic;
210
  signal cpu_irq        : std_logic;
211
  signal cpu_nmi        : std_logic;
212
  signal cpu_addr       : std_logic_vector(15 downto 0);
213
  signal cpu_data_in    : std_logic_vector(7 downto 0);
214
  signal cpu_data_out   : std_logic_vector(7 downto 0);
215
 
216
  -- Dynamic Address Translation
217
  signal dat_cs       : std_logic;
218
  signal dat_addr     : std_logic_vector(7 downto 0);
219
 
220
  -- timer
221
  signal timer_data_out : std_logic_vector(7 downto 0);
222
  signal timer_cs       : std_logic;
223
  signal timer_irq      : std_logic;
224
 
225
  -- trap
226
  signal trap_cs        : std_logic;
227
  signal trap_data_out  : std_logic_vector(7 downto 0);
228
  signal trap_irq       : std_logic;
229
 
230
  signal rst_i         : std_logic;     -- internal reset signal
231
  signal clk_i         : std_logic;     -- internal master clock signal
232 177 davidgb
 
233
  signal rs232_cts    :  Std_Logic;
234
  signal rs232_rts    :  Std_Logic;
235 165 davidgb
 
236
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
237
  signal Clk25         : std_logic;
238
 
239
-----------------------------------------------------------------
240
--
241
-- CPU09 CPU core
242
--
243
-----------------------------------------------------------------
244
 
245
component cpu09
246
  port (
247
    clk:      in  std_logic;
248
    rst:      in  std_logic;
249
    vma:      out std_logic;
250
    addr:     out std_logic_vector(15 downto 0);
251
    rw:       out std_logic;     -- Asynchronous memory interface
252
    data_out: out std_logic_vector(7 downto 0);
253
    data_in:  in  std_logic_vector(7 downto 0);
254
    irq:      in  std_logic;
255
    firq:     in  std_logic;
256
    nmi:      in  std_logic;
257
    halt:     in  std_logic;
258
    hold:     in  std_logic
259
  );
260
end component;
261
 
262
----------------------------------------
263
--
264
-- 4K Block RAM Monitor ROM
265
-- $F000 - $FFFF
266
--
267
----------------------------------------
268
 
269
component mon_rom
270
  Port (
271
    clk   : in  std_logic;
272
    rst   : in  std_logic;
273
    cs    : in  std_logic;
274
    rw    : in  std_logic;
275
    addr  : in  std_logic_vector (11 downto 0);
276
    data_out : out std_logic_vector (7 downto 0);
277
    data_in : in  std_logic_vector (7 downto 0)
278
  );
279
end component;
280
 
281
----------------------------------------
282
--
283
-- 8KBytes Block RAM for FLEX9
284
-- $C000 - $DFFF
285
--
286
----------------------------------------
287
 
288
component flex_ram
289
  Port (
290
    clk      : in  std_logic;
291
    rst      : in  std_logic;
292
    cs       : in  std_logic;
293
    rw       : in  std_logic;
294
    addr     : in  std_logic_vector (12 downto 0);
295
    data_out    : out std_logic_vector (7 downto 0);
296
    data_in    : in  std_logic_vector (7 downto 0)
297
  );
298
end component;
299 177 davidgb
 
300
----------------------------------------
301
--
302
-- 32KBytes Block RAM 0000
303
-- $0000 - $7FFF
304
--
305
----------------------------------------
306 165 davidgb
 
307 177 davidgb
component ram_32k
308
  Port (
309
    clk      : in  std_logic;
310
    rst      : in  std_logic;
311
    cs       : in  std_logic;
312
    rw       : in  std_logic;
313
    addr     : in  std_logic_vector (14 downto 0);
314
    data_out    : out std_logic_vector (7 downto 0);
315
    data_in    : in  std_logic_vector (7 downto 0)
316
  );
317
end component;
318
 
319
 
320
----------------------------------------
321
--
322
-- 16KBytes Block RAM 8000
323
-- $8000 - $BFFF
324
--
325
----------------------------------------
326
 
327
component ram_16k
328
  Port (
329
    clk      : in  std_logic;
330
    rst      : in  std_logic;
331
    cs       : in  std_logic;
332
    rw       : in  std_logic;
333
    addr     : in  std_logic_vector (13 downto 0);
334
    data_out    : out std_logic_vector (7 downto 0);
335
    data_in    : in  std_logic_vector (7 downto 0)
336
  );
337
end component;
338
 
339 165 davidgb
-----------------------------------------------------------------
340
--
341
-- 6850 Compatible ACIA / UART
342
--
343
-----------------------------------------------------------------
344
 
345
component acia6850
346
  port (
347
    clk      : in  Std_Logic;  -- System Clock
348
    rst      : in  Std_Logic;  -- Reset input (active high)
349
    cs       : in  Std_Logic;  -- miniUART Chip Select
350
    rw       : in  Std_Logic;  -- Read / Not Write
351
    addr     : in  Std_Logic;  -- Register Select
352
    data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
353
    data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
354
    irq      : out Std_Logic;  -- Interrupt
355
    RxC      : in  Std_Logic;  -- Receive Baud Clock
356
    TxC      : in  Std_Logic;  -- Transmit Baud Clock
357
    RxD      : in  Std_Logic;  -- Receive Data
358
    TxD      : out Std_Logic;  -- Transmit Data
359
    DCD_n    : in  Std_Logic;  -- Data Carrier Detect
360
    CTS_n    : in  Std_Logic;  -- Clear To Send
361
    RTS_n    : out Std_Logic   -- Request To send
362
  );
363
end component;
364
 
365
-----------------------------------------------------------------
366
--
367
-- ACIA Clock divider
368
--
369
-----------------------------------------------------------------
370
 
371
component ACIA_Clock
372
  generic (
373
    SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
374
    ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
375
  );
376
  port (
377
    clk      : in  Std_Logic;  -- System Clock Input
378
    ACIA_clk : out Std_logic   -- ACIA Clock output
379
  );
380
end component;
381
 
382
----------------------------------------
383
--
384
-- Timer module
385
--
386
----------------------------------------
387
 
388
component timer
389
  port (
390
    clk       : in std_logic;
391
    rst       : in std_logic;
392
    cs        : in std_logic;
393
    rw        : in std_logic;
394
    addr      : in std_logic;
395
    data_in   : in std_logic_vector(7 downto 0);
396
    data_out  : out std_logic_vector(7 downto 0);
397
    irq       : out std_logic
398
  );
399
end component;
400
 
401
------------------------------------------------------------
402
--
403
-- Bus Trap logic
404
--
405
------------------------------------------------------------
406
 
407
component trap
408
  port (
409
    clk        : in  std_logic;
410
    rst        : in  std_logic;
411
    cs         : in  std_logic;
412
    rw         : in  std_logic;
413
    vma        : in  std_logic;
414
    addr       : in  std_logic_vector(15 downto 0);
415
    data_in    : in  std_logic_vector(7 downto 0);
416
    data_out   : out std_logic_vector(7 downto 0);
417
    irq        : out std_logic
418
  );
419
end component;
420
 
421
----------------------------------------
422
--
423
-- Dynamic Address Translation Registers
424
--
425
----------------------------------------
426
 
427
component dat_ram
428
  port (
429
    clk      : in  std_logic;
430
    rst      : in  std_logic;
431
    cs       : in  std_logic;
432
    rw       : in  std_logic;
433
    addr_lo  : in  std_logic_vector(3 downto 0);
434
    addr_hi  : in  std_logic_vector(3 downto 0);
435
    data_in  : in  std_logic_vector(7 downto 0);
436
    data_out : out std_logic_vector(7 downto 0)
437
  );
438
end component;
439 177 davidgb
 
440
----------------------------------------
441 165 davidgb
--
442
-- Clock buffer
443
--
444 177 davidgb
----------------------------------------
445 165 davidgb
 
446
component BUFG
447
   Port (
448
     i: in std_logic;
449
     o: out std_logic
450
  );
451
end component;
452
 
453 177 davidgb
begin
454
 
455
  clk_i <= sysclk;
456 165 davidgb
  -----------------------------------------------------------------------------
457
  -- Instantiation of internal components
458
  -----------------------------------------------------------------------------
459
 
460
  my_cpu : cpu09
461
    port map (
462
      clk       => cpu_clk,
463
      rst       => cpu_reset,
464
      vma       => cpu_vma,
465
      addr      => cpu_addr(15 downto 0),
466
      rw        => cpu_rw,
467
      data_out  => cpu_data_out,
468
      data_in   => cpu_data_in,
469
      irq       => cpu_irq,
470
      firq      => cpu_firq,
471
      nmi       => cpu_nmi,
472
      halt      => cpu_halt,
473
      hold      => cpu_hold
474
    );
475
 
476
  my_rom : mon_rom
477
    port map (
478
      clk   => cpu_clk,
479
      rst   => cpu_reset,
480
      cs    => rom_cs,
481
      rw    => '1',
482
      addr  => cpu_addr(11 downto 0),
483
      data_in => cpu_data_out,
484
      data_out => rom_data_out
485
    );
486
 
487
  my_flex : flex_ram
488
    port map (
489
      clk       => cpu_clk,
490
      rst       => cpu_reset,
491
      cs        => flex_cs,
492
      rw        => cpu_rw,
493
      addr      => cpu_addr(12 downto 0),
494
      data_out     => flex_data_out,
495
      data_in     => cpu_data_out
496 177 davidgb
    );
497
 
498
  my_32k : ram_32k
499
    port map (
500
      clk       => cpu_clk,
501
      rst       => cpu_reset,
502
      cs        => ram1_cs,
503
      rw        => cpu_rw,
504
      addr      => cpu_addr(14 downto 0),
505
      data_out     => ram1_data_out,
506
      data_in     => cpu_data_out
507
    );
508
 
509
  my_16k : ram_16k
510
    port map (
511
      clk       => cpu_clk,
512
      rst       => cpu_reset,
513
      cs        => ram2_cs,
514
      rw        => cpu_rw,
515
      addr      => cpu_addr(13 downto 0),
516
      data_out     => ram2_data_out,
517
      data_in     => cpu_data_out
518
    );
519
 
520 165 davidgb
  my_acia  : acia6850
521
    port map (
522
      clk       => cpu_clk,
523
      rst       => cpu_reset,
524
      cs        => acia_cs,
525
      rw        => cpu_rw,
526
      addr      => cpu_addr(0),
527
      data_in   => cpu_data_out,
528
      data_out  => acia_data_out,
529
      irq       => acia_irq,
530
      RxC       => acia_clk,
531
      TxC       => acia_clk,
532
      RxD       => rxd,
533
      TxD       => txd,
534
      DCD_n     => dcd_n,
535
      CTS_n     => cts_n,
536
      RTS_n     => rts_n
537
    );
538
 
539
  my_ACIA_Clock : ACIA_Clock
540
    generic map(
541 177 davidgb
      SYS_CLK_FREQ  => SYS_CLK_FREQ,
542 165 davidgb
      ACIA_CLK_FREQ => ACIA_CLK_FREQ
543
    )
544
    port map(
545
      clk        => Clk_i,
546
      acia_clk   => acia_clk
547
    );
548
 
549
  ----------------------------------------
550
  --
551
  -- Timer Module
552
  --
553
  ----------------------------------------
554
  my_timer  : timer
555
    port map (
556
      clk       => cpu_clk,
557
      rst       => cpu_reset,
558
      cs        => timer_cs,
559
      rw        => cpu_rw,
560
      addr      => cpu_addr(0),
561
      data_in   => cpu_data_out,
562
      data_out  => timer_data_out,
563
      irq       => timer_irq
564
    );
565
 
566
  ----------------------------------------
567
  --
568
  -- Bus Trap Interrupt logic
569
  --
570
  ----------------------------------------
571
  my_trap : trap
572
    port map (
573
      clk        => cpu_clk,
574
      rst        => cpu_reset,
575
      cs         => trap_cs,
576
      rw         => cpu_rw,
577
      vma        => cpu_vma,
578
      addr       => cpu_addr,
579
      data_in    => cpu_data_out,
580
      data_out   => trap_data_out,
581
      irq        => trap_irq
582
    );
583
 
584
  my_dat : dat_ram
585
    port map (
586
      clk       => cpu_clk,
587
      rst       => cpu_reset,
588
      cs        => dat_cs,
589
      rw        => cpu_rw,
590
      addr_hi   => cpu_addr(15 downto 12),
591
      addr_lo   => cpu_addr(3 downto 0),
592
      data_in   => cpu_data_out,
593
      data_out  => dat_addr(7 downto 0)
594
    );
595
 
596
  cpu_clk_buffer : BUFG
597
    port map(
598
      i => Clk25,
599
      o => cpu_clk
600
    );
601
 
602
  ----------------------------------------------------------------------
603
  --
604
  -- Process to decode memory map
605
  --
606
  ----------------------------------------------------------------------
607
 
608
  mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
609
                     dat_addr,
610
                     rom_data_out,
611
                     flex_data_out,
612
                     acia_data_out,
613
                     timer_data_out,
614
                     trap_data_out,
615 177 davidgb
                     ram1_data_out, ram2_data_out
616 165 davidgb
                     )
617
  begin
618
    cpu_data_in <= (others=>'0');
619
    dat_cs      <= '0';
620
    rom_cs      <= '0';
621
    flex_cs     <= '0';
622
    acia_cs     <= '0';
623
    timer_cs    <= '0';
624
    trap_cs     <= '0';
625 177 davidgb
    ram1_cs      <= '0';
626
    ram2_cs      <= '0';
627
 
628 165 davidgb
    if cpu_addr( 15 downto 8 ) = "11111111" then  -- $FFxx
629
      cpu_data_in <= rom_data_out;
630
      dat_cs      <= cpu_vma;              -- write DAT
631
      rom_cs      <= cpu_vma;              -- read  ROM
632
 
633
    --
634
    -- Sys09Bug Monitor ROM $F000 - $FFFF
635
    --
636
    elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
637
      cpu_data_in <= rom_data_out;
638
      rom_cs      <= cpu_vma;
639
 
640
    --
641
    -- IO Devices $E000 - $E7FF
642
    --
643
    elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
644
      case cpu_addr(11 downto 8) is
645
        --
646
        -- SWTPC peripherals from $E000 to $E0FF
647
        --
648
        when "0000" =>
649
          case cpu_addr(7 downto 4) is
650
          --
651
          -- Console Port ACIA $E000 - $E00F
652
          --
653
            when "0000" => -- $E000
654
              cpu_data_in <= acia_data_out;
655
              acia_cs     <= cpu_vma;
656
 
657
            --
658
            -- Reserved
659
            -- Floppy Disk Controller port $E010 - $E01F
660
            --
661
 
662
            --
663
            -- Reserved SWTPc MP-T Timer $E040 - $E04F
664
            --
665
            when "0100" => -- $E040
666
              cpu_data_in <= (others=> '0');
667
 
668
            --
669
            -- Timer $E050 - $E05F
670
            --
671
            when "0101" => -- $E050
672
              cpu_data_in <= timer_data_out;
673
              timer_cs    <= cpu_vma;
674
 
675
            --
676
            -- Bus Trap Logic $E060 - $E06F
677
            --
678
            when "0110" => -- $E060
679
              cpu_data_in <= trap_data_out;
680
              trap_cs     <= cpu_vma;
681
 
682
            --
683
            -- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
684
            --
685
 
686
            --
687
            -- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
688
            --
689
 
690
            --
691
            -- Remaining 6 slots reserved for non SWTPc Peripherals
692
            --
693
            when others => -- $E0A0 to $E0FF
694
              null;
695
          end case;
696
 
697
        --
698
        -- $E200 to $EFFF reserved for future use
699
        --
700
        when others =>
701
           null;
702
      end case;
703
 
704
    --
705
    -- Flex RAM $0C000 - $0DFFF
706
    --
707
    elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
708
      cpu_data_in <= flex_data_out;
709
      flex_cs     <= cpu_vma;
710 177 davidgb
 
711
    --
712
    -- 32k RAM $00000 - $07FFF
713
    --
714
    elsif dat_addr(7 downto 1) = "0000000" then -- $00000 - $07FFF
715
      cpu_data_in <= ram1_data_out;
716
      ram1_cs     <= cpu_vma;
717
 
718
    --
719
    -- 16k RAM $08000 - $0BFFF
720
    --
721
    elsif dat_addr(7 downto 1) = "0000100" then -- $08000 - $0BFFF
722
      cpu_data_in <= ram2_data_out;
723
      ram2_cs     <= cpu_vma;
724 165 davidgb
 
725
    --
726
    -- Everything else is RAM
727
    --
728
    else
729 177 davidgb
      cpu_data_in <= (others => '0');
730
      ram3_cs      <= cpu_vma;
731 165 davidgb
    end if;
732
 
733
  end process;
734
 
735
  --
736
  -- Interrupts and other bus control signals
737
  --
738 177 davidgb
  interrupts : process( NMI_N,
739 165 davidgb
                      acia_irq,
740
                      trap_irq,
741
                      timer_irq
742
                      )
743
  begin
744
    cpu_irq    <= acia_irq;
745 177 davidgb
    cpu_nmi    <= trap_irq or not( NMI_N );
746 165 davidgb
    cpu_firq   <= timer_irq;
747
    cpu_halt   <= '0';
748 177 davidgb
    cpu_hold   <= '0'; -- pb_hold or ram_hold;
749 165 davidgb
  end process;
750
 
751
  --
752
  -- Generate CPU & Pixel Clock from Memory Clock
753
  --
754
  my_prescaler : process( clk_i, clk_count )
755
  begin
756
    if rising_edge( clk_i ) then
757
      if clk_count = 0 then
758
        clk_count <= CPU_CLK_DIV-1;
759
      else
760
        clk_count <= clk_count - 1;
761
      end if;
762
      if clk_count = 0 then
763
         clk25 <= '0';
764
      elsif clk_count = (CPU_CLK_DIV/2) then
765
         clk25 <= '1';
766
      end if;
767
    end if;
768 177 davidgb
  end process;
769 165 davidgb
 
770
  --
771
  -- Reset button and reset timer
772
  --
773 177 davidgb
  my_switch_assignments : process( rst_i, RESET_N)
774 165 davidgb
  begin
775 177 davidgb
    rst_i <= RESET_N;
776 165 davidgb
    cpu_reset <= rst_i;
777
  end process;
778
 
779
  --
780
  -- RS232 signals:
781
  --
782
  my_acia_assignments : process( RS232_RXD, RS232_CTS, txd, rts_n )
783
  begin
784
    rxd       <= RS232_RXD;
785
    cts_n     <= RS232_CTS;
786
    dcd_n     <= '0';
787
    RS232_TXD <= txd;
788
    RS232_RTS <= rts_n;
789
  end process;
790
 
791
--  debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
792
--                      cpu_halt, cpu_hold,
793
--                      cpu_firq, cpu_irq, cpu_nmi,
794
--                      cpu_addr, cpu_data_out, cpu_data_in )
795
--  begin
796
--    cpu_reset_o    <= cpu_reset;
797
--    cpu_clk_o      <= cpu_clk;
798
--    cpu_rw_o       <= cpu_rw;
799
--    cpu_vma_o      <= cpu_vma;
800
--    cpu_halt_o     <= cpu_halt;
801
--    cpu_hold_o     <= cpu_hold;
802
--    cpu_firq_o     <= cpu_firq;
803
--    cpu_irq_o      <= cpu_irq;
804
--    cpu_nmi_o      <= cpu_nmi;
805
--    cpu_addr_o     <= cpu_addr;
806
--    cpu_data_out_o <= cpu_data_out;
807
--    cpu_data_in_o  <= cpu_data_in;
808
--  end process;
809
 
810
end rtl; --===================== End of architecture =======================--
811
 

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