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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_ZyboZ20/] [system09.vhd] - Blame information for rev 208

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1 165 davidgb
--===========================================================================----
2
--
3
--  S Y N T H E Z I A B L E    System09 - SOC.
4
--
5
--  www.OpenCores.Org - February 2007
6
--  This core adheres to the GNU public license  
7
--
8 187 davidgb
-- File name      : system09.vhd
9 165 davidgb
--
10
-- Purpose        : Top level file for 6809 compatible system on a chip
11 187 davidgb
--                  Designed with Digilent Zybo Z20.
12
-- ==========================================================================
13
-- Setup/Buttons
14
--    RS232 - connect a RS-232 Pmod to JE (upper row)
15
--    Configure terminal for 57600 baud 8-N-1, hardware handshake
16
--
17
-- Slide Switches - selects the nibble to display on the 4 LEDs
18
--    0000 - CPU Address 3 to 0
19
--    0001 - CPU Address 7 to 4
20
--    0010 - CPU Address 11 to 8
21
--    0011 - CPU Address 15 to 12
22
--    0100 - CPU Data 3 to 0
23
--    0101 - CPU Data 7 to 4
24
--
25
-- Push buttons
26
--     BTN3     BTN2     BTN1     BTN0
27
--    (unused)  Single   NMI      RESET
28
--              Step
29
--
30
-- Single-Step functionality is controlled by the CLOCK_MODE constant below
31
--
32
-- Memory Map     :
33 165 davidgb
--
34 187 davidgb
-- $0000 - User program RAM (32K Bytes)
35
-- $8000 - User program RAM (16K Bytes)
36
-- $C000 - Flex Operating System memory (8K Bytes)
37
-- $E000 - ACIA (SWTPc)
38
-- $E050 - Timer
39
-- $E060 - Bus trap
40
-- $F000 - Sys09Bug monitor Program (4K Bytes)
41
-- ==========================================================================
42
--
43 165 davidgb
-- Dependencies   : ieee.Std_Logic_1164
44
--                  ieee.std_logic_unsigned
45
--                  ieee.std_logic_arith
46
--                  ieee.numeric_std
47
--                  unisim.vcomponents
48
--
49 187 davidgb
-- Uses           : mon_rom    (sys09swt.vhd)         SWTPc S-Bug 1.7 Monitor ROM 
50
--                  cpu09      (cpu09.vhd)            CPU core
51
--                  ACIA_6850  (acia6850.vhd)         ACIA / UART
52
--                  ACIA_Clock (ACIA_Clock.vhd)       ACIA clock.
53 165 davidgb
--                  timer      (timer.vhd)            Interrupt timer
54
--                  trap       (trap.vhd)             Bus condition trap logic
55 187 davidgb
--                  flex_ram   (flex9ram.vhd)         Flex operating system
56
--                  ram_16K    (ram16k_b16.vhd)       32 KBytes of Block RAM
57 165 davidgb
--                  ram_32K    (ram32k_b16.vhd)       32 KBytes of Block RAM
58
--                  
59
--===========================================================================----
60
--
61
-- Revision History:
62
--===========================================================================--
63 187 davidgb
-- Version 0.1 - Jan 20, 2021
64
--    Copied from the System09_Xess-XSA3S1000 vhdl
65 165 davidgb
--===========================================================================--
66
library ieee;
67
   use ieee.std_logic_1164.all;
68
   use IEEE.STD_LOGIC_ARITH.ALL;
69
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
70
   use ieee.numeric_std.all;
71
library work;
72
   use work.common.all;
73
library unisim;
74
   use unisim.vcomponents.all;
75
 
76
entity system09 is
77
  port(
78 187 davidgb
    CLKA         : in  Std_Logic;  -- 125 MHz Clock input
79 165 davidgb
 
80 193 davidgb
    -- RS232 Port - via Pmod RS232
81 199 davidgb
    RS232_CTS    : in  Std_Logic;
82
    RS232_RTS    : out Std_Logic;
83 187 davidgb
    RS232_RXD    : in  Std_Logic;
84
    RS232_TXD    : out Std_Logic;
85 200 davidgb
 
86
--      TMDS_Clk_p : out std_logic;
87
--      TMDS_Clk_n : out std_logic;
88
--      TMDS_Data_p : out std_logic_vector(2 downto 0);
89
--      TMDS_Data_n : out std_logic_vector(2 downto 0);
90
 
91 202 davidgb
    -- CRTC output signals
92
    VGA_vsync_n  : out Std_Logic;
93
    VGA_hsync_n  : out Std_Logic;
94
    VGA_blue     : out std_logic_vector(3 downto 0);
95
    VGA_green    : out std_logic_vector(3 downto 0);
96
    VGA_red      : out std_logic_vector(3 downto 0);
97 200 davidgb
 
98 187 davidgb
    -- slide switches
99
         sw           : in std_logic_vector(3 downto 0);
100
         -- push buttons [Unused, Single-Step, NMI, RESET]
101
         btn          : in std_logic_vector(3 downto 0);
102
    -- Status 4 LEDs
103
    led          : out std_logic_vector(3 downto 0)
104 165 davidgb
  );
105
end system09;
106
 
107
-------------------------------------------------------------------------------
108
-- Architecture for System09
109
-------------------------------------------------------------------------------
110
architecture rtl of system09 is
111
 
112
  -----------------------------------------------------------------------------
113
  -- constants
114
  -----------------------------------------------------------------------------
115 187 davidgb
  constant CLOCK_MODE           : natural := 0; -- 0 means normal, 1 means single-step
116
 
117
  constant SYS_CLK_FREQ         : natural := 125_000_000;  -- FPGA System Clock (in Hz)
118 165 davidgb
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
119 200 davidgb
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
120
  constant VGA_CLK_FREQ         : natural := 25_000_000;  -- VGA Pixel Clock
121 202 davidgb
  constant VGA_CLK_DIV          : natural := (SYS_CLK_FREQ/VGA_CLK_FREQ);
122 165 davidgb
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
123
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
124
 
125
  -----------------------------------------------------------------------------
126
  -- Signals
127 177 davidgb
  -----------------------------------------------------------------------------
128 187 davidgb
  signal pbtn           : std_logic_vector(3 downto 0);
129 193 davidgb
  signal NMI            : std_logic;
130
  signal RESET          : std_logic;
131 187 davidgb
  signal SINGLE_STEP    : std_logic;
132
 
133 165 davidgb
  -- BOOT ROM
134
  signal rom_cs         : Std_logic;
135
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
136
 
137
  -- Flex Memory & Monitor Stack
138
  signal flex_cs        : Std_logic;
139
  signal flex_data_out  : Std_Logic_Vector(7 downto 0);
140
 
141
  -- ACIA/UART Interface signals
142
  signal acia_data_out  : Std_Logic_Vector(7 downto 0);
143
  signal acia_cs        : Std_Logic;
144
  signal acia_irq       : Std_Logic;
145
  signal acia_clk       : Std_Logic;
146 193 davidgb
  signal RXD            : Std_Logic;
147
  signal TXD            : Std_Logic;
148 165 davidgb
  signal DCD_n          : Std_Logic;
149
  signal RTS_n          : Std_Logic;
150
  signal CTS_n          : Std_Logic;
151
 
152
  -- RAM
153 177 davidgb
  signal ram1_cs         : std_logic;
154
  signal ram1_data_out   : std_logic_vector(7 downto 0);
155
  signal ram2_cs         : std_logic;
156
  signal ram2_data_out   : std_logic_vector(7 downto 0);
157
  signal ram3_cs         : std_logic;
158 165 davidgb
 
159
  -- CPU Interface signals
160
  signal cpu_reset      : Std_Logic;
161
  signal cpu_clk        : Std_Logic;
162
  signal cpu_rw         : std_logic;
163
  signal cpu_vma        : std_logic;
164
  signal cpu_halt       : std_logic;
165
  signal cpu_hold       : std_logic;
166
  signal cpu_firq       : std_logic;
167
  signal cpu_irq        : std_logic;
168
  signal cpu_nmi        : std_logic;
169
  signal cpu_addr       : std_logic_vector(15 downto 0);
170
  signal cpu_data_in    : std_logic_vector(7 downto 0);
171
  signal cpu_data_out   : std_logic_vector(7 downto 0);
172
 
173
  -- Dynamic Address Translation
174
  signal dat_cs       : std_logic;
175
  signal dat_addr     : std_logic_vector(7 downto 0);
176 200 davidgb
 
177 202 davidgb
  -- Video Display Unit
178 200 davidgb
  signal vdu_cs         : std_logic;
179
  signal vdu_data_out   : std_logic_vector(7 downto 0);
180
  signal vga_red_o      : std_logic;
181
  signal vga_green_o    : std_logic;
182
  signal vga_blue_o     : std_logic;
183 202 davidgb
 
184 200 davidgb
  signal serial_clk_unused : std_logic;
185 165 davidgb
  -- timer
186
  signal timer_data_out : std_logic_vector(7 downto 0);
187
  signal timer_cs       : std_logic;
188
  signal timer_irq      : std_logic;
189
 
190
  -- trap
191
  signal trap_cs        : std_logic;
192
  signal trap_data_out  : std_logic_vector(7 downto 0);
193
  signal trap_irq       : std_logic;
194
 
195
  signal rst_i         : std_logic;     -- internal reset signal
196 187 davidgb
  signal clk_i         : std_logic;     -- internal master clock signal
197 165 davidgb
 
198 196 davidgb
  signal CountL        : std_logic_vector(25 downto 0);
199 165 davidgb
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
200 200 davidgb
  signal Clk25         : std_logic;
201
  signal vga_clk       : std_logic;
202 187 davidgb
 
203
component btn_debounce
204
    Port ( BTN_I : in  STD_LOGIC_VECTOR (3 downto 0);
205
           CLK : in  STD_LOGIC;
206
           BTN_O : out  STD_LOGIC_VECTOR (3 downto 0));
207
end component;
208
 
209 165 davidgb
 
210
-----------------------------------------------------------------
211
--
212
-- CPU09 CPU core
213
--
214
-----------------------------------------------------------------
215
 
216
component cpu09
217
  port (
218
    clk:      in  std_logic;
219
    rst:      in  std_logic;
220
    vma:      out std_logic;
221
    addr:     out std_logic_vector(15 downto 0);
222
    rw:       out std_logic;     -- Asynchronous memory interface
223
    data_out: out std_logic_vector(7 downto 0);
224
    data_in:  in  std_logic_vector(7 downto 0);
225
    irq:      in  std_logic;
226
    firq:     in  std_logic;
227
    nmi:      in  std_logic;
228
    halt:     in  std_logic;
229
    hold:     in  std_logic
230
  );
231
end component;
232
 
233
----------------------------------------
234
--
235
-- 4K Block RAM Monitor ROM
236
-- $F000 - $FFFF
237
--
238
----------------------------------------
239
 
240
component mon_rom
241
  Port (
242
    clk   : in  std_logic;
243
    rst   : in  std_logic;
244
    cs    : in  std_logic;
245
    rw    : in  std_logic;
246
    addr  : in  std_logic_vector (11 downto 0);
247
    data_out : out std_logic_vector (7 downto 0);
248
    data_in : in  std_logic_vector (7 downto 0)
249
  );
250
end component;
251
 
252
----------------------------------------
253
--
254
-- 8KBytes Block RAM for FLEX9
255
-- $C000 - $DFFF
256
--
257
----------------------------------------
258
 
259
component flex_ram
260
  Port (
261
    clk      : in  std_logic;
262
    rst      : in  std_logic;
263
    cs       : in  std_logic;
264
    rw       : in  std_logic;
265
    addr     : in  std_logic_vector (12 downto 0);
266
    data_out    : out std_logic_vector (7 downto 0);
267
    data_in    : in  std_logic_vector (7 downto 0)
268
  );
269
end component;
270 177 davidgb
 
271
----------------------------------------
272
--
273 208 davidgb
-- Parameterized Block RAM
274
--
275
----------------------------------------
276
 
277
  component block_spram
278
    generic (
279
      dwidth : integer := 8;     -- parameterized data width
280
           awidth : integer := 16     -- parameterized address width
281
         );
282
         port (
283
      clk         : in std_logic;
284
           cs          : in std_logic; -- chip-select/enable
285
           addr        : in std_logic_vector(awidth-1 downto 0);
286
           rw          : in std_logic;
287
           data_in     : in std_logic_vector(dwidth-1 downto 0);
288
           data_out    : out std_logic_vector(dwidth-1 downto 0)
289
         );
290
  end component;
291
 
292
----------------------------------------
293
--
294 177 davidgb
-- 32KBytes Block RAM 0000
295
-- $0000 - $7FFF
296
--
297
----------------------------------------
298 165 davidgb
 
299 177 davidgb
component ram_32k
300
  Port (
301
    clk      : in  std_logic;
302
    rst      : in  std_logic;
303
    cs       : in  std_logic;
304
    rw       : in  std_logic;
305
    addr     : in  std_logic_vector (14 downto 0);
306
    data_out    : out std_logic_vector (7 downto 0);
307
    data_in    : in  std_logic_vector (7 downto 0)
308
  );
309
end component;
310
 
311
 
312
----------------------------------------
313
--
314
-- 16KBytes Block RAM 8000
315
-- $8000 - $BFFF
316
--
317
----------------------------------------
318
 
319
component ram_16k
320
  Port (
321
    clk      : in  std_logic;
322
    rst      : in  std_logic;
323
    cs       : in  std_logic;
324
    rw       : in  std_logic;
325
    addr     : in  std_logic_vector (13 downto 0);
326
    data_out    : out std_logic_vector (7 downto 0);
327
    data_in    : in  std_logic_vector (7 downto 0)
328
  );
329
end component;
330
 
331 165 davidgb
-----------------------------------------------------------------
332
--
333
-- 6850 Compatible ACIA / UART
334
--
335
-----------------------------------------------------------------
336
 
337
component acia6850
338
  port (
339
    clk      : in  Std_Logic;  -- System Clock
340
    rst      : in  Std_Logic;  -- Reset input (active high)
341
    cs       : in  Std_Logic;  -- miniUART Chip Select
342
    rw       : in  Std_Logic;  -- Read / Not Write
343
    addr     : in  Std_Logic;  -- Register Select
344
    data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
345
    data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
346
    irq      : out Std_Logic;  -- Interrupt
347
    RxC      : in  Std_Logic;  -- Receive Baud Clock
348
    TxC      : in  Std_Logic;  -- Transmit Baud Clock
349
    RxD      : in  Std_Logic;  -- Receive Data
350
    TxD      : out Std_Logic;  -- Transmit Data
351
    DCD_n    : in  Std_Logic;  -- Data Carrier Detect
352
    CTS_n    : in  Std_Logic;  -- Clear To Send
353
    RTS_n    : out Std_Logic   -- Request To send
354
  );
355
end component;
356
 
357
-----------------------------------------------------------------
358
--
359
-- ACIA Clock divider
360
--
361
-----------------------------------------------------------------
362
 
363
component ACIA_Clock
364
  generic (
365
    SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
366
    ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
367
  );
368
  port (
369
    clk      : in  Std_Logic;  -- System Clock Input
370
    ACIA_clk : out Std_logic   -- ACIA Clock output
371
  );
372
end component;
373 200 davidgb
 
374
 
375
----------------------------------------
376
--
377
-- Video Display Unit.
378
--
379
----------------------------------------
380 165 davidgb
 
381 200 davidgb
component vdu8
382
  generic(
383
    VDU_CLK_FREQ           : integer := CPU_CLK_FREQ; -- HZ
384
    VGA_CLK_FREQ           : integer := VGA_CLK_FREQ; -- HZ
385
    VGA_HOR_CHARS          : integer := 80; -- CHARACTERS
386
    VGA_VER_CHARS          : integer := 25; -- CHARACTERS
387
    VGA_PIX_PER_CHAR       : integer := 8;  -- PIXELS
388
    VGA_LIN_PER_CHAR       : integer := 16; -- LINES
389
    VGA_HOR_BACK_PORCH     : integer := 40; -- PIXELS
390
    VGA_HOR_SYNC           : integer := 96; -- PIXELS
391
    VGA_HOR_FRONT_PORCH    : integer := 24; -- PIXELS
392
    VGA_VER_BACK_PORCH     : integer := 13; -- LINES
393
    VGA_VER_SYNC           : integer := 2;  -- LINES
394
    VGA_VER_FRONT_PORCH    : integer := 35  -- LINES
395
  );
396
  port(
397
    -- control register interface
398
    vdu_clk      : in  std_logic;  -- CPU Clock - 25MHz
399
    vdu_rst      : in  std_logic;
400
    vdu_cs       : in  std_logic;
401
    vdu_rw       : in  std_logic;
402
    vdu_addr     : in  std_logic_vector(2 downto 0);
403
    vdu_data_in  : in  std_logic_vector(7 downto 0);
404
    vdu_data_out : out std_logic_vector(7 downto 0);
405
 
406
    -- vga port connections
407
    vga_clk      : in  std_logic; -- VGA Pixel Clock - 25 MHz
408
    vga_red_o    : out std_logic;
409
    vga_green_o  : out std_logic;
410 202 davidgb
    vga_blue_o   : out std_logic;
411 200 davidgb
    vga_hsync_o  : out std_logic;
412
    vga_vsync_o  : out std_logic
413
  );
414
end component;
415
 
416
 
417 165 davidgb
----------------------------------------
418
--
419
-- Timer module
420
--
421
----------------------------------------
422
 
423
component timer
424
  port (
425
    clk       : in std_logic;
426
    rst       : in std_logic;
427
    cs        : in std_logic;
428
    rw        : in std_logic;
429
    addr      : in std_logic;
430
    data_in   : in std_logic_vector(7 downto 0);
431
    data_out  : out std_logic_vector(7 downto 0);
432
    irq       : out std_logic
433
  );
434
end component;
435
 
436
------------------------------------------------------------
437
--
438
-- Bus Trap logic
439
--
440
------------------------------------------------------------
441
 
442
component trap
443
  port (
444
    clk        : in  std_logic;
445
    rst        : in  std_logic;
446
    cs         : in  std_logic;
447
    rw         : in  std_logic;
448
    vma        : in  std_logic;
449
    addr       : in  std_logic_vector(15 downto 0);
450
    data_in    : in  std_logic_vector(7 downto 0);
451
    data_out   : out std_logic_vector(7 downto 0);
452
    irq        : out std_logic
453
  );
454
end component;
455
 
456
----------------------------------------
457
--
458
-- Dynamic Address Translation Registers
459
--
460
----------------------------------------
461
 
462
component dat_ram
463
  port (
464
    clk      : in  std_logic;
465
    rst      : in  std_logic;
466
    cs       : in  std_logic;
467
    rw       : in  std_logic;
468
    addr_lo  : in  std_logic_vector(3 downto 0);
469
    addr_hi  : in  std_logic_vector(3 downto 0);
470
    data_in  : in  std_logic_vector(7 downto 0);
471
    data_out : out std_logic_vector(7 downto 0)
472
  );
473
end component;
474 187 davidgb
 
475 165 davidgb
--
476
-- Clock buffer
477
--
478
 
479
component BUFG
480
   Port (
481
     i: in std_logic;
482
     o: out std_logic
483
  );
484
end component;
485
 
486 187 davidgb
begin
487 177 davidgb
 
488 187 davidgb
  --
489
  -- pushbutton debounce
490
  --
491
  my_singlestep: btn_debounce
492
    port map ( BTN_I => btn, CLK => CLKA, BTN_O => pbtn);
493
 
494 193 davidgb
  RESET      <= pbtn(0); -- Right PB
495
  NMI        <= pbtn(1); -- Center PB
496 187 davidgb
 
497
  --
498
  -- Generate CPU & Pixel Clock from Memory Clock
499
  --
500 196 davidgb
 
501
  my_prescaler : process( clk_i, clk_count )
502
  begin
503
    if rising_edge( clk_i ) then
504
      if clk_count = 0 then
505
        clk_count <= CPU_CLK_DIV-1;
506
      else
507
        clk_count <= clk_count - 1;
508 187 davidgb
      end if;
509 196 davidgb
      if clk_count = 0 then
510
         clk25 <= '0';
511
      elsif clk_count = (CPU_CLK_DIV/2) then
512
         clk25 <= '1';
513
      end if;
514
    end if;
515
  end process;
516 187 davidgb
 
517
  --
518
  -- Reset button and reset timer
519
  --
520 193 davidgb
  my_switch_assignments : process( rst_i, RESET)
521 187 davidgb
  begin
522 193 davidgb
    rst_i <= RESET;
523 187 davidgb
    cpu_reset <= rst_i;
524
  end process;
525
 
526
  clk_i <= CLKA;
527
 
528 165 davidgb
  -----------------------------------------------------------------------------
529
  -- Instantiation of internal components
530
  -----------------------------------------------------------------------------
531
 
532
  my_cpu : cpu09
533
    port map (
534
      clk       => cpu_clk,
535
      rst       => cpu_reset,
536
      vma       => cpu_vma,
537
      addr      => cpu_addr(15 downto 0),
538
      rw        => cpu_rw,
539
      data_out  => cpu_data_out,
540
      data_in   => cpu_data_in,
541
      irq       => cpu_irq,
542
      firq      => cpu_firq,
543
      nmi       => cpu_nmi,
544
      halt      => cpu_halt,
545
      hold      => cpu_hold
546
    );
547
 
548
  my_rom : mon_rom
549
    port map (
550
      clk   => cpu_clk,
551
      rst   => cpu_reset,
552
      cs    => rom_cs,
553
      rw    => '1',
554
      addr  => cpu_addr(11 downto 0),
555
      data_in => cpu_data_out,
556
      data_out => rom_data_out
557
    );
558
 
559
  my_flex : flex_ram
560
    port map (
561
      clk       => cpu_clk,
562
      rst       => cpu_reset,
563
      cs        => flex_cs,
564
      rw        => cpu_rw,
565
      addr      => cpu_addr(12 downto 0),
566
      data_out     => flex_data_out,
567
      data_in     => cpu_data_out
568 177 davidgb
    );
569
 
570 208 davidgb
  my_32k : block_spram
571
    generic map (dwidth => 8, awidth => 15)
572 177 davidgb
    port map (
573
      clk       => cpu_clk,
574 208 davidgb
      --rst       => cpu_reset,
575 177 davidgb
      cs        => ram1_cs,
576
      rw        => cpu_rw,
577
      addr      => cpu_addr(14 downto 0),
578
      data_out     => ram1_data_out,
579
      data_in     => cpu_data_out
580
    );
581
 
582 208 davidgb
  my_16k : block_spram
583
    generic map (dwidth => 8, awidth => 14)
584 177 davidgb
    port map (
585
      clk       => cpu_clk,
586 208 davidgb
      --rst       => cpu_reset,
587 177 davidgb
      cs        => ram2_cs,
588
      rw        => cpu_rw,
589
      addr      => cpu_addr(13 downto 0),
590
      data_out     => ram2_data_out,
591
      data_in     => cpu_data_out
592
    );
593
 
594 165 davidgb
  my_acia  : acia6850
595
    port map (
596
      clk       => cpu_clk,
597
      rst       => cpu_reset,
598
      cs        => acia_cs,
599
      rw        => cpu_rw,
600
      addr      => cpu_addr(0),
601
      data_in   => cpu_data_out,
602
      data_out  => acia_data_out,
603
      irq       => acia_irq,
604
      RxC       => acia_clk,
605
      TxC       => acia_clk,
606 193 davidgb
      RxD       => RXD,
607
      TxD       => TXD,
608
      DCD_n     => DCD_n,
609
      CTS_n     => CTS_n,
610
      RTS_n     => RTS_n
611
    );
612
 
613
  --
614
  -- RS232 signals:
615
  --
616 199 davidgb
  my_acia_assignments : process( RS232_RXD, RS232_CTS,
617 196 davidgb
                                 TXD, RTS_n )
618 193 davidgb
  begin
619
    RXD       <= RS232_RXD;
620 199 davidgb
    CTS_n     <= RS232_CTS;
621 193 davidgb
    DCD_n     <= '0';
622
    RS232_TXD <= TXD;
623 199 davidgb
    RS232_RTS <= RTS_n;
624 193 davidgb
  end process;
625 187 davidgb
 
626 165 davidgb
  my_ACIA_Clock : ACIA_Clock
627
    generic map(
628 187 davidgb
      SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
629 165 davidgb
      ACIA_CLK_FREQ => ACIA_CLK_FREQ
630
    )
631
    port map(
632 193 davidgb
      clk        => clk_i,
633 165 davidgb
      acia_clk   => acia_clk
634
    );
635 200 davidgb
 
636
  ----------------------------------------
637
  --
638
  -- Video Display Unit instantiation
639
  --
640
  ----------------------------------------
641
  my_vdu : vdu8
642
    generic map(
643
      VDU_CLK_FREQ           => CPU_CLK_FREQ, -- HZ
644
      VGA_CLK_FREQ           => VGA_CLK_FREQ, -- HZ
645
      VGA_HOR_CHARS          => 80, -- CHARACTERS
646
      VGA_VER_CHARS          => 25, -- CHARACTERS
647
      VGA_PIX_PER_CHAR       => 8,  -- PIXELS
648
      VGA_LIN_PER_CHAR       => 16, -- LINES
649
      VGA_HOR_BACK_PORCH     => 40, -- PIXELS
650
      VGA_HOR_SYNC           => 96, -- PIXELS
651
      VGA_HOR_FRONT_PORCH    => 24, -- PIXELS
652
      VGA_VER_BACK_PORCH     => 13, -- LINES
653
      VGA_VER_SYNC           => 2,  -- LINES
654
      VGA_VER_FRONT_PORCH    => 35  -- LINES
655
    )
656
    port map(
657
      -- Control Registers
658
      vdu_clk       => cpu_clk,               -- 12.5 MHz System Clock in
659
      vdu_rst       => cpu_reset,
660
      vdu_cs        => vdu_cs,
661
      vdu_rw        => cpu_rw,
662
      vdu_addr      => cpu_addr(2 downto 0),
663
      vdu_data_in   => cpu_data_out,
664
      vdu_data_out  => vdu_data_out,
665
      -- vga port connections
666
      vga_clk       => vga_clk,               -- 25 MHz VDU pixel clock
667 202 davidgb
      vga_red_o     => vga_red_o,
668
      vga_green_o   => vga_green_o,
669
      vga_blue_o    => vga_blue_o,
670
      vga_hsync_o   => VGA_hsync_n,
671
      vga_vsync_o   => VGA_vsync_n
672 200 davidgb
   );
673 202 davidgb
  --
674
  -- VGA ouputs
675
  --
676
  my_vga_assignments : process( vga_red_o, vga_green_o, vga_blue_o )
677
  begin
678
    VGA_red(0)   <= vga_red_o;
679
    VGA_red(1)   <= vga_red_o;
680
    VGA_red(2)   <= vga_red_o;
681
    VGA_red(3)   <= vga_red_o;
682
    VGA_green(0) <= vga_green_o;
683
    VGA_green(1) <= vga_green_o;
684
    VGA_green(2) <= vga_green_o;
685
    VGA_green(3) <= vga_green_o;
686
    VGA_blue(0)  <= vga_blue_o;
687
    VGA_blue(1)  <= vga_blue_o;
688
    VGA_blue(2)  <= vga_blue_o;
689
    VGA_blue(3)  <= vga_blue_o;
690
  end process;
691
 
692 165 davidgb
 
693
  ----------------------------------------
694
  --
695
  -- Timer Module
696
  --
697
  ----------------------------------------
698
  my_timer  : timer
699
    port map (
700
      clk       => cpu_clk,
701
      rst       => cpu_reset,
702
      cs        => timer_cs,
703
      rw        => cpu_rw,
704
      addr      => cpu_addr(0),
705
      data_in   => cpu_data_out,
706
      data_out  => timer_data_out,
707
      irq       => timer_irq
708
    );
709
 
710
  ----------------------------------------
711
  --
712
  -- Bus Trap Interrupt logic
713
  --
714
  ----------------------------------------
715
  my_trap : trap
716
    port map (
717
      clk        => cpu_clk,
718
      rst        => cpu_reset,
719
      cs         => trap_cs,
720
      rw         => cpu_rw,
721
      vma        => cpu_vma,
722
      addr       => cpu_addr,
723
      data_in    => cpu_data_out,
724
      data_out   => trap_data_out,
725
      irq        => trap_irq
726
    );
727
 
728
  my_dat : dat_ram
729
    port map (
730
      clk       => cpu_clk,
731
      rst       => cpu_reset,
732
      cs        => dat_cs,
733
      rw        => cpu_rw,
734
      addr_hi   => cpu_addr(15 downto 12),
735
      addr_lo   => cpu_addr(3 downto 0),
736
      data_in   => cpu_data_out,
737
      data_out  => dat_addr(7 downto 0)
738
    );
739
 
740
  cpu_clk_buffer : BUFG
741
    port map(
742
      i => Clk25,
743
      o => cpu_clk
744
    );
745 202 davidgb
  vga_clk_buffer : BUFG
746
    port map(
747
      i => Clk25,
748
      o => vga_clk
749
    );
750 165 davidgb
  ----------------------------------------------------------------------
751
  --
752
  -- Process to decode memory map
753
  --
754
  ----------------------------------------------------------------------
755
 
756
  mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
757
                     dat_addr,
758
                     rom_data_out,
759
                     flex_data_out,
760
                     acia_data_out,
761 200 davidgb
                     vdu_data_out,
762 165 davidgb
                     timer_data_out,
763
                     trap_data_out,
764 177 davidgb
                     ram1_data_out, ram2_data_out
765 165 davidgb
                     )
766
  begin
767
    cpu_data_in <= (others=>'0');
768
    dat_cs      <= '0';
769
    rom_cs      <= '0';
770
    flex_cs     <= '0';
771 200 davidgb
    acia_cs     <= '0';
772
    vdu_cs      <= '0';
773 165 davidgb
    timer_cs    <= '0';
774
    trap_cs     <= '0';
775 177 davidgb
    ram1_cs      <= '0';
776
    ram2_cs      <= '0';
777
 
778 165 davidgb
    if cpu_addr( 15 downto 8 ) = "11111111" then  -- $FFxx
779
      cpu_data_in <= rom_data_out;
780
      dat_cs      <= cpu_vma;              -- write DAT
781
      rom_cs      <= cpu_vma;              -- read  ROM
782
 
783
    --
784
    -- Sys09Bug Monitor ROM $F000 - $FFFF
785
    --
786
    elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
787
      cpu_data_in <= rom_data_out;
788
      rom_cs      <= cpu_vma;
789
 
790
    --
791
    -- IO Devices $E000 - $E7FF
792
    --
793
    elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
794
      case cpu_addr(11 downto 8) is
795
        --
796
        -- SWTPC peripherals from $E000 to $E0FF
797
        --
798
        when "0000" =>
799
          case cpu_addr(7 downto 4) is
800
          --
801
          -- Console Port ACIA $E000 - $E00F
802
          --
803
            when "0000" => -- $E000
804
              cpu_data_in <= acia_data_out;
805
              acia_cs     <= cpu_vma;
806
 
807
            --
808
            -- Reserved
809
            -- Floppy Disk Controller port $E010 - $E01F
810
            --
811
            --
812 200 davidgb
            -- VDU port $E030 - $E03F
813
            --
814
            when "0011" => -- $E030
815
              cpu_data_in <= vdu_data_out;
816
              vdu_cs      <= cpu_vma;
817
 
818
            --
819 165 davidgb
            -- Reserved SWTPc MP-T Timer $E040 - $E04F
820
            --
821
            when "0100" => -- $E040
822
              cpu_data_in <= (others=> '0');
823
 
824
            --
825
            -- Timer $E050 - $E05F
826
            --
827
            when "0101" => -- $E050
828
              cpu_data_in <= timer_data_out;
829
              timer_cs    <= cpu_vma;
830
 
831
            --
832
            -- Bus Trap Logic $E060 - $E06F
833
            --
834
            when "0110" => -- $E060
835
              cpu_data_in <= trap_data_out;
836
              trap_cs     <= cpu_vma;
837
 
838
            --
839
            -- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
840
            --
841
 
842
            --
843
            -- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
844
            --
845
 
846
            --
847
            -- Remaining 6 slots reserved for non SWTPc Peripherals
848
            --
849
            when others => -- $E0A0 to $E0FF
850
              null;
851
          end case;
852
 
853
        --
854
        -- $E200 to $EFFF reserved for future use
855
        --
856
        when others =>
857
           null;
858
      end case;
859 177 davidgb
 
860
    --
861 193 davidgb
    -- Block RAM (32k) $00000 - $07FFF
862 177 davidgb
    --
863 193 davidgb
    elsif dat_addr(7 downto 3) = "00000"   then -- $00000 - $07FFF
864 177 davidgb
      cpu_data_in <= ram1_data_out;
865
      ram1_cs     <= cpu_vma;
866
 
867
    --
868 193 davidgb
    -- Block RAM (16k) $08000 - $0BFFF
869 177 davidgb
    --
870 193 davidgb
    elsif dat_addr(7 downto 2) = "000010"  then -- $08000 - $0BFFF
871 177 davidgb
      cpu_data_in <= ram2_data_out;
872
      ram2_cs     <= cpu_vma;
873 165 davidgb
 
874
    --
875 193 davidgb
    -- Flex RAM (8k) $0C000 - $0DFFF
876
    --
877
    elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
878
      cpu_data_in <= flex_data_out;
879
      flex_cs     <= cpu_vma;
880
 
881
    --
882 165 davidgb
    -- Everything else is RAM
883
    --
884
    else
885 177 davidgb
      cpu_data_in <= (others => '0');
886
      ram3_cs      <= cpu_vma;
887 165 davidgb
    end if;
888
 
889
  end process;
890
 
891
  --
892
  -- Interrupts and other bus control signals
893
  --
894 193 davidgb
  interrupts : process( NMI,
895 165 davidgb
                      acia_irq,
896
                      trap_irq,
897
                      timer_irq
898
                      )
899
  begin
900
    cpu_irq    <= acia_irq;
901 193 davidgb
    cpu_nmi    <= trap_irq or NMI;
902 165 davidgb
    cpu_firq   <= timer_irq;
903
    cpu_halt   <= '0';
904 177 davidgb
    cpu_hold   <= '0'; -- pb_hold or ram_hold;
905 165 davidgb
  end process;
906
 
907
  --
908 187 davidgb
  -- Flash 7 segment LEDS
909 165 davidgb
  --
910 187 davidgb
  my_led_flasher: process( clk_i, rst_i, CountL )
911 165 davidgb
  begin
912 187 davidgb
    if rst_i = '1' then
913 196 davidgb
         CountL <= "00000000000000000000000000";
914 187 davidgb
    elsif rising_edge(clk_i) then
915
         CountL <= CountL + 1;
916 165 davidgb
    end if;
917 187 davidgb
    --S(7 downto 0) <= CountL(23 downto 16);
918 165 davidgb
  end process;
919
 
920 193 davidgb
  status_leds : process( rst_i, cpu_reset, cpu_addr, cpu_data_in, sw)
921 187 davidgb
  begin
922
    case sw is
923 196 davidgb
         when "1000" =>
924 187 davidgb
           led(3 downto 0) <= cpu_addr(3 downto 0);
925 196 davidgb
    when "1001" =>
926 187 davidgb
           led(3 downto 0) <= cpu_addr(7 downto 4);
927 196 davidgb
         when "1010" =>
928 187 davidgb
           led(3 downto 0) <= cpu_addr(11 downto 8);
929 196 davidgb
    when "1011" =>
930 187 davidgb
           led(3 downto 0) <= cpu_addr(15 downto 12);
931 196 davidgb
    when "1100" =>
932 187 davidgb
           led(3 downto 0) <= cpu_data_in(3 downto 0);
933 196 davidgb
    when "1101" =>
934
           led(3 downto 0) <= cpu_data_in(7 downto 4);
935
    when "0000" =>
936
           led(3) <= '0';
937
      led(2) <= CountL(24);
938
                led(1) <= cpu_reset;
939
                led(0) <= NMI;
940 187 davidgb
    when others => led(3 downto 0) <= (others => '0');
941
         end case;
942 165 davidgb
  end process;
943
 
944
--  debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
945
--                      cpu_halt, cpu_hold,
946
--                      cpu_firq, cpu_irq, cpu_nmi,
947
--                      cpu_addr, cpu_data_out, cpu_data_in )
948
--  begin
949
--    cpu_reset_o    <= cpu_reset;
950
--    cpu_clk_o      <= cpu_clk;
951
--    cpu_rw_o       <= cpu_rw;
952
--    cpu_vma_o      <= cpu_vma;
953
--    cpu_halt_o     <= cpu_halt;
954
--    cpu_hold_o     <= cpu_hold;
955
--    cpu_firq_o     <= cpu_firq;
956
--    cpu_irq_o      <= cpu_irq;
957
--    cpu_nmi_o      <= cpu_nmi;
958
--    cpu_addr_o     <= cpu_addr;
959
--    cpu_data_out_o <= cpu_data_out;
960
--    cpu_data_in_o  <= cpu_data_in;
961
--  end process;
962
 
963
end rtl; --===================== End of architecture =======================--
964
 

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