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[/] [System09/] [trunk/] [rtl/] [System09_Trenz_TE0141/] [secd_ram_controller.vhd] - Blame information for rev 105

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-- secd_ram_controller.vhd
--
-- Multiplex the external 16 bit SRAM to the 32 bit interface required
-- by the CPU and provide for an 8 bit backside port for the 6809 to
-- read and write SECD memory
 
library ieee;
 
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
 
entity secd_ram_controller is
  port(
    clk              : in std_logic;
    reset            : in std_logic;
 
    secd_stopped     : in std_logic;
 
    -- Internal interface to SECD (16k x 32)
    din32            : in std_logic_vector(31 downto 0);
    dout32           : out std_logic_vector(31 downto 0);
    addr32           : in std_logic_vector(13 downto 0);
    read32_enable    : in std_logic;
    write32_enable   : in std_logic;
    busy32           : out std_logic;
 
    -- Internal interface to 6809 (64k x 8)
         clk8             : in std_logic;
    din8             : in std_logic_vector(7 downto 0);
    dout8            : out std_logic_vector(7 downto 0);
    addr8            : in std_logic_vector(15 downto 0);
    rw8              : in std_logic;
    cs8_ram          : in std_logic;
    hold8            : out std_logic;
         cs8_cf           : in std_logic;
 
    -- External interface
    ram_oen          : out std_logic;
    ram_cen          : out std_logic;
    ram_wen          : out std_logic;
    ram_io           : inout std_logic_vector(15 downto 0);
    ram_a            : out std_logic_vector(20 downto 1);
    ram_bhen         : out std_logic;
    ram_blen         : out std_logic
  );
end;
 
architecture external_ram of secd_ram_controller is
 
  type hold_state_type is ( hold_release_state, hold_request_state );
 
  signal cf_hold_state : hold_state_type;
 
  signal cf_release  : std_logic;
  signal cf_count    : std_logic_vector(3 downto 0);
 
  type state_type is (idle,
                      read32_high, read32_high_deselect, read32_low,    read32_low_deselect,
                      write32_high, write32_high_deselect, write32_low, write32_low_deselect,
                                                         read8_ram, write8_ram, read8_cf, write8_cf );
 
  signal state, next_state : state_type;
 
  signal read32_buff : std_logic_vector(31 downto 0);
  signal read32_hen, read32_len : std_logic;
 
begin
 
 
secd_ram_process : process( state,
                            read32_enable, write32_enable, addr32, din32,
                            cs8_ram, rw8, addr8, din8 )
begin
    case state is
         when idle =>
                 ram_a(20 downto 1) <= (others => '0');
                 ram_cen  <= '1';
                 ram_oen  <= '1';
                 ram_wen  <= '1';
                 ram_bhen <= '1';
                 ram_blen <= '1';
                 ram_io   <= (others => 'Z');
                 read32_hen <= '0';
                 read32_len <= '0';
                 dout8      <= (others => '0');
       if read32_enable = '1' then
           hold8  <= '0';
                     busy32 <= '1';
                     next_state <= read32_high;
       elsif write32_enable = '1' then
           hold8  <= '0';
                     busy32 <= '1';
                     next_state <= write32_high;
       elsif (cs8_ram = '1') and (rw8 = '1') then
           hold8  <= '1';
                     busy32 <= '1';
                     next_state <= read8_ram;
       elsif (cs8_ram = '1') and (rw8 = '0') then
           hold8  <= '1';
                     busy32 <= '1';
                     next_state <= write8_ram;
       elsif (cs8_cf = '1') and (rw8 = '1') then
           hold8  <= '1';
                     busy32 <= '1';
                     next_state <= read8_cf;
       elsif (cs8_cf = '1') and (rw8 = '0') then
           hold8  <= '1';
                     busy32 <= '1';
                     next_state <= write8_cf;
       else
           hold8  <= '0';
                     busy32 <= '0';
                     next_state <= idle;
       end if;
 
    when read32_high =>
            ram_a(1) <= '0';
                 ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);
                 ram_cen  <= '0';
                 ram_oen  <= '0';
                 ram_wen  <= '1';
                 ram_bhen <= '0';
                 ram_blen <= '0';
                 ram_io <= (others => 'Z');
                 read32_hen <= '1';
                 read32_len <= '0';
                 busy32 <= '1';
                 dout8  <= (others => '0');
                 hold8  <= cs8_ram;
                 next_state <= read32_high_deselect;
 
    when read32_high_deselect =>
            ram_a(1) <= '1';
                 ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);
                 ram_cen  <= '1';
                 ram_oen  <= '1';
                 ram_wen  <= '1';
                 ram_bhen <= '1';
                 ram_blen <= '1';
                 ram_io <= (others => 'Z');
                 read32_hen <= '0';
                 read32_len <= '0';
                 busy32 <= '1';
                 dout8  <= (others => '0');
                 hold8  <= cs8_ram;
                 next_state <= read32_low;
 
    when read32_low =>
            ram_a(1) <= '1';
                 ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);
                 ram_cen  <= '0';
                 ram_oen  <= '0';
                 ram_wen  <= '1';
                 ram_bhen <= '0';
                 ram_blen <= '0';
                 ram_io <= (others => 'Z');
                 read32_hen <= '0';
                 read32_len <= '1';
                 busy32 <= '1';
                 dout8  <= (others => '0');
                 hold8  <= cs8_ram;
                 next_state <= read32_low_deselect;
 
    when read32_low_deselect =>
            ram_a(1) <= '1';
                 ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);
                 ram_cen  <= '1';
                 ram_oen  <= '1';
                 ram_wen  <= '1';
                 ram_bhen <= '1';
                 ram_blen <= '1';
                 ram_io <= (others => 'Z');
                 read32_hen <= '0';
                 read32_len <= '0';
                 busy32 <= '0';
                 dout8  <= (others => '0');
                 hold8  <= cs8_ram;
                 next_state <= idle;
 
    when write32_high =>
            ram_a(1) <= '0';
                 ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);
                 ram_cen  <= '0';
                 ram_oen  <= '1';
                 ram_wen  <= '0';
                 ram_bhen <= '0';
                 ram_blen <= '0';
                 ram_io <= din32(31 downto 16);
                 read32_hen <= '0';
                 read32_len <= '0';
                 busy32 <= '1';
                 dout8  <= (others => '0');
                 hold8  <= cs8_ram;
                 next_state <= write32_high_deselect;
 
    when write32_high_deselect =>
            ram_a(1) <= '1';
                 ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);
                 ram_cen  <= '1';
                 ram_oen  <= '1';
                 ram_wen  <= '1';
                 ram_bhen <= '1';
                 ram_blen <= '1';
                 ram_io <= (others => 'Z');
                 read32_hen <= '0';
                 read32_len <= '0';
                 busy32 <= '1';
                 dout8  <= (others => '0');
                 hold8  <= cs8_ram;
                 next_state <= write32_low;
 
    when write32_low =>
            ram_a(1) <= '1';
                 ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);
                 ram_cen  <= '0';
                 ram_oen  <= '0';
                 ram_wen  <= '1';
                 ram_bhen <= '0';
                 ram_blen <= '0';
                 ram_io <= din32(15 downto 0);
                 read32_hen <= '0';
                 read32_len <= '0';
                 busy32 <= '0';
                 dout8  <= (others => '0');
                 hold8  <= cs8_ram;
                 next_state <= write32_low_deselect;
 
    when write32_low_deselect =>
            ram_a(1) <= '1';
                 ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);
                 ram_cen  <= '1';
                 ram_oen  <= '1';
                 ram_wen  <= '1';
                 ram_bhen <= '1';
                 ram_blen <= '1';
                 ram_io <= (others => 'Z');
                 read32_hen <= '0';
                 read32_len <= '0';
                 busy32 <= '0';
                 dout8  <= (others => '0');
                 hold8  <= cs8_ram;
                 next_state <= idle;
 
    when read8_ram =>
                 ram_a(20 downto 1) <= "00000" & addr8(15 downto 1);
                 ram_cen  <= '0';
                 ram_oen  <= '0';
                 ram_wen  <= '1';
                 ram_bhen <= addr8(0);
                 ram_blen <= not addr8(0);
                 ram_io <= (others => 'Z');
                 read32_hen <= '0';
                 read32_len <= '0';
                 busy32 <= '1';
                 if addr8(0) = '0' then
               dout8 <= ram_io(15 downto 8);
       else
                    dout8 <= ram_io(7 downto 0);
       end if;
                 hold8 <= '0';
                 -- Synchronize on the CPU clock
                 if clk8 = '1' then
                     next_state <= idle;
       else
                     next_state <= read8_ram;
       end if;
 
    when write8_ram =>
            ram_a(1) <= '1';
                 ram_a(20 downto 1) <= "00000" & addr8(15 downto 1);
                 ram_cen  <= '0';
                 ram_oen  <= '0';
                 ram_wen  <= '1';
                 ram_bhen <= addr8(0);
                 ram_blen <= not addr8(0);
                 if addr8(0) = '0' then
               ram_io(15 downto 8) <= din8;
                         ram_io( 7 downto 0) <= (others => 'Z');
       else
                         ram_io(15 downto 8) <= (others => 'Z');
                    ram_io( 7 downto 0) <= din8;
       end if;
                 read32_hen <= '0';
                 read32_len <= '0';
                 busy32 <= '1';
                 dout8  <= (others => '0');
                 hold8  <= '0';
                 -- Synchronize on the CPU clock
                 if clk8 = '1' then
                     next_state <= idle;
       else
                     next_state <= write8_ram;
       end if;
 
 
    when read8_cf =>
                 ram_a(20 downto 1) <= "00000" & addr8(15 downto 1);
                 ram_cen  <= '1';
                 ram_oen  <= '1';
                 ram_wen  <= '1';
                 ram_bhen <= '1';
                 ram_blen <= '1';
                 ram_io <= (others => 'Z');
                 read32_hen <= '0';
                 read32_len <= '0';
                 busy32 <= '1';
                 dout8 <= ram_io(7 downto 0);
                 if cf_release = '1' then
           hold8 <= '0';
                     next_state <= idle;
       else
           hold8 <= '1';
                     next_state <= read8_cf;
       end if;
 
    when write8_cf =>
            ram_a(1) <= '1';
                 ram_a(20 downto 1) <= "00000" & addr8(15 downto 1);
                 ram_cen  <= '1';
                 ram_oen  <= '1';
                 ram_wen  <= '1';
                 ram_bhen <= '1';
                 ram_blen <= '1';
            ram_io(15 downto 8) <= (others => '0');
                 ram_io( 7 downto 0) <= din8;
                 read32_hen <= '0';
                 read32_len <= '0';
                 busy32 <= '1';
                 dout8  <= (others => '0');
                 if cf_release = '1' then
           hold8 <= '0';
                     next_state <= idle;
       else
           hold8 <= '1';
                     next_state <= write8_cf;
       end if;
 
   when others =>
            null;
 
        end case;
end process;
 
  --
  -- RAM state machine
  -- clock state transitions
  -- and register 32 bit reads.
  --
  -- Try experimenting with the clock edge
  -- The Clock edge should be the same
  -- as the transition edge of the
  -- 12.5 MHz 6809 clock.
  -- 
  ram_state_machine : process( clk, reset, read32_buff )
  begin
     if reset = '1' then
              state <= idle;
                   read32_buff <= (others => '0');
     elsif falling_edge( clk ) then
              state <= next_state;
                   if read32_hen = '1' then
                       read32_buff(31 downto 16) <= ram_io;
         end if;
                   if read32_len = '1' then
                       read32_buff(15 downto 0) <= ram_io;
         end if;
          end if;
          dout32 <= read32_buff;
  end process;
 
--
-- Hold CF access       for a few cycles
-- synchronize with the CPU clock
-- hold release is set on the rising edge
-- of the CPU clock so that you have one
-- VGA clock cycle to return to the idle state
-- of the secd_ram_process state machine.
--
cf_hold_proc: process( clk8, reset )
begin
    if reset = '1' then
                 cf_release    <= '0';
                 cf_count      <= "0000";
            cf_hold_state <= hold_release_state;
         elsif rising_edge( clk8 ) then
            case cf_hold_state is
                 when hold_release_state =>
          cf_release <= '0';
                    if cs8_cf = '1' then
                            cf_count      <= "0011";
                                 cf_hold_state <= hold_request_state;
                         end if;
 
                 when hold_request_state =>
                    cf_count <= cf_count - "0001";
                         if cf_count = "0000" then
             cf_release    <= '1';
                                 cf_hold_state <= hold_release_state;
                         end if;
       when others =>
                    null;
       end case;
         end if;
 
end process;
 
end;

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[/] [System09/] [trunk/] [rtl/] [System09_Trenz_TE0141/] [secd_ram_controller.vhd] - Blame information for rev 105

Line No.	Rev	Author	Line
1	105	davidgb	`-- secd_ram_controller.vhd`
2			`--`
3			`-- Multiplex the external 16 bit SRAM to the 32 bit interface required`
4			`-- by the CPU and provide for an 8 bit backside port for the 6809 to`
5			`-- read and write SECD memory`
6
7			`library ieee;`
8
9			`use ieee.std_logic_1164.all;`
10			`use ieee.numeric_std.all;`
11			`use ieee.std_logic_unsigned.all;`
12
13			`entity secd_ram_controller is`
14			`port(`
15			`clk : in std_logic;`
16			`reset : in std_logic;`
17
18			`secd_stopped : in std_logic;`
19
20			`-- Internal interface to SECD (16k x 32)`
21			`din32 : in std_logic_vector(31 downto 0);`
22			`dout32 : out std_logic_vector(31 downto 0);`
23			`addr32 : in std_logic_vector(13 downto 0);`
24			`read32_enable : in std_logic;`
25			`write32_enable : in std_logic;`
26			`busy32 : out std_logic;`
27
28			`-- Internal interface to 6809 (64k x 8)`
29			`clk8 : in std_logic;`
30			`din8 : in std_logic_vector(7 downto 0);`
31			`dout8 : out std_logic_vector(7 downto 0);`
32			`addr8 : in std_logic_vector(15 downto 0);`
33			`rw8 : in std_logic;`
34			`cs8_ram : in std_logic;`
35			`hold8 : out std_logic;`
36			`cs8_cf : in std_logic;`
37
38			`-- External interface`
39			`ram_oen : out std_logic;`
40			`ram_cen : out std_logic;`
41			`ram_wen : out std_logic;`
42			`ram_io : inout std_logic_vector(15 downto 0);`
43			`ram_a : out std_logic_vector(20 downto 1);`
44			`ram_bhen : out std_logic;`
45			`ram_blen : out std_logic`
46			`);`
47			`end;`
48
49			`architecture external_ram of secd_ram_controller is`
50
51			`type hold_state_type is ( hold_release_state, hold_request_state );`
52
53			`signal cf_hold_state : hold_state_type;`
54
55			`signal cf_release : std_logic;`
56			`signal cf_count : std_logic_vector(3 downto 0);`
57
58			`type state_type is (idle,`
59			`read32_high, read32_high_deselect, read32_low, read32_low_deselect,`
60			`write32_high, write32_high_deselect, write32_low, write32_low_deselect,`
61			`read8_ram, write8_ram, read8_cf, write8_cf );`
62
63			`signal state, next_state : state_type;`
64
65			`signal read32_buff : std_logic_vector(31 downto 0);`
66			`signal read32_hen, read32_len : std_logic;`
67
68			`begin`
69
70
71			`secd_ram_process : process( state,`
72			`read32_enable, write32_enable, addr32, din32,`
73			`cs8_ram, rw8, addr8, din8 )`
74			`begin`
75			`case state is`
76			`when idle =>`
77			`ram_a(20 downto 1) <= (others => '0');`
78			`ram_cen <= '1';`
79			`ram_oen <= '1';`
80			`ram_wen <= '1';`
81			`ram_bhen <= '1';`
82			`ram_blen <= '1';`
83			`ram_io <= (others => 'Z');`
84			`read32_hen <= '0';`
85			`read32_len <= '0';`
86			`dout8 <= (others => '0');`
87			`if read32_enable = '1' then`
88			`hold8 <= '0';`
89			`busy32 <= '1';`
90			`next_state <= read32_high;`
91			`elsif write32_enable = '1' then`
92			`hold8 <= '0';`
93			`busy32 <= '1';`
94			`next_state <= write32_high;`
95			`elsif (cs8_ram = '1') and (rw8 = '1') then`
96			`hold8 <= '1';`
97			`busy32 <= '1';`
98			`next_state <= read8_ram;`
99			`elsif (cs8_ram = '1') and (rw8 = '0') then`
100			`hold8 <= '1';`
101			`busy32 <= '1';`
102			`next_state <= write8_ram;`
103			`elsif (cs8_cf = '1') and (rw8 = '1') then`
104			`hold8 <= '1';`
105			`busy32 <= '1';`
106			`next_state <= read8_cf;`
107			`elsif (cs8_cf = '1') and (rw8 = '0') then`
108			`hold8 <= '1';`
109			`busy32 <= '1';`
110			`next_state <= write8_cf;`
111			`else`
112			`hold8 <= '0';`
113			`busy32 <= '0';`
114			`next_state <= idle;`
115			`end if;`
116
117			`when read32_high =>`
118			`ram_a(1) <= '0';`
119			`ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);`
120			`ram_cen <= '0';`
121			`ram_oen <= '0';`
122			`ram_wen <= '1';`
123			`ram_bhen <= '0';`
124			`ram_blen <= '0';`
125			`ram_io <= (others => 'Z');`
126			`read32_hen <= '1';`
127			`read32_len <= '0';`
128			`busy32 <= '1';`
129			`dout8 <= (others => '0');`
130			`hold8 <= cs8_ram;`
131			`next_state <= read32_high_deselect;`
132
133			`when read32_high_deselect =>`
134			`ram_a(1) <= '1';`
135			`ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);`
136			`ram_cen <= '1';`
137			`ram_oen <= '1';`
138			`ram_wen <= '1';`
139			`ram_bhen <= '1';`
140			`ram_blen <= '1';`
141			`ram_io <= (others => 'Z');`
142			`read32_hen <= '0';`
143			`read32_len <= '0';`
144			`busy32 <= '1';`
145			`dout8 <= (others => '0');`
146			`hold8 <= cs8_ram;`
147			`next_state <= read32_low;`
148
149			`when read32_low =>`
150			`ram_a(1) <= '1';`
151			`ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);`
152			`ram_cen <= '0';`
153			`ram_oen <= '0';`
154			`ram_wen <= '1';`
155			`ram_bhen <= '0';`
156			`ram_blen <= '0';`
157			`ram_io <= (others => 'Z');`
158			`read32_hen <= '0';`
159			`read32_len <= '1';`
160			`busy32 <= '1';`
161			`dout8 <= (others => '0');`
162			`hold8 <= cs8_ram;`
163			`next_state <= read32_low_deselect;`
164
165			`when read32_low_deselect =>`
166			`ram_a(1) <= '1';`
167			`ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);`
168			`ram_cen <= '1';`
169			`ram_oen <= '1';`
170			`ram_wen <= '1';`
171			`ram_bhen <= '1';`
172			`ram_blen <= '1';`
173			`ram_io <= (others => 'Z');`
174			`read32_hen <= '0';`
175			`read32_len <= '0';`
176			`busy32 <= '0';`
177			`dout8 <= (others => '0');`
178			`hold8 <= cs8_ram;`
179			`next_state <= idle;`
180
181			`when write32_high =>`
182			`ram_a(1) <= '0';`
183			`ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);`
184			`ram_cen <= '0';`
185			`ram_oen <= '1';`
186			`ram_wen <= '0';`
187			`ram_bhen <= '0';`
188			`ram_blen <= '0';`
189			`ram_io <= din32(31 downto 16);`
190			`read32_hen <= '0';`
191			`read32_len <= '0';`
192			`busy32 <= '1';`
193			`dout8 <= (others => '0');`
194			`hold8 <= cs8_ram;`
195			`next_state <= write32_high_deselect;`
196
197			`when write32_high_deselect =>`
198			`ram_a(1) <= '1';`
199			`ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);`
200			`ram_cen <= '1';`
201			`ram_oen <= '1';`
202			`ram_wen <= '1';`
203			`ram_bhen <= '1';`
204			`ram_blen <= '1';`
205			`ram_io <= (others => 'Z');`
206			`read32_hen <= '0';`
207			`read32_len <= '0';`
208			`busy32 <= '1';`
209			`dout8 <= (others => '0');`
210			`hold8 <= cs8_ram;`
211			`next_state <= write32_low;`
212
213			`when write32_low =>`
214			`ram_a(1) <= '1';`
215			`ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);`
216			`ram_cen <= '0';`
217			`ram_oen <= '0';`
218			`ram_wen <= '1';`
219			`ram_bhen <= '0';`
220			`ram_blen <= '0';`
221			`ram_io <= din32(15 downto 0);`
222			`read32_hen <= '0';`
223			`read32_len <= '0';`
224			`busy32 <= '0';`
225			`dout8 <= (others => '0');`
226			`hold8 <= cs8_ram;`
227			`next_state <= write32_low_deselect;`
228
229			`when write32_low_deselect =>`
230			`ram_a(1) <= '1';`
231			`ram_a(20 downto 2) <= "00000" & addr32(13 downto 0);`
232			`ram_cen <= '1';`
233			`ram_oen <= '1';`
234			`ram_wen <= '1';`
235			`ram_bhen <= '1';`
236			`ram_blen <= '1';`
237			`ram_io <= (others => 'Z');`
238			`read32_hen <= '0';`
239			`read32_len <= '0';`
240			`busy32 <= '0';`
241			`dout8 <= (others => '0');`
242			`hold8 <= cs8_ram;`
243			`next_state <= idle;`
244
245			`when read8_ram =>`
246			`ram_a(20 downto 1) <= "00000" & addr8(15 downto 1);`
247			`ram_cen <= '0';`
248			`ram_oen <= '0';`
249			`ram_wen <= '1';`
250			`ram_bhen <= addr8(0);`
251			`ram_blen <= not addr8(0);`
252			`ram_io <= (others => 'Z');`
253			`read32_hen <= '0';`
254			`read32_len <= '0';`
255			`busy32 <= '1';`
256			`if addr8(0) = '0' then`
257			`dout8 <= ram_io(15 downto 8);`
258			`else`
259			`dout8 <= ram_io(7 downto 0);`
260			`end if;`
261			`hold8 <= '0';`
262			`-- Synchronize on the CPU clock`
263			`if clk8 = '1' then`
264			`next_state <= idle;`
265			`else`
266			`next_state <= read8_ram;`
267			`end if;`
268
269			`when write8_ram =>`
270			`ram_a(1) <= '1';`
271			`ram_a(20 downto 1) <= "00000" & addr8(15 downto 1);`
272			`ram_cen <= '0';`
273			`ram_oen <= '0';`
274			`ram_wen <= '1';`
275			`ram_bhen <= addr8(0);`
276			`ram_blen <= not addr8(0);`
277			`if addr8(0) = '0' then`
278			`ram_io(15 downto 8) <= din8;`
279			`ram_io( 7 downto 0) <= (others => 'Z');`
280			`else`
281			`ram_io(15 downto 8) <= (others => 'Z');`
282			`ram_io( 7 downto 0) <= din8;`
283			`end if;`
284			`read32_hen <= '0';`
285			`read32_len <= '0';`
286			`busy32 <= '1';`
287			`dout8 <= (others => '0');`
288			`hold8 <= '0';`
289			`-- Synchronize on the CPU clock`
290			`if clk8 = '1' then`
291			`next_state <= idle;`
292			`else`
293			`next_state <= write8_ram;`
294			`end if;`
295
296
297			`when read8_cf =>`
298			`ram_a(20 downto 1) <= "00000" & addr8(15 downto 1);`
299			`ram_cen <= '1';`
300			`ram_oen <= '1';`
301			`ram_wen <= '1';`
302			`ram_bhen <= '1';`
303			`ram_blen <= '1';`
304			`ram_io <= (others => 'Z');`
305			`read32_hen <= '0';`
306			`read32_len <= '0';`
307			`busy32 <= '1';`
308			`dout8 <= ram_io(7 downto 0);`
309			`if cf_release = '1' then`
310			`hold8 <= '0';`
311			`next_state <= idle;`
312			`else`
313			`hold8 <= '1';`
314			`next_state <= read8_cf;`
315			`end if;`
316
317			`when write8_cf =>`
318			`ram_a(1) <= '1';`
319			`ram_a(20 downto 1) <= "00000" & addr8(15 downto 1);`
320			`ram_cen <= '1';`
321			`ram_oen <= '1';`
322			`ram_wen <= '1';`
323			`ram_bhen <= '1';`
324			`ram_blen <= '1';`
325			`ram_io(15 downto 8) <= (others => '0');`
326			`ram_io( 7 downto 0) <= din8;`
327			`read32_hen <= '0';`
328			`read32_len <= '0';`
329			`busy32 <= '1';`
330			`dout8 <= (others => '0');`
331			`if cf_release = '1' then`
332			`hold8 <= '0';`
333			`next_state <= idle;`
334			`else`
335			`hold8 <= '1';`
336			`next_state <= write8_cf;`
337			`end if;`
338
339			`when others =>`
340			`null;`
341
342			`end case;`
343			`end process;`
344
345			`--`
346			`-- RAM state machine`
347			`-- clock state transitions`
348			`-- and register 32 bit reads.`
349			`--`
350			`-- Try experimenting with the clock edge`
351			`-- The Clock edge should be the same`
352			`-- as the transition edge of the`
353			`-- 12.5 MHz 6809 clock.`
354			`--`
355			`ram_state_machine : process( clk, reset, read32_buff )`
356			`begin`
357			`if reset = '1' then`
358			`state <= idle;`
359			`read32_buff <= (others => '0');`
360			`elsif falling_edge( clk ) then`
361			`state <= next_state;`
362			`if read32_hen = '1' then`
363			`read32_buff(31 downto 16) <= ram_io;`
364			`end if;`
365			`if read32_len = '1' then`
366			`read32_buff(15 downto 0) <= ram_io;`
367			`end if;`
368			`end if;`
369			`dout32 <= read32_buff;`
370			`end process;`
371
372			`--`
373			`-- Hold CF access for a few cycles`
374			`-- synchronize with the CPU clock`
375			`-- hold release is set on the rising edge`
376			`-- of the CPU clock so that you have one`
377			`-- VGA clock cycle to return to the idle state`
378			`-- of the secd_ram_process state machine.`
379			`--`
380			`cf_hold_proc: process( clk8, reset )`
381			`begin`
382			`if reset = '1' then`
383			`cf_release <= '0';`
384			`cf_count <= "0000";`
385			`cf_hold_state <= hold_release_state;`
386			`elsif rising_edge( clk8 ) then`
387			`case cf_hold_state is`
388			`when hold_release_state =>`
389			`cf_release <= '0';`
390			`if cs8_cf = '1' then`
391			`cf_count <= "0011";`
392			`cf_hold_state <= hold_request_state;`
393			`end if;`
394
395			`when hold_request_state =>`
396			`cf_count <= cf_count - "0001";`
397			`if cf_count = "0000" then`
398			`cf_release <= '1';`
399			`cf_hold_state <= hold_release_state;`
400			`end if;`
401			`when others =>`
402			`null;`
403			`end case;`
404			`end if;`
405
406			`end process;`
407
408			`end;`