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[/] [System09/] [trunk/] [rtl/] [System09_Xess_XSA-3S1000/] [System09_Xess_XSA-3S1000.vhd] - Blame information for rev 113

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1 19 dilbert57
--===========================================================================----
2
--
3
--  S Y N T H E Z I A B L E    System09 - SOC.
4
--
5
--  www.OpenCores.Org - February 2007
6
--  This core adheres to the GNU public license  
7
--
8
-- File name      : System09_Xess_XSA-3S1000.vhd
9
--
10
-- Purpose        : Top level file for 6809 compatible system on a chip
11
--                  Designed with Xilinx XC3S1000 Spartan 3 FPGA.
12
--                  Implemented With XESS XSA-3S1000 FPGA board.
13
--                  *** Note ***
14
--                  This configuration can run Flex9 however it only has
15
--                  32k bytes of user memory and the VDU is monochrome
16
--                  The design needs to be updated to use the SDRAM on 
17
--                  the XSA-3S1000 board.
18
--                  This configuration also lacks a DAT so cannot use
19
--                  the RAM Disk features of SYS09BUG.
20
--
21
-- Dependencies   : ieee.Std_Logic_1164
22
--                  ieee.std_logic_unsigned
23
--                  ieee.std_logic_arith
24
--                  ieee.numeric_std
25
--                  unisim.vcomponents
26
--
27
-- Uses           : mon_rom    (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
28
--                  cpu09      (cpu09.vhd)          CPU core
29 99 davidgb
--                  ACIA_6850  (acia6850.vhd)      ACIA / UART
30 19 dilbert57
--                  ACIA_Clock (ACIA_Clock.vhd)      ACIA clock.
31
--                  keyboard   (keyboard.vhd)        PS/2 Keyboard interface
32
--                             (ps2_keyboard.vhd)
33
--                             (keymap_rom_slice.vhd) Key map table 
34
--                  vdu8_mono  (vdu8_mono.vhd)        Monochrome VDU
35
--                             (char_rom2k_b16.vhd)
36
--                             (ram2k_b16.vhd)
37
--                  timer      (timer.vhd)            Interrupt timer
38
--                  trap       (trap.vhd)             Bus condition trap logic
39
--                  flex_ram   (flex9_ram8k_b16.vhd)  Flex operating system
40
--                  ram_32K    (ram32k_b16.vhd)       32 KBytes of Block RAM
41
--                  
42
-- 
43
-- Author         : John E. Kent      
44
--                  dilbert57@opencores.org      
45
--
46
-- Memory Map     :
47
--
48
-- $0000 - User program RAM (32K Bytes)
49
-- $C000 - Flex Operating System memory (8K Bytes)
50
-- $E000 - ACIA (SWTPc)
51
-- $E010 - Reserved for FD1771 FDC (SWTPc)
52
-- $E020 - Keyboard
53
-- $E030 - VDU
54
-- $E040 - IDE / Compact Flash interface
55
-- $E050 - Timer
56
-- $E060 - Bus trap
57
-- $E070 - Reserced for Parallel I/O (B5-X300)
58
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
59
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
60
-- $F000 - Sys09Bug monitor Program (4K Bytes)
61
--
62
--===========================================================================----
63
--
64
-- Revision History:
65
--===========================================================================--
66
-- Version 0.1 - 20 March 2003
67
-- Version 0.2 - 30 March 2003
68
-- Version 0.3 - 29 April 2003
69
-- Version 0.4 - 29 June 2003
70
--
71
-- Version 0.5 - 19 July 2003
72
-- prints out "Hello World"
73
--
74
-- Version 0.6 - 5 September 2003
75
-- Runs SBUG
76
--
77
-- Version 1.0- 6 Sep 2003 - John Kent
78
-- Inverted SysClk
79
-- Initial release to Open Cores
80
--
81
-- Version 1.1 - 17 Jan 2004 - John Kent
82
-- Updated miniUart.
83
--
84
-- Version 1.2 - 25 Jan 2004 - John Kent
85
-- removed signals "test_alu" and "test_cc" 
86
-- Trap hardware re-instated.
87
--
88
-- Version 1.3 - 11 Feb 2004 - John Kent
89
-- Designed forked off to produce System09_VDU
90
-- Added VDU component
91
--      VDU runs at 25MHz and divides the clock by 2 for the CPU
92
-- UART Runs at 57.6 Kbps
93
--
94
-- Version 2.0 - 2 September 2004 - John Kent
95
-- ported to Digilent Xilinx Spartan3 starter board
96
--      removed Compact Flash and Trap Logic.
97
-- Replaced SBUG with KBug9s
98
--
99
-- Version 3.0 - 29th August 2006 - John Kent
100
-- Adapted to XSA-3S1000 board.
101
-- Removed DAT and miniUART.
102
-- Used 32KBytes of Block RAM.
103
--
104
-- Version 3.1 - 15th January 2007 - John Kent
105
-- Modified vdu8 interface
106
-- Added a clock divider
107
--
108
-- Version 3.2 - 25th February 2007 - John Kent
109
-- reinstated ACIA_6850 and ACIA_Clock
110
-- Updated VDU8 & Keyboard with generic parameters
111
-- Defined Constants for clock speed calculations
112
--
113
-- Version 3.3 - 1st July 2007 - John Kent
114
-- Made VDU mono to save on one RAMB16
115
-- Used distributed memory for Key Map ROM to save one RAMB16
116
-- Added Flex RAM at $C000 to $DFFF using 4 spare RAMB16s
117
-- Added timer and trap logic
118
-- Added IDE Interface for Compact Flash
119
-- Replaced KBug9s and stack with Sys09Bug.
120
--
121 22 dilbert57
-- Version 4.0 - 1st February 2008 - John kent
122
-- Replaced Block RAM with SDRAM Interface
123
-- Modified Hold timing for SDRAM
124
-- Added CF and Ethernet interface 
125
-- via the 16 bit peripheral bus at $E100
126
--
127 19 dilbert57
--===========================================================================--
128
library ieee;
129
   use ieee.std_logic_1164.all;
130
   use IEEE.STD_LOGIC_ARITH.ALL;
131
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
132
   use ieee.numeric_std.all;
133 22 dilbert57
library work;
134
        use work.common.all;
135
        use WORK.xsasdram.all;
136 19 dilbert57
library unisim;
137
   use unisim.vcomponents.all;
138
 
139 59 davidgb
entity my_system09 is
140 19 dilbert57
  port(
141 22 dilbert57
    CLKA       : in  Std_Logic;  -- 100MHz Clock input
142
         SW2_N        : in  Std_logic;  -- Master Reset input (active low)
143
         SW3_N        : in  Std_logic;  -- Non Maskable Interrupt input (active low)
144 19 dilbert57
 
145
         -- PS/2 Keyboard
146 22 dilbert57
         ps2_clk      : inout Std_logic;
147
         ps2_dat      : inout Std_Logic;
148 19 dilbert57
 
149
         -- CRTC output signals
150 22 dilbert57
         vga_vsync_n  : out Std_Logic;
151
    vga_hsync_n  : out Std_Logic;
152
    vga_blue     : out std_logic_vector(2 downto 0);
153
    vga_green    : out std_logic_vector(2 downto 0);
154
    vga_red      : out std_logic_vector(2 downto 0);
155 19 dilbert57
 
156
    -- RS232 Port
157 22 dilbert57
         RS232_RXD    : in  Std_Logic;
158
         RS232_TXD    : out Std_Logic;
159
    RS232_CTS    : in  Std_Logic;
160
    RS232_RTS    : out Std_Logic;
161 19 dilbert57
 
162 22 dilbert57
         -- Status 7 segment LED
163
--       S            : out std_logic_vector(7 downto 0);
164 19 dilbert57
 
165 22 dilbert57
    -- SDRAM side
166
    SDRAM_clkfb  : in  std_logic;            -- feedback SDRAM clock after PCB delays
167
    SDRAM_clkout : out std_logic;            -- clock to SDRAM
168
    SDRAM_CKE    : out std_logic;            -- clock-enable to SDRAM
169
    SDRAM_CS_N   : out std_logic;            -- chip-select to SDRAM
170
    SDRAM_RAS_N  : out std_logic;            -- SDRAM row address strobe
171
    SDRAM_CAS_N  : out std_logic;            -- SDRAM column address strobe
172
    SDRAM_WE_N   : out std_logic;            -- SDRAM write enable
173
    SDRAM_BA     : out std_logic_vector(1 downto 0);  -- SDRAM bank address
174
    SDRAM_A      : out std_logic_vector(12 downto 0);  -- SDRAM row/column address
175
    SDRAM_D      : inout  std_logic_vector(15 downto 0);  -- data from SDRAM
176
    SDRAM_DQMH   : out std_logic;            -- enable upper-byte of SDRAM databus if true
177
    SDRAM_DQML   : out std_logic;            -- enable lower-byte of SDRAM databus if true
178
 
179
         -- Peripheral I/O bus $E100 - $E1FF
180
    PB_RD_N      : out std_logic;
181
    PB_WR_N      : out std_logic;
182
    PB_A         : out std_logic_vector(4 downto 0);
183
    PB_D         : inout std_logic_vector(15 downto 0);
184
 
185
    -- IDE Compact Flash $E100 - $E13F
186
    ide_dmack_n  : out std_logic;
187
         ide_cs0_n    : out std_logic;
188
         ide_cs1_n    : out std_logic;
189
 
190
    -- Ethernet $E140 - $E17F
191
         ether_cs_n   : out std_logic;
192
    ether_aen    : out std_logic; -- Ethernet address enable not 
193
    ether_bhe_n  : out std_logic; -- Ethernet bus high enable 
194
    ether_clk    : in  std_logic; -- Ethernet clock 
195
    ether_rdy    : in  std_logic; -- Ethernet ready
196
         ether_irq    : in  std_logic; -- Ethernet irq - Shared with BAR6
197
 
198
    -- Slot 1 $E180 - $E1BF
199
         slot1_cs_n   : out std_logic;
200
--       slot1_irq    : in  std_logic;
201
 
202
    -- Slot 2 $E1C0 - $E1FF
203
         slot2_cs_n   : out std_logic;
204
--       slot2_irq    : in  std_logic;
205
 
206
         -- Disable Flash
207
         FLASH_CE_N   : out std_logic
208 19 dilbert57
         );
209
end My_System09;
210
 
211
-------------------------------------------------------------------------------
212
-- Architecture for System09
213
-------------------------------------------------------------------------------
214 59 davidgb
architecture rtl of my_system09 is
215 19 dilbert57
 
216
  -----------------------------------------------------------------------------
217
  -- constants
218
  -----------------------------------------------------------------------------
219
  constant SYS_Clock_Frequency  : integer := 50000000;  -- FPGA System Clock
220
  constant PIX_Clock_Frequency  : integer := 25000000;  -- VGA Pixel Clock
221
  constant CPU_Clock_Frequency  : integer := 25000000;  -- CPU Clock
222
  constant BAUD_Rate            : integer := 57600;       -- Baud Rate
223
  constant ACIA_Clock_Frequency : integer := BAUD_Rate * 16;
224
 
225
  type hold_state_type is ( hold_release_state, hold_request_state );
226
 
227
  -----------------------------------------------------------------------------
228
  -- Signals
229
  -----------------------------------------------------------------------------
230
  signal rst_n          :  Std_logic;  -- Master Reset input (active low)
231
  signal nmi_n          :  Std_logic;  -- Non Maskable Interrupt input (active low)
232
 
233
  -- BOOT ROM
234
  signal rom_cs         : Std_logic;
235
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
236
 
237
  -- Flex Memory & Monitor Stack
238
  signal flex_cs        : Std_logic;
239
  signal flex_data_out  : Std_Logic_Vector(7 downto 0);
240
 
241
  -- ACIA/UART Interface signals
242 22 dilbert57
  signal acia_data_out  : Std_Logic_Vector(7 downto 0);
243
  signal acia_cs        : Std_Logic;
244
  signal acia_irq       : Std_Logic;
245
  signal acia_clk       : Std_Logic;
246 19 dilbert57
  signal rxd            : Std_Logic;
247
  signal txd            : Std_Logic;
248
  signal DCD_n          : Std_Logic;
249
  signal RTS_n          : Std_Logic;
250
  signal CTS_n          : Std_Logic;
251
 
252
  -- keyboard port
253
  signal keyboard_data_out : std_logic_vector(7 downto 0);
254
  signal keyboard_cs       : std_logic;
255
  signal keyboard_irq      : std_logic;
256
 
257
  -- RAM
258
  signal ram_cs         : std_logic; -- memory chip select
259
  signal ram_data_out   : std_logic_vector(7 downto 0);
260 22 dilbert57
  signal ram_hold       : std_logic; -- hold off slow accesses
261 19 dilbert57
 
262
  -- CPU Interface signals
263
  signal cpu_reset      : Std_Logic;
264
  signal cpu_clk        : Std_Logic;
265
  signal cpu_rw         : std_logic;
266
  signal cpu_vma        : std_logic;
267
  signal cpu_halt       : std_logic;
268
  signal cpu_hold       : std_logic;
269
  signal cpu_firq       : std_logic;
270
  signal cpu_irq        : std_logic;
271
  signal cpu_nmi        : std_logic;
272
  signal cpu_addr       : std_logic_vector(15 downto 0);
273
  signal cpu_data_in    : std_logic_vector(7 downto 0);
274
  signal cpu_data_out   : std_logic_vector(7 downto 0);
275
 
276 22 dilbert57
  -- Dynamic Address Translation
277
  signal dat_cs       : std_logic;
278
  signal dat_addr     : std_logic_vector(7 downto 0);
279
 
280 19 dilbert57
  -- Video Display Unit
281
  signal vdu_cs         : std_logic;
282
  signal vdu_data_out   : std_logic_vector(7 downto 0);
283
  signal vga_red_o      : std_logic;
284
  signal vga_green_o    : std_logic;
285
  signal vga_blue_o     : std_logic;
286
 
287
  -- timer
288
  signal timer_data_out : std_logic_vector(7 downto 0);
289
  signal timer_cs       : std_logic;
290
  signal timer_irq      : std_logic;
291
 
292
  -- trap
293
  signal trap_cs        : std_logic;
294
  signal trap_data_out  : std_logic_vector(7 downto 0);
295
  signal trap_irq       : std_logic;
296
 
297 22 dilbert57
  -- Peripheral Bus port
298
  signal pb_data_out   : std_logic_vector(7 downto 0);
299
  signal pb_cs         : std_logic;       -- peripheral bus chip select
300
  signal pb_wru        : std_logic;       -- upper byte write strobe
301
  signal pb_wrl        : std_logic;       -- lower byte write strobe
302
  signal pb_rdu        : std_logic;       -- upper byte read strobe
303
  signal pb_rdl        : std_logic;       -- lower byte read strobe
304
  signal pb_hold       : std_logic;       -- hold peripheral bus access
305
  signal pb_release    : std_logic;       -- release hold of peripheral bus
306
  signal pb_count      : std_logic_vector(3 downto 0); -- hold counter
307
  signal pb_hold_state : hold_state_type;
308
  signal pb_wreg       : std_logic_vector(7 downto 0); -- lower byte write register
309
  signal pb_rreg       : std_logic_vector(7 downto 0); -- lower byte read register
310 19 dilbert57
 
311 22 dilbert57
  -- Peripheral chip selects on Peripheral Bus
312
  signal ide_cs        : std_logic; -- IDE CF interface
313
  signal ether_cs      : std_logic;     -- Ethernet interface
314
  signal slot1_cs      : std_logic;     -- Expansion slot 1
315
  signal slot2_cs      : std_logic;     -- Expansion slot 2
316
 
317
 
318
-- SDRAM
319
 
320
  constant  FREQ                 :     natural := 100_000; -- operating frequency in KHz
321
  constant  CLK_DIV              :     real    := 2.0;    -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
322
  constant  PIPE_EN              :     boolean := false;  -- if true, enable pipelined read operations
323
  constant  MAX_NOP              :     natural := 10000;  -- number of NOPs before entering self-refresh
324
  constant  MULTIPLE_ACTIVE_ROWS :     boolean := false;  -- if true, allow an active row in each bank
325
  constant  DATA_WIDTH           :     natural := 16;     -- host & SDRAM data width
326
  constant  NROWS                :     natural := 8192;   -- number of rows in SDRAM array
327
  constant  NCOLS                :     natural := 512;    -- number of columns in SDRAM array
328
  constant  HADDR_WIDTH          :     natural := 24;     -- host-side address width
329
  constant  SADDR_WIDTH          :     natural := 13;     -- SDRAM-side address width
330
 
331
  signal   rst_i        : std_logic;     -- internal reset signal
332
  signal   clk_i        : std_logic;     -- internal master clock signal
333
  signal   lock         : std_logic;     -- SDRAM clock DLL lock indicator
334
 
335
  -- signals that go through the SDRAM host-side interface
336
  signal opBegun        : std_logic;        -- SDRAM operation started indicator
337
  signal earlyBegun     : std_logic;        -- SDRAM operation started indicator
338
  signal ramDone        : std_logic;        -- SDRAM operation complete indicator
339
  signal rdDone         : std_logic;        -- SDRAM read operation complete indicator
340
  signal wrDone         : std_logic;        -- SDRAM write operation complete indicator
341
  signal hAddr          : std_logic_vector(HADDR_WIDTH-1 downto 0);  -- host address bus
342
  signal hDIn           : std_logic_vector(DATA_WIDTH-1 downto 0);  -- host-side data to SDRAM
343
  signal hDOut          : std_logic_vector(DATA_WIDTH-1 downto 0);  -- host-side data from SDRAM
344
  signal hRd            : std_logic;        -- host-side read control signal
345
  signal hWr            : std_logic;        -- host-side write control signal
346
  signal rdPending      : std_logic;        -- read operation pending in SDRAM pipeline
347
  type ram_rd_type is (rd_state0, rd_state1, rd_state2, rd_state3);
348
  type ram_wr_type is (wr_state0, wr_state1, wr_state2, wr_state3, wr_state4);
349
  signal ram_rd_state   : ram_rd_type;
350
  signal ram_wr_state   : ram_wr_type;
351
 
352 19 dilbert57
--  signal BaudCount    : std_logic_vector(5 downto 0);
353
  signal CountL         : std_logic_vector(23 downto 0);
354 22 dilbert57
  signal clk_count      : std_logic_vector(0 downto 0);
355 19 dilbert57
  signal Clk25          : std_logic;
356
  signal pix_clk        : std_logic;
357
 
358
-----------------------------------------------------------------
359
--
360
-- CPU09 CPU core
361
--
362
-----------------------------------------------------------------
363
 
364
component cpu09
365
  port (
366
         clk:        in std_logic;
367
    rst:      in        std_logic;
368 99 davidgb
    vma:             out        std_logic;
369
    addr:  out  std_logic_vector(15 downto 0);
370 19 dilbert57
    rw:      out        std_logic;              -- Asynchronous memory interface
371 99 davidgb
         data_out: out std_logic_vector(7 downto 0);
372 19 dilbert57
    data_in:  in        std_logic_vector(7 downto 0);
373
         irq:      in  std_logic;
374 99 davidgb
         firq:     in  std_logic;
375 19 dilbert57
         nmi:      in  std_logic;
376 99 davidgb
         halt:     in  std_logic;
377
         hold:     in  std_logic
378 19 dilbert57
  );
379
end component;
380
 
381
 
382
----------------------------------------
383
--
384
-- 4K Block RAM Monitor ROM
385
--
386
----------------------------------------
387
component mon_rom
388
    Port (
389
       clk   : in  std_logic;
390
                 rst   : in  std_logic;
391
                 cs    : in  std_logic;
392
                 rw    : in  std_logic;
393
       addr  : in  std_logic_vector (11 downto 0);
394 95 davidgb
       data_out : out std_logic_vector (7 downto 0);
395
       data_in : in  std_logic_vector (7 downto 0)
396 19 dilbert57
    );
397
end component;
398
 
399
 
400
----------------------------------------
401
--
402
-- 8KBytes Block RAM for FLEX9
403
-- $C000 - $DFFF
404
--
405
----------------------------------------
406
component flex_ram
407
  Port (
408
    clk      : in  std_logic;
409
    rst      : in  std_logic;
410
    cs       : in  std_logic;
411
    rw       : in  std_logic;
412
    addr     : in  std_logic_vector (12 downto 0);
413 95 davidgb
    data_out    : out std_logic_vector (7 downto 0);
414
    data_in    : in  std_logic_vector (7 downto 0)
415 19 dilbert57
    );
416
end component;
417
 
418
-----------------------------------------------------------------
419
--
420
-- 6850 Compatible ACIA / UART
421
--
422
-----------------------------------------------------------------
423
 
424 99 davidgb
component acia6850
425 19 dilbert57
  port (
426
     clk      : in  Std_Logic;  -- System Clock
427
     rst      : in  Std_Logic;  -- Reset input (active high)
428
     cs       : in  Std_Logic;  -- miniUART Chip Select
429
     rw       : in  Std_Logic;  -- Read / Not Write
430 99 davidgb
     addr     : in  Std_Logic;  -- Register Select
431
     data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
432
     data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
433 19 dilbert57
     irq      : out Std_Logic;  -- Interrupt
434
     RxC      : in  Std_Logic;  -- Receive Baud Clock
435
     TxC      : in  Std_Logic;  -- Transmit Baud Clock
436
     RxD      : in  Std_Logic;  -- Receive Data
437
     TxD      : out Std_Logic;  -- Transmit Data
438
     DCD_n    : in  Std_Logic;  -- Data Carrier Detect
439
     CTS_n    : in  Std_Logic;  -- Clear To Send
440
     RTS_n    : out Std_Logic );  -- Request To send
441
end component;
442
 
443
 
444
-----------------------------------------------------------------
445
--
446
-- ACIA Clock divider
447
--
448
-----------------------------------------------------------------
449
 
450
component ACIA_Clock
451
  generic (
452 99 davidgb
     SYS_CLK_FREQ  : integer :=  SYS_Clock_Frequency;
453
          ACIA_CLK_FREQ : integer := ACIA_Clock_Frequency
454 19 dilbert57
  );
455
  port (
456
     clk      : in  Std_Logic;  -- System Clock Input
457 99 davidgb
          acia_clk : out Std_logic   -- ACIA Clock output
458 19 dilbert57
  );
459
end component;
460
 
461
 
462
----------------------------------------
463
--
464
-- PS/2 Keyboard
465
--
466
----------------------------------------
467
 
468
component keyboard
469
  generic(
470 99 davidgb
  KBD_CLK_FREQ : integer := CPU_Clock_Frequency
471 19 dilbert57
  );
472
  port(
473
  clk             : in    std_logic;
474
  rst             : in    std_logic;
475
  cs              : in    std_logic;
476
  rw              : in    std_logic;
477
  addr            : in    std_logic;
478
  data_in         : in    std_logic_vector(7 downto 0);
479
  data_out        : out   std_logic_vector(7 downto 0);
480
  irq             : out   std_logic;
481
  kbd_clk         : inout std_logic;
482
  kbd_data        : inout std_logic
483
  );
484
end component;
485
 
486
----------------------------------------
487
--
488
-- Video Display Unit.
489
--
490
----------------------------------------
491 22 dilbert57
component vdu8
492 19 dilbert57
      generic(
493
        VDU_CLOCK_FREQUENCY    : integer := CPU_Clock_Frequency; -- HZ
494
        VGA_CLOCK_FREQUENCY    : integer := PIX_Clock_Frequency; -- HZ
495
             VGA_HOR_CHARS          : integer := 80; -- CHARACTERS
496
             VGA_VER_CHARS          : integer := 25; -- CHARACTERS
497
             VGA_PIXELS_PER_CHAR    : integer := 8;  -- PIXELS
498
             VGA_LINES_PER_CHAR     : integer := 16; -- LINES
499
             VGA_HOR_BACK_PORCH     : integer := 40; -- PIXELS
500
             VGA_HOR_SYNC           : integer := 96; -- PIXELS
501
             VGA_HOR_FRONT_PORCH    : integer := 24; -- PIXELS
502
             VGA_VER_BACK_PORCH     : integer := 13; -- LINES
503
             VGA_VER_SYNC           : integer := 1;  -- LINES
504
             VGA_VER_FRONT_PORCH    : integer := 36  -- LINES
505
      );
506
      port(
507
                -- control register interface
508 22 dilbert57
      vdu_clk      : in  std_logic;      -- CPU Clock - 25MHz
509 19 dilbert57
      vdu_rst      : in  std_logic;
510
                vdu_cs       : in  std_logic;
511
                vdu_rw       : in  std_logic;
512
                vdu_addr     : in  std_logic_vector(2 downto 0);
513
      vdu_data_in  : in  std_logic_vector(7 downto 0);
514
      vdu_data_out : out std_logic_vector(7 downto 0);
515
 
516
      -- vga port connections
517
                vga_clk      : in  std_logic;   -- VGA Pixel Clock - 25 MHz
518
      vga_red_o    : out std_logic;
519
      vga_green_o  : out std_logic;
520
      vga_blue_o   : out std_logic;
521
      vga_hsync_o  : out std_logic;
522
      vga_vsync_o  : out std_logic
523
   );
524
end component;
525
 
526
 
527
----------------------------------------
528
--
529
-- Timer module
530
--
531
----------------------------------------
532
 
533
component timer
534
  port (
535
     clk       : in std_logic;
536
     rst       : in std_logic;
537
     cs        : in std_logic;
538
     rw        : in std_logic;
539
     addr      : in std_logic;
540
     data_in   : in std_logic_vector(7 downto 0);
541
          data_out  : out std_logic_vector(7 downto 0);
542 22 dilbert57
          irq       : out std_logic
543 19 dilbert57
          );
544
end component;
545
 
546
------------------------------------------------------------
547
--
548
-- Bus Trap logic
549
--
550
------------------------------------------------------------
551
 
552
component trap
553
        port (
554
         clk        : in  std_logic;
555
    rst        : in  std_logic;
556
    cs         : in  std_logic;
557
    rw         : in  std_logic;
558
    vma        : in  std_logic;
559
    addr       : in  std_logic_vector(15 downto 0);
560
    data_in    : in  std_logic_vector(7 downto 0);
561
         data_out   : out std_logic_vector(7 downto 0);
562
         irq        : out std_logic
563
  );
564
end component;
565
 
566 22 dilbert57
 
567 19 dilbert57
----------------------------------------
568
--
569 22 dilbert57
-- Dynamic Address Translation Registers
570 19 dilbert57
--
571
----------------------------------------
572 22 dilbert57
component dat_ram
573
  port (
574
    clk      : in  std_logic;
575
         rst      : in  std_logic;
576
         cs       : in  std_logic;
577
         rw       : in  std_logic;
578
         addr_lo  : in  std_logic_vector(3 downto 0);
579
         addr_hi  : in  std_logic_vector(3 downto 0);
580
    data_in  : in  std_logic_vector(7 downto 0);
581
         data_out : out std_logic_vector(7 downto 0)
582
  );
583
end component;
584
 
585
component XSASDRAMCntl
586
  generic(
587
    FREQ                 :     natural := FREQ;        -- operating frequency in KHz
588
    CLK_DIV              :     real    := CLK_DIV;     -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
589
    PIPE_EN              :     boolean := PIPE_EN;     -- if true, enable pipelined read operations
590
    MAX_NOP              :     natural := MAX_NOP;     -- number of NOPs before entering self-refresh
591
    MULTIPLE_ACTIVE_ROWS :     boolean := MULTIPLE_ACTIVE_ROWS;  -- if true, allow an active row in each bank
592
    DATA_WIDTH           :     natural := DATA_WIDTH;  -- host & SDRAM data width
593
    NROWS                :     natural := NROWS;       -- number of rows in SDRAM array
594
    NCOLS                :     natural := NCOLS;       -- number of columns in SDRAM array
595
    HADDR_WIDTH          :     natural := HADDR_WIDTH; -- host-side address width
596
    SADDR_WIDTH          :     natural := SADDR_WIDTH  -- SDRAM-side address width
597 19 dilbert57
    );
598 22 dilbert57
  port(
599
    -- host side
600
    clk                  : in  std_logic;  -- master clock
601
    bufclk               : out std_logic;  -- buffered master clock
602
    clk1x                : out std_logic;  -- host clock sync'ed to master clock (and divided if CLK_DIV>1)
603
    clk2x                : out std_logic;  -- double-speed host clock
604
    lock                 : out std_logic;  -- true when host clock is locked to master clock
605
    rst                  : in  std_logic;  -- reset
606
    rd                   : in  std_logic;  -- initiate read operation
607
    wr                   : in  std_logic;  -- initiate write operation
608
    earlyOpBegun         : out std_logic;  -- read/write/self-refresh op begun     (async)
609
    opBegun              : out std_logic;  -- read/write/self-refresh op begun (clocked)
610
    rdPending            : out std_logic;  -- read operation(s) are still in the pipeline
611
    done                 : out std_logic;  -- read or write operation is done
612
    rdDone               : out std_logic;  -- read done and data is available
613
    hAddr                : in  std_logic_vector(HADDR_WIDTH-1 downto 0);  -- address from host
614
    hDIn                 : in  std_logic_vector(DATA_WIDTH-1 downto 0);  -- data from host
615
    hDOut                : out std_logic_vector(DATA_WIDTH-1 downto 0);  -- data to host
616
    status               : out std_logic_vector(3 downto 0);  -- diagnostic status of the FSM         
617
 
618
    -- SDRAM side
619
    sclkfb               : in    std_logic;           -- clock from SDRAM after PCB delays
620
    sclk                 : out   std_logic;           -- SDRAM clock sync'ed to master clock
621
    cke                  : out   std_logic;           -- clock-enable to SDRAM
622
    cs_n                 : out   std_logic;           -- chip-select to SDRAM
623
    ras_n                : out   std_logic;           -- SDRAM row address strobe
624
    cas_n                : out   std_logic;           -- SDRAM column address strobe
625
    we_n                 : out   std_logic;           -- SDRAM write enable
626
    ba                   : out   std_logic_vector(1 downto 0);  -- SDRAM bank address bits
627
    sAddr                : out   std_logic_vector(SADDR_WIDTH-1 downto 0);  -- SDRAM row/column address
628
    sData                : inout std_logic_vector(DATA_WIDTH-1 downto 0);  -- SDRAM in/out databus
629
    dqmh                 : out   std_logic;           -- high databits I/O mask
630
    dqml                 : out   std_logic            -- low databits I/O mask
631
    );
632 19 dilbert57
end component;
633
 
634
--
635
-- Clock buffer
636
--
637
component BUFG
638
   Port (
639
     i: in std_logic;
640
          o: out std_logic
641
  );
642
end component;
643
 
644
begin
645
  -----------------------------------------------------------------------------
646
  -- Instantiation of internal components
647
  -----------------------------------------------------------------------------
648
 
649
my_cpu : cpu09  port map (
650
         clk         => cpu_clk,
651
    rst       => cpu_reset,
652 99 davidgb
    vma       => cpu_vma,
653
    addr   => cpu_addr(15 downto 0),
654 19 dilbert57
    rw       => cpu_rw,
655 99 davidgb
         data_out  => cpu_data_out,
656 19 dilbert57
    data_in   => cpu_data_in,
657
         irq       => cpu_irq,
658 99 davidgb
         firq      => cpu_firq,
659 19 dilbert57
         nmi       => cpu_nmi,
660 99 davidgb
         halt      => cpu_halt,
661
         hold      => cpu_hold
662 19 dilbert57
  );
663
 
664
my_rom : mon_rom port map (
665
       clk   => cpu_clk,
666
                 rst   => cpu_reset,
667
                 cs    => rom_cs,
668
                 rw    => '1',
669
       addr  => cpu_addr(11 downto 0),
670 95 davidgb
       data_in => cpu_data_out,
671
       data_out => rom_data_out
672 19 dilbert57
    );
673
 
674
my_flex : flex_ram port map (
675
    clk       => cpu_clk,
676
    rst       => cpu_reset,
677
         cs        => flex_cs,
678
         rw        => cpu_rw,
679
    addr      => cpu_addr(12 downto 0),
680 95 davidgb
    data_out     => flex_data_out,
681
    data_in     => cpu_data_out
682 19 dilbert57
    );
683
 
684 99 davidgb
my_acia  : acia6850 port map (
685 19 dilbert57
         clk         => cpu_clk,
686
         rst       => cpu_reset,
687 22 dilbert57
    cs        => acia_cs,
688 19 dilbert57
         rw        => cpu_rw,
689 99 davidgb
    addr      => cpu_addr(0),
690
         data_in    => cpu_data_out,
691
         data_out   => acia_data_out,
692 22 dilbert57
    irq       => acia_irq,
693 99 davidgb
 
694 22 dilbert57
         RxC       => acia_clk,
695
         TxC       => acia_clk,
696 19 dilbert57
         RxD       => rxd,
697
         TxD       => txd,
698
         DCD_n     => dcd_n,
699
         CTS_n     => cts_n,
700
         RTS_n     => rts_n
701
         );
702
 
703
 
704
my_ACIA_Clock : ACIA_Clock
705
  generic map(
706 99 davidgb
    SYS_CLK_FREQ  => SYS_Clock_Frequency,
707
         ACIA_CLK_FREQ => ACIA_Clock_Frequency
708 19 dilbert57
  )
709
  port map(
710 22 dilbert57
    clk        => Clk_i,
711
    acia_clk   => acia_clk
712 19 dilbert57
  );
713
 
714
----------------------------------------
715
--
716
-- PS/2 Keyboard Interface
717
--
718
----------------------------------------
719
my_keyboard : keyboard
720
   generic map (
721 99 davidgb
        KBD_CLK_FREQ => CPU_Clock_frequency
722 19 dilbert57
        )
723
   port map(
724
        clk          => cpu_clk,
725
        rst          => cpu_reset,
726
        cs           => keyboard_cs,
727
        rw           => cpu_rw,
728
        addr         => cpu_addr(0),
729
        data_in      => cpu_data_out(7 downto 0),
730
        data_out     => keyboard_data_out(7 downto 0),
731
        irq          => keyboard_irq,
732
        kbd_clk      => ps2_clk,
733
        kbd_data     => ps2_dat
734
        );
735
 
736
----------------------------------------
737
--
738
-- Video Display Unit instantiation
739
--
740
----------------------------------------
741 22 dilbert57
my_vdu : vdu8
742 19 dilbert57
  generic map(
743
      VDU_CLOCK_FREQUENCY    => CPU_Clock_Frequency, -- HZ
744
      VGA_CLOCK_FREQUENCY    => PIX_Clock_Frequency, -- HZ
745
           VGA_HOR_CHARS          => 80, -- CHARACTERS
746
           VGA_VER_CHARS          => 25, -- CHARACTERS
747
           VGA_PIXELS_PER_CHAR    => 8,  -- PIXELS
748
           VGA_LINES_PER_CHAR     => 16, -- LINES
749
           VGA_HOR_BACK_PORCH     => 40, -- PIXELS
750
           VGA_HOR_SYNC           => 96, -- PIXELS
751
           VGA_HOR_FRONT_PORCH    => 24, -- PIXELS
752
           VGA_VER_BACK_PORCH     => 13, -- LINES
753
           VGA_VER_SYNC           => 1,  -- LINES
754
           VGA_VER_FRONT_PORCH    => 36  -- LINES
755
  )
756
  port map(
757
 
758
                -- Control Registers
759
                vdu_clk       => cpu_clk,                                        -- 12.5 MHz System Clock in
760
      vdu_rst       => cpu_reset,
761
                vdu_cs        => vdu_cs,
762
                vdu_rw        => cpu_rw,
763
                vdu_addr      => cpu_addr(2 downto 0),
764
                vdu_data_in   => cpu_data_out,
765
                vdu_data_out  => vdu_data_out,
766
 
767
      -- vga port connections
768
      vga_clk       => pix_clk,                                  -- 25 MHz VDU pixel clock
769
      vga_red_o     => vga_red_o,
770
      vga_green_o   => vga_green_o,
771
      vga_blue_o    => vga_blue_o,
772
      vga_hsync_o   => vga_hsync_n,
773
      vga_vsync_o   => vga_vsync_n
774
   );
775
 
776
----------------------------------------
777
--
778
-- Timer Module
779
--
780
----------------------------------------
781
my_timer  : timer port map (
782
    clk       => cpu_clk,
783
         rst       => cpu_reset,
784
    cs        => timer_cs,
785
         rw        => cpu_rw,
786
    addr      => cpu_addr(0),
787
         data_in   => cpu_data_out,
788
         data_out  => timer_data_out,
789 22 dilbert57
    irq       => timer_irq
790 19 dilbert57
    );
791
 
792
----------------------------------------
793
--
794
-- Bus Trap Interrupt logic
795
--
796
----------------------------------------
797
my_trap : trap port map (
798
         clk        => cpu_clk,
799
    rst        => cpu_reset,
800
    cs         => trap_cs,
801
    rw         => cpu_rw,
802
         vma        => cpu_vma,
803
    addr       => cpu_addr,
804
    data_in    => cpu_data_out,
805
         data_out   => trap_data_out,
806
         irq        => trap_irq
807
    );
808
 
809
 
810 22 dilbert57
my_dat : dat_ram port map (
811
    clk       => cpu_clk,
812
         rst       => cpu_reset,
813
         cs        => dat_cs,
814
         rw        => cpu_rw,
815
         addr_hi   => cpu_addr(15 downto 12),
816
         addr_lo   => cpu_addr(3 downto 0),
817
    data_in   => cpu_data_out,
818
         data_out  => dat_addr(7 downto 0)
819
         );
820 19 dilbert57
 
821 22 dilbert57
  ------------------------------------------------------------------------
822
  -- Instantiate the SDRAM controller that connects to the memory tester
823
  -- module and interfaces to the external SDRAM chip.
824
  ------------------------------------------------------------------------
825
  u1 : xsaSDRAMCntl
826
    generic map(
827
      FREQ                 => FREQ,
828
      PIPE_EN              => PIPE_EN,
829
      DATA_WIDTH           => DATA_WIDTH,
830
      MULTIPLE_ACTIVE_ROWS => MULTIPLE_ACTIVE_ROWS,
831
      NROWS                => NROWS,
832
      NCOLS                => NCOLS,
833
      HADDR_WIDTH          => HADDR_WIDTH,
834
      SADDR_WIDTH          => SADDR_WIDTH
835
      )
836
    port map(
837
           -- Host Side
838
      clk                  => CLKA,     -- master clock from external clock source (unbuffered)
839
      bufclk               => open,     -- buffered master clock output
840
      clk1x                => clk_i,    -- synchronized master clock (accounts for delays to external SDRAM)
841
      clk2x                => open,     -- synchronized doubled master clock
842
      lock                 => lock,     -- DLL lock indicator
843
      rst                  => rst_i,    -- reset
844
      rd                   => hRd,      -- host-side SDRAM read control from memory tester
845
      wr                   => hWr,      -- host-side SDRAM write control from memory tester
846
      rdPending            => rdPending,-- read operation to SDRAM is in progress
847
      opBegun              => opBegun,  -- indicates memory read/write has begun
848
      earlyOpBegun         => earlyBegun,  -- early indicator that memory operation has begun
849
      rdDone               => rdDone,   -- indicates SDRAM memory read operation is done
850
      done                 => ramDone, -- indicates SDRAM memory read or write operation is done
851
      hAddr                => hAddr,    -- host-side address from memory tester to SDRAM
852
      hDIn                 => hDIn,     -- test data pattern from memory tester to SDRAM
853
      hDOut                => hDOut,    -- SDRAM data output to memory tester
854
      status               => open,     -- SDRAM controller state (for diagnostics)
855
                -- SDRAM Side
856
      sclkfb               => SDRAM_clkfb,    -- clock feedback with added external PCB delays
857
      sclk                 => SDRAM_clkout,   -- synchronized clock to external SDRAM
858
      cke                  => SDRAM_cke,      -- SDRAM clock enable
859
      cs_n                 => SDRAM_cs_n,     -- SDRAM chip-select
860
      ras_n                => SDRAM_ras_n,    -- SDRAM RAS
861
      cas_n                => SDRAM_cas_n,    -- SDRAM CAS
862
      we_n                 => SDRAM_we_n,     -- SDRAM write-enable
863
      ba                   => SDRAM_ba,       -- SDRAM bank address
864
      sAddr                => SDRAM_A,        -- SDRAM address
865
      sData                => SDRAM_D,        -- SDRAM databus
866
      dqmh                 => SDRAM_dqmh,     -- SDRAM DQMH
867
      dqml                 => SDRAM_dqml      -- SDRAM DQML
868
      );
869
 
870 19 dilbert57
cpu_clk_buffer : BUFG port map(
871
    i => Clk25,
872
         o => cpu_clk
873
    );
874
 
875
pix_clk_buffer : BUFG port map(
876
    i => Clk25,
877
         o => pix_clk
878
    );
879
 
880
----------------------------------------------------------------------
881
--
882
-- Process to decode memory map
883
--
884
----------------------------------------------------------------------
885
 
886
mem_decode: process( cpu_clk,
887
                     cpu_addr, cpu_rw, cpu_vma,
888 22 dilbert57
                                                        dat_addr,
889 19 dilbert57
                                              rom_data_out,
890
                                                        flex_data_out,
891 22 dilbert57
                                                   acia_data_out,
892 19 dilbert57
                                                        keyboard_data_out,
893
                                                        vdu_data_out,
894 22 dilbert57
                                                        pb_data_out,
895 19 dilbert57
                                                        timer_data_out,
896
                                                        trap_data_out,
897
                                                        ram_data_out
898
                                                        )
899
begin
900 22 dilbert57
      cpu_data_in <= (others=>'0');
901
      dat_cs      <= '0';
902
      rom_cs      <= '0';
903
      flex_cs     <= '0';
904
           acia_cs     <= '0';
905
           keyboard_cs <= '0';
906
           vdu_cs      <= '0';
907
           timer_cs    <= '0';
908
           trap_cs     <= '0';
909
           pb_cs       <= '0';
910
           ide_cs      <= '0';
911
           ether_cs    <= '0';
912
           slot1_cs    <= '0';
913
           slot2_cs    <= '0';
914
           ram_cs      <= '0';
915
      if cpu_addr( 15 downto 8 ) = "11111111" then
916
              cpu_data_in <= rom_data_out;
917
         dat_cs      <= cpu_vma;              -- write DAT
918
         rom_cs      <= cpu_vma;              -- read  ROM
919 19 dilbert57
           --
920
                -- Sys09Bug Monitor ROM $F000 - $FFFF
921
                --
922 22 dilbert57
           elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
923 19 dilbert57
                   cpu_data_in <= rom_data_out;
924
                        rom_cs      <= cpu_vma;
925
 
926
      --
927
                -- IO Devices $E000 - $E7FF
928
                --
929 22 dilbert57
                elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
930
                        case cpu_addr(11 downto 8) is
931 19 dilbert57
                        --
932 22 dilbert57
                        -- SWTPC peripherals from $E000 to $E0FF
933 19 dilbert57
                        --
934 22 dilbert57
                        when "0000" =>
935
                     case cpu_addr(7 downto 4) is
936
                          --
937
                          -- Console Port ACIA $E000 - $E00F
938
                          --
939
                          when "0000" => -- $E000
940
                       cpu_data_in <= acia_data_out;
941
                            acia_cs     <= cpu_vma;
942 19 dilbert57
 
943 22 dilbert57
           --
944
           -- Reserved
945
                          -- Floppy Disk Controller port $E010 - $E01F
946
                          --
947 19 dilbert57
 
948 22 dilbert57
           --
949
           -- Keyboard port $E020 - $E02F
950
                          --
951
                          when "0010" => -- $E020
952
             cpu_data_in <= keyboard_data_out;
953
                            keyboard_cs <= cpu_vma;
954 19 dilbert57
 
955 22 dilbert57
           --
956
           -- VDU port $E030 - $E03F
957
                          --
958
                          when "0011" => -- $E030
959
             cpu_data_in <= vdu_data_out;
960
                            vdu_cs      <= cpu_vma;
961 19 dilbert57
 
962 22 dilbert57
           --
963
                          -- Reserved SWTPc MP-T Timer $E040 - $E04F
964
                          --
965
                          when "0100" => -- $E040
966
             cpu_data_in <= (others=> '0');
967 19 dilbert57
 
968 22 dilbert57
           --
969
           -- Timer $E050 - $E05F
970
                          --
971
                          when "0101" => -- $E050
972
             cpu_data_in <= timer_data_out;
973
             timer_cs    <= cpu_vma;
974
 
975
           --
976
           -- Bus Trap Logic $E060 - $E06F
977
                          --
978
                          when "0110" => -- $E060
979
             cpu_data_in <= trap_data_out;
980
                            trap_cs     <= cpu_vma;
981
 
982
           --
983
                          -- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
984
                          --
985
 
986
           --
987
                          -- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
988
                          --
989
 
990
                          --
991
                          -- Remaining 6 slots reserved for non SWTPc Peripherals
992
                          --
993
                          when others => -- $E0A0 to $E0FF
994
                            null;
995
                     end case;
996 19 dilbert57
                        --
997 22 dilbert57
                        -- XST-3.0 Peripheral Bus goes here
998
                        --      $E100 to $E1FF
999
                        --      Four devices
1000
                        -- IDE, Ethernet, Slot1, Slot2
1001
                        --
1002
                        when "0001" =>
1003
                          cpu_data_in <= pb_data_out;
1004
                          pb_cs       <= cpu_vma;
1005
                     case cpu_addr(7 downto 6) is
1006
                          --
1007
                          -- IDE Interface $E100 to $E13F
1008
                          --
1009
                          when "00" =>
1010
                            ide_cs   <= cpu_vma;
1011
                          --
1012
                          -- Ethernet Interface $E140 to $E17F
1013
                          --
1014
                          when "01" =>
1015
                            ether_cs <= cpu_vma;
1016
                          --
1017
                          -- Slot 1 Interface $E180 to $E1BF
1018
                          --
1019
                          when "10" =>
1020
                            slot1_cs <= cpu_vma;
1021
                          --
1022
                          -- Slot 2 Interface $E1C0 to $E1FF
1023
                          --
1024
                          when "11" =>
1025
                            slot2_cs <= cpu_vma;
1026
           --
1027
                          -- Nothing else
1028
                          --
1029
           when others =>
1030
                            null;
1031
           end case;
1032 19 dilbert57
         --
1033 22 dilbert57
                        --      $E200 to $EFFF reserved for future use
1034 19 dilbert57
                        --
1035 22 dilbert57
                when others =>
1036
                          null;
1037
         end case;
1038 19 dilbert57
                --
1039 22 dilbert57
                -- Flex RAM $0C000 - $0DFFF
1040 19 dilbert57
                --
1041 22 dilbert57
                elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
1042
                   cpu_data_in <= flex_data_out;
1043 19 dilbert57
                        flex_cs     <= cpu_vma;
1044
                --
1045
                -- Everything else is RAM
1046
                --
1047 22 dilbert57
                else
1048
                   cpu_data_in <= ram_data_out;
1049
                   ram_cs      <= cpu_vma;
1050
          end if;
1051 19 dilbert57
end process;
1052
 
1053
 
1054
--
1055 22 dilbert57
-- 16-bit Peripheral Bus
1056
-- 6809 Big endian
1057
-- ISA bus little endian
1058
-- Not sure about IDE interface
1059 19 dilbert57
--
1060 22 dilbert57
peripheral_bus: process( clk_i, cpu_reset, cpu_rw, cpu_addr, cpu_data_out )
1061 19 dilbert57
begin
1062 22 dilbert57
  pb_wru <= pb_cs and (not cpu_rw) and (not cpu_addr(0));
1063
  pb_wrl <= pb_cs and (not cpu_rw) and      cpu_addr(0) ;
1064
  pb_rdu <= pb_cs and      cpu_rw  and (not cpu_addr(0));
1065
  pb_rdl <= pb_cs and      cpu_rw  and      cpu_addr(0) ;
1066
  pb_a   <= cpu_addr(5 downto 1);
1067
 
1068
  --
1069
  -- Register upper byte from CPU on first CPU write
1070
  -- and lower byte from the peripheral bus on first CPU read
1071
  --
1072
  if cpu_reset = '1' then
1073
    pb_wreg <= (others => '0');
1074
    pb_rreg <= (others => '0');
1075
  elsif clk_i'event and clk_i ='1' then
1076
    if pb_wru = '1' then
1077
           pb_wreg <= cpu_data_out;
1078
    end if;
1079
    if pb_rdu = '1' then
1080
           pb_rreg <= pb_d(7 downto 0);
1081
    end if;
1082
   end if;
1083
  --
1084
  -- Peripheral bus read and write strobes are
1085
  -- Syncronized with the 50 MHz clock
1086
  -- and are asserted until the peripheral bus hold is released
1087
  --
1088
  if cpu_reset = '1' then
1089
    pb_wr_n <= '1';
1090
    pb_rd_n <= '1';
1091
  elsif clk_i'event and clk_i ='1' then
1092
         if pb_hold = '1' then
1093
           pb_wr_n  <= not pb_wrl;
1094
           pb_rd_n  <= not pb_rdu;
1095
    else
1096
      pb_wr_n <= '1';
1097
      pb_rd_n <= '1';
1098
    end if;
1099
  end if;
1100
  --
1101
  -- The peripheral bus will be an output 
1102
  -- the registered even byte on data(15 downto 8)
1103
  -- and the CPU odd bytes on data(7 downto 0)
1104
  -- on odd byte writes
1105
  --
1106
  if pb_wrl = '1' then
1107
    pb_d <= pb_wreg & cpu_data_out;
1108
  else
1109
    pb_d <= (others => 'Z');
1110
  end if;
1111
 
1112
  --
1113
  -- On even byte reads,
1114
  -- the CPU reads the low (even) byte of the peripheral bus
1115
  -- On odd byte reads,
1116
  -- the CPU reads the registered (odd byte) input from the peripheral bus
1117
  --
1118
  if pb_rdu = '1' then
1119
    pb_data_out <= pb_d(15 downto 8);
1120
  elsif pb_rdl = '1' then
1121
    pb_data_out <= pb_rreg;
1122
  else
1123
    pb_data_out <= (others => '0');
1124
  end if;
1125
 
1126 19 dilbert57
end process;
1127
 
1128
--
1129 22 dilbert57
-- Hold Peripheral bus accesses for a few cycles
1130 19 dilbert57
--
1131 22 dilbert57
peripheral_bus_hold: process( cpu_clk, cpu_reset, pb_rdu, pb_wrl, ether_rdy )
1132 19 dilbert57
begin
1133 22 dilbert57
    if cpu_reset = '1' then
1134
                 pb_release    <= '0';
1135
                 pb_count      <= "0000";
1136
            pb_hold_state <= hold_release_state;
1137
         elsif cpu_clk'event and cpu_clk='1' then
1138
  --
1139
  -- The perpheral bus hold signal should be generated on 
1140
  -- 16 bit bus read which will be on even byte reads or 
1141
  -- 16 bit bus write which will be on odd byte writes.
1142
  -- 
1143
            case pb_hold_state is
1144 19 dilbert57
                 when hold_release_state =>
1145 22 dilbert57
          pb_release <= '0';
1146
                    if (pb_rdu = '1') or (pb_wrl = '1') then
1147
                            pb_count      <= "0100";
1148
                                 pb_hold_state <= hold_request_state;
1149
          elsif (pb_rdl = '1') or (pb_wru = '1') then
1150
             pb_release    <= '1';
1151
                                 pb_hold_state <= hold_release_state;
1152 19 dilbert57
                         end if;
1153
 
1154
                 when hold_request_state =>
1155 22 dilbert57
                         if pb_count = "0000" then
1156
            if ether_rdy = '1' then
1157
              pb_release    <= '1';
1158
                                  pb_hold_state <= hold_release_state;
1159
            end if;
1160
          else
1161
                       pb_count <= pb_count - "0001";
1162 19 dilbert57
                         end if;
1163
       when others =>
1164
                    null;
1165
       end case;
1166
         end if;
1167
end process;
1168
 
1169
--
1170 22 dilbert57
-- Compact Flash Control
1171
--
1172
compact_flash: process( ide_cs, cpu_addr )
1173
begin
1174
         ide_cs0_n  <= not( ide_cs ) or cpu_addr(4);
1175
         ide_cs1_n  <= not( ide_cs and cpu_addr(4));
1176
         ide_dmack_n  <= '1';
1177
end process;
1178
 
1179
--
1180 19 dilbert57
-- Interrupts and other bus control signals
1181
--
1182 22 dilbert57
interrupts : process( lock, rst_n, nmi_n,
1183
                                                         pb_cs, pb_hold, pb_release,
1184
                                                         ram_cs, ram_hold,
1185
                                                         ether_irq,
1186
                      acia_irq,
1187 19 dilbert57
                                                         keyboard_irq,
1188
                                                         trap_irq,
1189
                                                         timer_irq
1190
                                                         )
1191
begin
1192 22 dilbert57
         cpu_reset <= (not rst_n) or (not lock); -- CPU reset is active high
1193
    pb_hold   <= pb_cs and (not pb_release);
1194
    cpu_irq   <= acia_irq or keyboard_irq;
1195 19 dilbert57
         cpu_nmi   <= trap_irq or not( nmi_n );
1196
         cpu_firq  <= timer_irq;
1197
         cpu_halt  <= '0';
1198 22 dilbert57
         cpu_hold  <= pb_hold or ram_hold;
1199 19 dilbert57
end process;
1200
 
1201
 
1202
--
1203
-- Flash 7 segment LEDS
1204
--
1205 22 dilbert57
my_led_flasher: process( Clk_i, rst_n, CountL )
1206 19 dilbert57
begin
1207
    if rst_n = '0' then
1208
                   CountL <= "000000000000000000000000";
1209 22 dilbert57
    elsif(Clk_i'event and Clk_i = '1') then
1210 19 dilbert57
                   CountL <= CountL + 1;
1211
    end if;
1212 22 dilbert57
--       S(7 downto 0) <= CountL(23 downto 16);
1213 19 dilbert57
end process;
1214
 
1215
--
1216 22 dilbert57
-- Generate a 25 MHz Clock from 50 MHz
1217 19 dilbert57
--
1218 22 dilbert57
my_prescaler : process( Clk_i, clk_count )
1219 19 dilbert57
begin
1220 22 dilbert57
  if Clk_i'event and Clk_i = '1' then
1221
    clk_count(0) <= not clk_count(0);
1222 19 dilbert57
  end if;
1223 22 dilbert57
  Clk25 <= clk_count(0);
1224 19 dilbert57
end process;
1225
 
1226
--
1227
-- Push buttons
1228
--
1229 22 dilbert57
my_switch_assignments : process( SW2_N, SW3_N, rst_n )
1230 19 dilbert57
begin
1231
  rst_n    <= SW2_N;
1232 22 dilbert57
  rst_i    <= not rst_n;
1233 19 dilbert57
  nmi_n    <= SW3_N;
1234
  --
1235 22 dilbert57
  -- Disable Flash memory
1236 19 dilbert57
  --
1237 22 dilbert57
  FLASH_CE_N    <= '1';
1238 19 dilbert57
end process;
1239
 
1240
--
1241
-- RS232 signals:
1242
--
1243 22 dilbert57
my_acia_assignments : process( RS232_RXD, RS232_CTS, txd, rts_n )
1244 19 dilbert57
begin
1245
  rxd       <= RS232_RXD;
1246
  cts_n     <= RS232_CTS;
1247
  dcd_n     <= '0';
1248
  RS232_TXD <= txd;
1249
  RS232_RTS <= rts_n;
1250
end process;
1251
 
1252
--
1253 22 dilbert57
-- Pin assignments for ethernet controller
1254
--
1255
my_ethernet_assignments : process( clk_i, cpu_reset, ether_cs )
1256
begin
1257
    ether_cs_n  <= not ether_cs;
1258
    ether_aen   <= not ether_cs; -- Ethernet address enable not 
1259
    ether_bhe_n <= '1';          -- Ethernet bus high enable - 8 bit access only
1260
end process;
1261
 
1262
--
1263
-- I/O expansion slot assignments
1264
--
1265
my_slot_assignments : process( slot1_cs, slot2_cs)
1266
begin
1267
    slot1_cs_n <= not slot1_cs;
1268
    slot2_cs_n <= not slot2_cs;
1269
end process;
1270
 
1271
--
1272 19 dilbert57
-- VGA ouputs
1273
--
1274
my_vga_assignments : process( vga_red_o, vga_green_o, vga_blue_o )
1275
begin
1276
  VGA_red(0)   <= vga_red_o;
1277
  VGA_red(1)   <= vga_red_o;
1278
  VGA_red(2)   <= vga_red_o;
1279
  VGA_green(0) <= vga_green_o;
1280
  VGA_green(1) <= vga_green_o;
1281
  VGA_green(2) <= vga_green_o;
1282
  VGA_blue(0)  <= vga_blue_o;
1283
  VGA_blue(1)  <= vga_blue_o;
1284
  VGA_blue(2)  <= vga_blue_o;
1285
end process;
1286
 
1287 22 dilbert57
--
1288
-- SDRAM assignments
1289
--
1290
my_sdram_assignments : process( cpu_clk, clk_i, cpu_reset,
1291
                                opBegun, rdDone, wrDone,
1292
                                                                                  ram_rd_state, ram_wr_state,
1293
                                cpu_addr, dat_addr,
1294
                                cpu_data_out, hDout,
1295
                                                                                  ram_cs, cpu_rw, ram_hold )
1296
begin
1297
  if( cpu_reset = '1' ) then
1298
    hWr    <= '0';
1299
         hRd    <= '0';
1300
         wrDone <= '0';
1301
         ram_wr_state <= wr_state0;
1302
         ram_rd_state <= rd_state0;
1303 19 dilbert57
 
1304 22 dilbert57
  elsif( clk_i'event and clk_i='0' ) then
1305
    --
1306
         -- read state machine
1307
         --
1308
    case ram_rd_state is
1309
 
1310
    when rd_state0 =>
1311
           if (ram_hold = '1') and (cpu_rw = '1') then
1312
                  hRd          <= '1';
1313
                  ram_rd_state <= rd_state1;
1314
      end if;
1315
 
1316
    when rd_state1 =>
1317
           if opBegun = '1' then
1318
                  ram_rd_state <= rd_state2;
1319
      end if;
1320
 
1321
    when rd_state2 =>
1322
           if rdDone = '1' then
1323
                  hRd <= '0';
1324
                  ram_rd_state <= rd_state3;
1325
                end if;
1326
 
1327
    when rd_state3 =>
1328
           if rdDone = '0' then
1329
                  ram_rd_state <= rd_state0;
1330
      end if;
1331
 
1332
         when others =>
1333
                hRd          <= '0';
1334
                ram_rd_state <= rd_state0;
1335
         end case;
1336
 
1337
         --
1338
         -- Write state machine
1339
         --
1340
    case ram_wr_state is
1341
 
1342
    when wr_state0 =>
1343
           if (ram_hold = '1') and (cpu_rw = '0') then
1344
                  hWr          <= '1';
1345
        wrDone       <= '0';
1346
                  ram_wr_state <= wr_state1;
1347
      end if;
1348
 
1349
    when wr_state1 =>
1350
           if opBegun = '1' then
1351
                  hWr          <= '0';
1352
        wrDone       <= '0';
1353
                  ram_wr_state <= wr_state2;
1354
      end if;
1355
 
1356
    when wr_state2 =>
1357
                hWr          <= '0';
1358
      wrDone       <= '0';
1359
                ram_wr_state <= wr_state3;
1360
 
1361
    when wr_state3 =>
1362
                hWr          <= '0';
1363
      wrDone       <= '1';
1364
                ram_wr_state <= wr_state4;
1365
 
1366
    when wr_state4 =>
1367
                hWr          <= '0';
1368
      wrDone       <= '0';
1369
                ram_wr_state <= wr_state0;
1370
 
1371
         when others =>
1372
                hWr          <= '0';
1373
      wrDone       <= '0';
1374
                ram_wr_state <= wr_state0;
1375
 
1376
         end case;
1377
 
1378
  end if;
1379
  --
1380
  -- Strobe host RD and WR signals high on RAM select
1381
  -- Return low when cycle has started
1382
  --
1383
  if( cpu_reset = '1' ) then
1384
         ram_hold     <= '0';
1385
  elsif( cpu_clk'event and cpu_clk='1' ) then
1386
    --
1387
    -- Hold is intitiated when the RAM is selected
1388
    -- and released when access cycle is complete
1389
    -- 
1390
         if (ram_hold = '0') and (ram_cs = '1') then
1391
                ram_hold <= '1';
1392
    elsif (ram_hold = '1') and ((rdDone = '1') or (wrDone = '1')) then
1393
                ram_hold <= '0';
1394
    end if;
1395
  end if;
1396
 
1397
  hAddr(23 downto 20) <= "0000";
1398
  hAddr(19 downto 12) <= dat_addr;
1399
  hAddr(11 downto 0)  <= cpu_addr(11 downto 0);
1400
  hDin(7 downto 0)    <= cpu_data_out;
1401
  hDin(15 downto 8)   <= (others => '0');
1402
  ram_data_out        <= hDout(7 downto 0);
1403
 
1404
end process;
1405
 
1406 19 dilbert57
end rtl; --===================== End of architecture =======================--
1407
 

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