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[/] [System09/] [trunk/] [rtl/] [System09_Xess_XSA-3S1000/] [System09_Xess_XSA-3S1000.vhd] - Blame information for rev 223

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1 19 dilbert57
--===========================================================================----
2
--
3
--  S Y N T H E Z I A B L E    System09 - SOC.
4
--
5
--  www.OpenCores.Org - February 2007
6
--  This core adheres to the GNU public license  
7
--
8
-- File name      : System09_Xess_XSA-3S1000.vhd
9
--
10
-- Purpose        : Top level file for 6809 compatible system on a chip
11
--                  Designed with Xilinx XC3S1000 Spartan 3 FPGA.
12
--                  Implemented With XESS XSA-3S1000 FPGA board.
13
--                  *** Note ***
14
--                  This configuration can run Flex9 however it only has
15
--                  32k bytes of user memory and the VDU is monochrome
16
--                  The design needs to be updated to use the SDRAM on 
17
--                  the XSA-3S1000 board.
18
--                  This configuration also lacks a DAT so cannot use
19
--                  the RAM Disk features of SYS09BUG.
20
--
21
-- Dependencies   : ieee.Std_Logic_1164
22
--                  ieee.std_logic_unsigned
23
--                  ieee.std_logic_arith
24
--                  ieee.numeric_std
25
--                  unisim.vcomponents
26
--
27
-- Uses           : mon_rom    (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
28
--                  cpu09      (cpu09.vhd)          CPU core
29 99 davidgb
--                  ACIA_6850  (acia6850.vhd)      ACIA / UART
30 19 dilbert57
--                  ACIA_Clock (ACIA_Clock.vhd)      ACIA clock.
31
--                  keyboard   (keyboard.vhd)        PS/2 Keyboard interface
32
--                             (ps2_keyboard.vhd)
33
--                             (keymap_rom_slice.vhd) Key map table 
34
--                  vdu8_mono  (vdu8_mono.vhd)        Monochrome VDU
35
--                             (char_rom2k_b16.vhd)
36
--                             (ram2k_b16.vhd)
37
--                  timer      (timer.vhd)            Interrupt timer
38
--                  trap       (trap.vhd)             Bus condition trap logic
39
--                  flex_ram   (flex9_ram8k_b16.vhd)  Flex operating system
40
--                  ram_32K    (ram32k_b16.vhd)       32 KBytes of Block RAM
41
--                  
42
-- 
43
-- Author         : John E. Kent      
44
--                  dilbert57@opencores.org      
45
--
46
-- Memory Map     :
47
--
48
-- $0000 - User program RAM (32K Bytes)
49
-- $C000 - Flex Operating System memory (8K Bytes)
50
-- $E000 - ACIA (SWTPc)
51
-- $E010 - Reserved for FD1771 FDC (SWTPc)
52
-- $E020 - Keyboard
53
-- $E030 - VDU
54
-- $E040 - IDE / Compact Flash interface
55
-- $E050 - Timer
56
-- $E060 - Bus trap
57
-- $E070 - Reserced for Parallel I/O (B5-X300)
58
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
59
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
60
-- $F000 - Sys09Bug monitor Program (4K Bytes)
61
--
62
--===========================================================================----
63
--
64
-- Revision History:
65
--===========================================================================--
66
-- Version 0.1 - 20 March 2003
67
-- Version 0.2 - 30 March 2003
68
-- Version 0.3 - 29 April 2003
69
-- Version 0.4 - 29 June 2003
70
--
71
-- Version 0.5 - 19 July 2003
72
-- prints out "Hello World"
73
--
74
-- Version 0.6 - 5 September 2003
75
-- Runs SBUG
76
--
77
-- Version 1.0- 6 Sep 2003 - John Kent
78
-- Inverted SysClk
79
-- Initial release to Open Cores
80
--
81
-- Version 1.1 - 17 Jan 2004 - John Kent
82
-- Updated miniUart.
83
--
84
-- Version 1.2 - 25 Jan 2004 - John Kent
85
-- removed signals "test_alu" and "test_cc" 
86
-- Trap hardware re-instated.
87
--
88
-- Version 1.3 - 11 Feb 2004 - John Kent
89
-- Designed forked off to produce System09_VDU
90
-- Added VDU component
91 134 davidgb
-- VDU runs at 25MHz and divides the clock by 2 for the CPU
92 19 dilbert57
-- UART Runs at 57.6 Kbps
93
--
94
-- Version 2.0 - 2 September 2004 - John Kent
95
-- ported to Digilent Xilinx Spartan3 starter board
96 134 davidgb
-- removed Compact Flash and Trap Logic.
97 19 dilbert57
-- Replaced SBUG with KBug9s
98
--
99
-- Version 3.0 - 29th August 2006 - John Kent
100
-- Adapted to XSA-3S1000 board.
101
-- Removed DAT and miniUART.
102
-- Used 32KBytes of Block RAM.
103
--
104
-- Version 3.1 - 15th January 2007 - John Kent
105
-- Modified vdu8 interface
106
-- Added a clock divider
107
--
108
-- Version 3.2 - 25th February 2007 - John Kent
109
-- reinstated ACIA_6850 and ACIA_Clock
110
-- Updated VDU8 & Keyboard with generic parameters
111
-- Defined Constants for clock speed calculations
112
--
113
-- Version 3.3 - 1st July 2007 - John Kent
114
-- Made VDU mono to save on one RAMB16
115
-- Used distributed memory for Key Map ROM to save one RAMB16
116
-- Added Flex RAM at $C000 to $DFFF using 4 spare RAMB16s
117
-- Added timer and trap logic
118
-- Added IDE Interface for Compact Flash
119
-- Replaced KBug9s and stack with Sys09Bug.
120
--
121 22 dilbert57
-- Version 4.0 - 1st February 2008 - John kent
122
-- Replaced Block RAM with SDRAM Interface
123
-- Modified Hold timing for SDRAM
124
-- Added CF and Ethernet interface 
125
-- via the 16 bit peripheral bus at $E100
126
--
127 19 dilbert57
--===========================================================================--
128
library ieee;
129
   use ieee.std_logic_1164.all;
130
   use IEEE.STD_LOGIC_ARITH.ALL;
131
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
132
   use ieee.numeric_std.all;
133 22 dilbert57
library work;
134 134 davidgb
   use work.common.all;
135
   use WORK.xsasdram.all;
136 19 dilbert57
library unisim;
137
   use unisim.vcomponents.all;
138
 
139 114 davidgb
entity system09 is
140 19 dilbert57
  port(
141 115 davidgb
    CLKA         : in  Std_Logic;  -- 100MHz Clock input
142
--    CLKB         : in  Std_Logic;  -- 50MHz Clock input
143 134 davidgb
    SW2_N        : in  Std_logic;  -- Master Reset input (active low)
144
    SW3_N        : in  Std_logic;  -- Non Maskable Interrupt input (active low)
145 19 dilbert57
 
146 134 davidgb
    -- PS/2 Keyboard
147
    ps2_clk      : inout Std_logic;
148
    ps2_dat      : inout Std_Logic;
149 19 dilbert57
 
150 134 davidgb
    -- CRTC output signals
151
    vga_vsync_n  : out Std_Logic;
152 22 dilbert57
    vga_hsync_n  : out Std_Logic;
153
    vga_blue     : out std_logic_vector(2 downto 0);
154
    vga_green    : out std_logic_vector(2 downto 0);
155
    vga_red      : out std_logic_vector(2 downto 0);
156 19 dilbert57
 
157
    -- RS232 Port
158 134 davidgb
    RS232_RXD    : in  Std_Logic;
159
    RS232_TXD    : out Std_Logic;
160 22 dilbert57
    RS232_CTS    : in  Std_Logic;
161
    RS232_RTS    : out Std_Logic;
162 19 dilbert57
 
163 134 davidgb
    -- Status 7 segment LED
164
    S            : out std_logic_vector(7 downto 0);
165 19 dilbert57
 
166 22 dilbert57
    -- SDRAM side
167
    SDRAM_clkfb  : in  std_logic;            -- feedback SDRAM clock after PCB delays
168
    SDRAM_clkout : out std_logic;            -- clock to SDRAM
169
    SDRAM_CKE    : out std_logic;            -- clock-enable to SDRAM
170
    SDRAM_CS_N   : out std_logic;            -- chip-select to SDRAM
171
    SDRAM_RAS_N  : out std_logic;            -- SDRAM row address strobe
172
    SDRAM_CAS_N  : out std_logic;            -- SDRAM column address strobe
173
    SDRAM_WE_N   : out std_logic;            -- SDRAM write enable
174
    SDRAM_BA     : out std_logic_vector(1 downto 0);  -- SDRAM bank address
175
    SDRAM_A      : out std_logic_vector(12 downto 0);  -- SDRAM row/column address
176
    SDRAM_D      : inout  std_logic_vector(15 downto 0);  -- data from SDRAM
177
    SDRAM_DQMH   : out std_logic;            -- enable upper-byte of SDRAM databus if true
178
    SDRAM_DQML   : out std_logic;            -- enable lower-byte of SDRAM databus if true
179
 
180 134 davidgb
    -- Peripheral I/O bus $E100 - $E1FF
181 22 dilbert57
    PB_RD_N      : out std_logic;
182
    PB_WR_N      : out std_logic;
183
    PB_A         : out std_logic_vector(4 downto 0);
184
    PB_D         : inout std_logic_vector(15 downto 0);
185
 
186
    -- IDE Compact Flash $E100 - $E13F
187
    ide_dmack_n  : out std_logic;
188 134 davidgb
    ide_cs0_n    : out std_logic;
189
    ide_cs1_n    : out std_logic;
190 22 dilbert57
 
191
    -- Ethernet $E140 - $E17F
192 115 davidgb
    ether_cs_n   : out std_logic;
193 22 dilbert57
    ether_aen    : out std_logic; -- Ethernet address enable not 
194
    ether_bhe_n  : out std_logic; -- Ethernet bus high enable 
195
    ether_clk    : in  std_logic; -- Ethernet clock 
196
    ether_rdy    : in  std_logic; -- Ethernet ready
197 115 davidgb
    ether_irq    : in  std_logic; -- Ethernet irq - Shared with BAR6
198 22 dilbert57
 
199
    -- Slot 1 $E180 - $E1BF
200 134 davidgb
    slot1_cs_n   : out std_logic;
201
--  slot1_irq    : in  std_logic;
202 22 dilbert57
 
203
    -- Slot 2 $E1C0 - $E1FF
204 134 davidgb
    slot2_cs_n   : out std_logic;
205
--  slot2_irq    : in  std_logic;
206
 
207 115 davidgb
-- CPU Debug Interface signals
208
--    cpu_reset_o     : out Std_Logic;
209
--    cpu_clk_o       : out Std_Logic;
210
--    cpu_rw_o        : out std_logic;
211
--    cpu_vma_o       : out std_logic;
212
--    cpu_halt_o      : out std_logic;
213
--    cpu_hold_o      : out std_logic;
214
--    cpu_firq_o      : out std_logic;
215
--    cpu_irq_o       : out std_logic;
216
--    cpu_nmi_o       : out std_logic;
217
--    cpu_addr_o      : out std_logic_vector(15 downto 0);
218
--    cpu_data_in_o   : out std_logic_vector(7 downto 0);
219
--    cpu_data_out_o  : out std_logic_vector(7 downto 0);
220 22 dilbert57
 
221 134 davidgb
    -- Disable Flash
222
    FLASH_CE_N   : out std_logic
223
  );
224 114 davidgb
end system09;
225 19 dilbert57
 
226
-------------------------------------------------------------------------------
227
-- Architecture for System09
228
-------------------------------------------------------------------------------
229 114 davidgb
architecture rtl of system09 is
230 19 dilbert57
 
231
  -----------------------------------------------------------------------------
232
  -- constants
233 134 davidgb
  -----------------------------------------------------------------------------
234
 
235 115 davidgb
  -- SDRAM
236
  constant MEM_CLK_FREQ         : natural := 100_000; -- operating frequency of Memory in KHz
237
  constant SYS_CLK_DIV          : real    := 2.0;    -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
238
  constant PIPE_EN              : boolean := false;  -- if true, enable pipelined read operations
239
  constant MAX_NOP              : natural := 10000;  -- number of NOPs before entering self-refresh
240
  constant MULTIPLE_ACTIVE_ROWS : boolean := false;  -- if true, allow an active row in each bank
241
  constant DATA_WIDTH           : natural := 16;     -- host & SDRAM data width
242
  constant NROWS                : natural := 8192;   -- number of rows in SDRAM array
243
  constant NCOLS                : natural := 512;    -- number of columns in SDRAM array
244
  constant HADDR_WIDTH          : natural := 24;     -- host-side address width
245
  constant SADDR_WIDTH          : natural := 13;     -- SDRAM-side address width
246 19 dilbert57
 
247 115 davidgb
  constant SYS_CLK_FREQ         : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000;  -- FPGA System Clock
248 134 davidgb
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
249 115 davidgb
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
250
  constant VGA_CLK_FREQ         : natural := 25_000_000;  -- VGA Pixel Clock
251
  constant VGA_CLK_DIV          : natural := ((MEM_CLK_FREQ*1000)/VGA_CLK_FREQ);
252 134 davidgb
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
253
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
254
 
255
  constant TRESET               : natural := 300;      -- min initialization interval (us)
256 115 davidgb
  constant RST_CYCLES           : natural := 1+(TRESET*(MEM_CLK_FREQ/1_000));  -- SDRAM power-on initialization interval
257
 
258 19 dilbert57
  type hold_state_type is ( hold_release_state, hold_request_state );
259
 
260
  -----------------------------------------------------------------------------
261
  -- Signals
262
  -----------------------------------------------------------------------------
263
  -- BOOT ROM
264
  signal rom_cs         : Std_logic;
265
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
266
 
267
  -- Flex Memory & Monitor Stack
268
  signal flex_cs        : Std_logic;
269
  signal flex_data_out  : Std_Logic_Vector(7 downto 0);
270
 
271
  -- ACIA/UART Interface signals
272 22 dilbert57
  signal acia_data_out  : Std_Logic_Vector(7 downto 0);
273
  signal acia_cs        : Std_Logic;
274
  signal acia_irq       : Std_Logic;
275
  signal acia_clk       : Std_Logic;
276 19 dilbert57
  signal rxd            : Std_Logic;
277
  signal txd            : Std_Logic;
278
  signal DCD_n          : Std_Logic;
279
  signal RTS_n          : Std_Logic;
280
  signal CTS_n          : Std_Logic;
281
 
282
  -- keyboard port
283
  signal keyboard_data_out : std_logic_vector(7 downto 0);
284
  signal keyboard_cs       : std_logic;
285
  signal keyboard_irq      : std_logic;
286
 
287
  -- RAM
288
  signal ram_cs         : std_logic; -- memory chip select
289
  signal ram_data_out   : std_logic_vector(7 downto 0);
290 134 davidgb
  signal ram_rd_req     : std_logic; -- ram read request (asynch set on ram read, cleared falling CPU clock edge)
291 115 davidgb
  signal ram_wr_req     : std_logic; -- ram write request (set on rising CPU clock edge, asynch clear on acknowledge) 
292 22 dilbert57
  signal ram_hold       : std_logic; -- hold off slow accesses
293 115 davidgb
  signal ram_release    : std_logic; -- Release ram hold
294 19 dilbert57
 
295
  -- CPU Interface signals
296
  signal cpu_reset      : Std_Logic;
297
  signal cpu_clk        : Std_Logic;
298
  signal cpu_rw         : std_logic;
299
  signal cpu_vma        : std_logic;
300
  signal cpu_halt       : std_logic;
301
  signal cpu_hold       : std_logic;
302
  signal cpu_firq       : std_logic;
303
  signal cpu_irq        : std_logic;
304
  signal cpu_nmi        : std_logic;
305
  signal cpu_addr       : std_logic_vector(15 downto 0);
306
  signal cpu_data_in    : std_logic_vector(7 downto 0);
307
  signal cpu_data_out   : std_logic_vector(7 downto 0);
308
 
309 22 dilbert57
  -- Dynamic Address Translation
310
  signal dat_cs       : std_logic;
311
  signal dat_addr     : std_logic_vector(7 downto 0);
312
 
313 19 dilbert57
  -- Video Display Unit
314
  signal vdu_cs         : std_logic;
315
  signal vdu_data_out   : std_logic_vector(7 downto 0);
316
  signal vga_red_o      : std_logic;
317
  signal vga_green_o    : std_logic;
318
  signal vga_blue_o     : std_logic;
319
 
320
  -- timer
321
  signal timer_data_out : std_logic_vector(7 downto 0);
322
  signal timer_cs       : std_logic;
323
  signal timer_irq      : std_logic;
324
 
325
  -- trap
326
  signal trap_cs        : std_logic;
327
  signal trap_data_out  : std_logic_vector(7 downto 0);
328
  signal trap_irq       : std_logic;
329
 
330 22 dilbert57
  -- Peripheral Bus port
331
  signal pb_data_out   : std_logic_vector(7 downto 0);
332 134 davidgb
  signal pb_cs         : std_logic;   -- peripheral bus chip select
333
  signal pb_wru        : std_logic;   -- upper byte write strobe
334
  signal pb_wrl        : std_logic;   -- lower byte write strobe
335
  signal pb_rdu        : std_logic;   -- upper byte read strobe
336
  signal pb_rdl        : std_logic;   -- lower byte read strobe
337
  signal pb_hold       : std_logic;   -- hold peripheral bus access
338
  signal pb_release    : std_logic;   -- release hold of peripheral bus
339 22 dilbert57
  signal pb_count      : std_logic_vector(3 downto 0); -- hold counter
340
  signal pb_hold_state : hold_state_type;
341
  signal pb_wreg       : std_logic_vector(7 downto 0); -- lower byte write register
342
  signal pb_rreg       : std_logic_vector(7 downto 0); -- lower byte read register
343 19 dilbert57
 
344 22 dilbert57
  -- Peripheral chip selects on Peripheral Bus
345
  signal ide_cs        : std_logic; -- IDE CF interface
346 134 davidgb
  signal ether_cs      : std_logic; -- Ethernet interface
347
  signal slot1_cs      : std_logic; -- Expansion slot 1
348
  signal slot2_cs      : std_logic; -- Expansion slot 2
349 22 dilbert57
 
350 115 davidgb
  signal rst_i         : std_logic;     -- internal reset signal
351
  signal clk_i         : std_logic;     -- internal master clock signal
352
  signal lock          : std_logic;     -- SDRAM clock DLL lock indicator
353 22 dilbert57
 
354
  -- signals that go through the SDRAM host-side interface
355 115 davidgb
  signal opBegun       : std_logic;        -- SDRAM operation started indicator
356
  signal earlyBegun    : std_logic;        -- SDRAM operation started indicator
357
  signal ramDone       : std_logic;        -- SDRAM operation complete indicator
358
  signal rdDone        : std_logic;        -- SDRAM read operation complete indicator
359
  signal wrDone        : std_logic;        -- SDRAM write operation complete indicator
360
  signal hAddr         : std_logic_vector(HADDR_WIDTH-1 downto 0);  -- host address bus
361
  signal hDIn          : std_logic_vector(DATA_WIDTH-1 downto 0);  -- host-side data to SDRAM
362
  signal hDOut         : std_logic_vector(DATA_WIDTH-1 downto 0);  -- host-side data from SDRAM
363
  signal hRd           : std_logic;        -- host-side read control signal
364
  signal hWr           : std_logic;        -- host-side write control signal
365 134 davidgb
  signal hUds          : std_logic;        -- host-side upper data strobe
366
  signal hLds          : std_logic;        -- host-side lower data strobe
367 115 davidgb
  signal rdPending     : std_logic;        -- read operation pending in SDRAM pipeline
368 134 davidgb
  type ram_type is (ram_state_0,
369
                    ram_state_rd1, ram_state_rd2,
370
                    ram_state_wr1,
371
                    ram_state_3 );
372 115 davidgb
  signal ram_state     : ram_type;
373 22 dilbert57
 
374 115 davidgb
  signal CountL        : std_logic_vector(23 downto 0);
375
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
376
  signal Clk25         : std_logic;
377
  signal vga_clk       : std_logic;
378 19 dilbert57
 
379
-----------------------------------------------------------------
380
--
381
-- CPU09 CPU core
382
--
383
-----------------------------------------------------------------
384
 
385
component cpu09
386
  port (
387 134 davidgb
    clk:      in  std_logic;
388
    rst:      in  std_logic;
389
    vma:      out std_logic;
390
    addr:     out std_logic_vector(15 downto 0);
391
    rw:       out std_logic;     -- Asynchronous memory interface
392
    data_out: out std_logic_vector(7 downto 0);
393
    data_in:  in  std_logic_vector(7 downto 0);
394
    irq:      in  std_logic;
395
    firq:     in  std_logic;
396
    nmi:      in  std_logic;
397
    halt:     in  std_logic;
398
    hold:     in  std_logic
399 19 dilbert57
  );
400
end component;
401
 
402
----------------------------------------
403
--
404
-- 4K Block RAM Monitor ROM
405 134 davidgb
-- $F000 - $FFFF
406 19 dilbert57
--
407
----------------------------------------
408 134 davidgb
 
409 19 dilbert57
component mon_rom
410 134 davidgb
  Port (
411
    clk   : in  std_logic;
412
    rst   : in  std_logic;
413
    cs    : in  std_logic;
414
    rw    : in  std_logic;
415
    addr  : in  std_logic_vector (11 downto 0);
416
    data_out : out std_logic_vector (7 downto 0);
417
    data_in : in  std_logic_vector (7 downto 0)
418
  );
419 19 dilbert57
end component;
420
 
421
----------------------------------------
422
--
423
-- 8KBytes Block RAM for FLEX9
424
-- $C000 - $DFFF
425
--
426
----------------------------------------
427 134 davidgb
 
428 19 dilbert57
component flex_ram
429
  Port (
430
    clk      : in  std_logic;
431
    rst      : in  std_logic;
432
    cs       : in  std_logic;
433
    rw       : in  std_logic;
434
    addr     : in  std_logic_vector (12 downto 0);
435 95 davidgb
    data_out    : out std_logic_vector (7 downto 0);
436
    data_in    : in  std_logic_vector (7 downto 0)
437 134 davidgb
  );
438 19 dilbert57
end component;
439
 
440
-----------------------------------------------------------------
441
--
442
-- 6850 Compatible ACIA / UART
443
--
444
-----------------------------------------------------------------
445
 
446 99 davidgb
component acia6850
447 19 dilbert57
  port (
448 134 davidgb
    clk      : in  Std_Logic;  -- System Clock
449
    rst      : in  Std_Logic;  -- Reset input (active high)
450
    cs       : in  Std_Logic;  -- miniUART Chip Select
451
    rw       : in  Std_Logic;  -- Read / Not Write
452
    addr     : in  Std_Logic;  -- Register Select
453
    data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
454
    data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
455
    irq      : out Std_Logic;  -- Interrupt
456
    RxC      : in  Std_Logic;  -- Receive Baud Clock
457
    TxC      : in  Std_Logic;  -- Transmit Baud Clock
458
    RxD      : in  Std_Logic;  -- Receive Data
459
    TxD      : out Std_Logic;  -- Transmit Data
460
    DCD_n    : in  Std_Logic;  -- Data Carrier Detect
461
    CTS_n    : in  Std_Logic;  -- Clear To Send
462
    RTS_n    : out Std_Logic   -- Request To send
463
  );
464 19 dilbert57
end component;
465
 
466
-----------------------------------------------------------------
467
--
468
-- ACIA Clock divider
469
--
470
-----------------------------------------------------------------
471
 
472
component ACIA_Clock
473
  generic (
474 134 davidgb
    SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
475
    ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
476 19 dilbert57
  );
477
  port (
478 134 davidgb
    clk      : in  Std_Logic;  -- System Clock Input
479
    ACIA_clk : out Std_logic   -- ACIA Clock output
480 19 dilbert57
  );
481
end component;
482
 
483
----------------------------------------
484
--
485
-- PS/2 Keyboard
486
--
487
----------------------------------------
488
 
489
component keyboard
490
  generic(
491 134 davidgb
    KBD_CLK_FREQ : integer := CPU_CLK_FREQ
492 19 dilbert57
  );
493
  port(
494 134 davidgb
    clk             : in    std_logic;
495
    rst             : in    std_logic;
496
    cs              : in    std_logic;
497
    rw              : in    std_logic;
498
    addr            : in    std_logic;
499
    data_in         : in    std_logic_vector(7 downto 0);
500
    data_out        : out   std_logic_vector(7 downto 0);
501
    irq             : out   std_logic;
502
    kbd_clk         : inout std_logic;
503
    kbd_data        : inout std_logic
504 19 dilbert57
  );
505
end component;
506
 
507
----------------------------------------
508
--
509
-- Video Display Unit.
510
--
511
----------------------------------------
512 134 davidgb
 
513 22 dilbert57
component vdu8
514 134 davidgb
  generic(
515
    VDU_CLK_FREQ           : integer := CPU_CLK_FREQ; -- HZ
516
    VGA_CLK_FREQ           : integer := VGA_CLK_FREQ; -- HZ
517
    VGA_HOR_CHARS          : integer := 80; -- CHARACTERS
518
    VGA_VER_CHARS          : integer := 25; -- CHARACTERS
519
    VGA_PIX_PER_CHAR       : integer := 8;  -- PIXELS
520
    VGA_LIN_PER_CHAR       : integer := 16; -- LINES
521
    VGA_HOR_BACK_PORCH     : integer := 40; -- PIXELS
522
    VGA_HOR_SYNC           : integer := 96; -- PIXELS
523
    VGA_HOR_FRONT_PORCH    : integer := 24; -- PIXELS
524
    VGA_VER_BACK_PORCH     : integer := 13; -- LINES
525
    VGA_VER_SYNC           : integer := 2;  -- LINES
526
    VGA_VER_FRONT_PORCH    : integer := 35  -- LINES
527
  );
528
  port(
529
    -- control register interface
530
    vdu_clk      : in  std_logic;  -- CPU Clock - 25MHz
531
    vdu_rst      : in  std_logic;
532
    vdu_cs       : in  std_logic;
533
    vdu_rw       : in  std_logic;
534
    vdu_addr     : in  std_logic_vector(2 downto 0);
535
    vdu_data_in  : in  std_logic_vector(7 downto 0);
536
    vdu_data_out : out std_logic_vector(7 downto 0);
537 19 dilbert57
 
538 134 davidgb
    -- vga port connections
539
    vga_clk      : in  std_logic; -- VGA Pixel Clock - 25 MHz
540
    vga_red_o    : out std_logic;
541
    vga_green_o  : out std_logic;
542
    vga_blue_o   : out std_logic;
543
    vga_hsync_o  : out std_logic;
544
    vga_vsync_o  : out std_logic
545
  );
546 19 dilbert57
end component;
547
 
548
----------------------------------------
549
--
550
-- Timer module
551
--
552
----------------------------------------
553
 
554
component timer
555
  port (
556 134 davidgb
    clk       : in std_logic;
557
    rst       : in std_logic;
558
    cs        : in std_logic;
559
    rw        : in std_logic;
560
    addr      : in std_logic;
561
    data_in   : in std_logic_vector(7 downto 0);
562
    data_out  : out std_logic_vector(7 downto 0);
563
    irq       : out std_logic
564
  );
565 19 dilbert57
end component;
566
 
567
------------------------------------------------------------
568
--
569
-- Bus Trap logic
570
--
571
------------------------------------------------------------
572
 
573
component trap
574 134 davidgb
  port (
575
    clk        : in  std_logic;
576 19 dilbert57
    rst        : in  std_logic;
577
    cs         : in  std_logic;
578
    rw         : in  std_logic;
579
    vma        : in  std_logic;
580
    addr       : in  std_logic_vector(15 downto 0);
581
    data_in    : in  std_logic_vector(7 downto 0);
582 134 davidgb
    data_out   : out std_logic_vector(7 downto 0);
583
    irq        : out std_logic
584 19 dilbert57
  );
585
end component;
586
 
587
----------------------------------------
588
--
589 22 dilbert57
-- Dynamic Address Translation Registers
590 19 dilbert57
--
591
----------------------------------------
592 134 davidgb
 
593 22 dilbert57
component dat_ram
594
  port (
595
    clk      : in  std_logic;
596 134 davidgb
    rst      : in  std_logic;
597
    cs       : in  std_logic;
598
    rw       : in  std_logic;
599
    addr_lo  : in  std_logic_vector(3 downto 0);
600
    addr_hi  : in  std_logic_vector(3 downto 0);
601 22 dilbert57
    data_in  : in  std_logic_vector(7 downto 0);
602 134 davidgb
    data_out : out std_logic_vector(7 downto 0)
603 22 dilbert57
  );
604
end component;
605
 
606 134 davidgb
----------------------------------------
607
--
608
-- SDRAM Controller for XSA-3S1000
609
--
610
----------------------------------------
611
 
612 22 dilbert57
component XSASDRAMCntl
613
  generic(
614 115 davidgb
    FREQ                 :     natural := MEM_CLK_FREQ;-- operating frequency in KHz
615
    CLK_DIV              :     real    := SYS_CLK_DIV; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
616 22 dilbert57
    PIPE_EN              :     boolean := PIPE_EN;     -- if true, enable pipelined read operations
617
    MAX_NOP              :     natural := MAX_NOP;     -- number of NOPs before entering self-refresh
618
    MULTIPLE_ACTIVE_ROWS :     boolean := MULTIPLE_ACTIVE_ROWS;  -- if true, allow an active row in each bank
619
    DATA_WIDTH           :     natural := DATA_WIDTH;  -- host & SDRAM data width
620
    NROWS                :     natural := NROWS;       -- number of rows in SDRAM array
621
    NCOLS                :     natural := NCOLS;       -- number of columns in SDRAM array
622
    HADDR_WIDTH          :     natural := HADDR_WIDTH; -- host-side address width
623
    SADDR_WIDTH          :     natural := SADDR_WIDTH  -- SDRAM-side address width
624 134 davidgb
  );
625 22 dilbert57
  port(
626
    -- host side
627
    clk                  : in  std_logic;  -- master clock
628
    bufclk               : out std_logic;  -- buffered master clock
629
    clk1x                : out std_logic;  -- host clock sync'ed to master clock (and divided if CLK_DIV>1)
630
    clk2x                : out std_logic;  -- double-speed host clock
631
    lock                 : out std_logic;  -- true when host clock is locked to master clock
632
    rst                  : in  std_logic;  -- reset
633
    rd                   : in  std_logic;  -- initiate read operation
634
    wr                   : in  std_logic;  -- initiate write operation
635 134 davidgb
    uds                  : in  std_logic;  -- upper data strobe
636
    lds                  : in  std_logic;  -- lower data strobe
637 22 dilbert57
    earlyOpBegun         : out std_logic;  -- read/write/self-refresh op begun     (async)
638
    opBegun              : out std_logic;  -- read/write/self-refresh op begun (clocked)
639
    rdPending            : out std_logic;  -- read operation(s) are still in the pipeline
640
    done                 : out std_logic;  -- read or write operation is done
641
    rdDone               : out std_logic;  -- read done and data is available
642
    hAddr                : in  std_logic_vector(HADDR_WIDTH-1 downto 0);  -- address from host
643
    hDIn                 : in  std_logic_vector(DATA_WIDTH-1 downto 0);  -- data from host
644
    hDOut                : out std_logic_vector(DATA_WIDTH-1 downto 0);  -- data to host
645
    status               : out std_logic_vector(3 downto 0);  -- diagnostic status of the FSM         
646
 
647
    -- SDRAM side
648
    sclkfb               : in    std_logic;           -- clock from SDRAM after PCB delays
649
    sclk                 : out   std_logic;           -- SDRAM clock sync'ed to master clock
650
    cke                  : out   std_logic;           -- clock-enable to SDRAM
651
    cs_n                 : out   std_logic;           -- chip-select to SDRAM
652
    ras_n                : out   std_logic;           -- SDRAM row address strobe
653
    cas_n                : out   std_logic;           -- SDRAM column address strobe
654
    we_n                 : out   std_logic;           -- SDRAM write enable
655
    ba                   : out   std_logic_vector(1 downto 0);  -- SDRAM bank address bits
656
    sAddr                : out   std_logic_vector(SADDR_WIDTH-1 downto 0);  -- SDRAM row/column address
657
    sData                : inout std_logic_vector(DATA_WIDTH-1 downto 0);  -- SDRAM in/out databus
658
    dqmh                 : out   std_logic;           -- high databits I/O mask
659
    dqml                 : out   std_logic            -- low databits I/O mask
660 134 davidgb
  );
661 19 dilbert57
end component;
662 134 davidgb
 
663 19 dilbert57
--
664
-- Clock buffer
665
--
666 134 davidgb
 
667 19 dilbert57
component BUFG
668
   Port (
669
     i: in std_logic;
670 134 davidgb
     o: out std_logic
671 19 dilbert57
  );
672
end component;
673
 
674
begin
675 134 davidgb
 
676 19 dilbert57
  -----------------------------------------------------------------------------
677
  -- Instantiation of internal components
678
  -----------------------------------------------------------------------------
679
 
680 134 davidgb
  my_cpu : cpu09
681
    port map (
682
      clk       => cpu_clk,
683
      rst       => cpu_reset,
684
      vma       => cpu_vma,
685
      addr      => cpu_addr(15 downto 0),
686
      rw        => cpu_rw,
687
      data_out  => cpu_data_out,
688
      data_in   => cpu_data_in,
689
      irq       => cpu_irq,
690
      firq      => cpu_firq,
691
      nmi       => cpu_nmi,
692
      halt      => cpu_halt,
693
      hold      => cpu_hold
694
    );
695 19 dilbert57
 
696 134 davidgb
  my_rom : mon_rom
697
    port map (
698
      clk   => cpu_clk,
699
      rst   => cpu_reset,
700
      cs    => rom_cs,
701
      rw    => '1',
702
      addr  => cpu_addr(11 downto 0),
703
      data_in => cpu_data_out,
704
      data_out => rom_data_out
705 19 dilbert57
    );
706
 
707 134 davidgb
  my_flex : flex_ram
708
    port map (
709
      clk       => cpu_clk,
710
      rst       => cpu_reset,
711
      cs        => flex_cs,
712
      rw        => cpu_rw,
713
      addr      => cpu_addr(12 downto 0),
714
      data_out     => flex_data_out,
715
      data_in     => cpu_data_out
716 19 dilbert57
    );
717
 
718 134 davidgb
  my_acia  : acia6850
719
    port map (
720
      clk       => cpu_clk,
721
      rst       => cpu_reset,
722
      cs        => acia_cs,
723
      rw        => cpu_rw,
724
      addr      => cpu_addr(0),
725
      data_in   => cpu_data_out,
726
      data_out  => acia_data_out,
727
      irq       => acia_irq,
728
      RxC       => acia_clk,
729
      TxC       => acia_clk,
730
      RxD       => rxd,
731
      TxD       => txd,
732
      DCD_n     => dcd_n,
733
      CTS_n     => cts_n,
734
      RTS_n     => rts_n
735
    );
736 19 dilbert57
 
737 134 davidgb
  my_ACIA_Clock : ACIA_Clock
738
    generic map(
739
      SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
740
      ACIA_CLK_FREQ => ACIA_CLK_FREQ
741
    )
742
    port map(
743
      clk        => Clk_i,
744
      acia_clk   => acia_clk
745
    );
746 19 dilbert57
 
747 134 davidgb
  ----------------------------------------
748
  --
749
  -- PS/2 Keyboard Interface
750
  --
751
  ----------------------------------------
752
  my_keyboard : keyboard
753
    generic map (
754
      KBD_CLK_FREQ => CPU_CLK_FREQ
755
    )
756
    port map(
757
      clk          => cpu_clk,
758
      rst          => cpu_reset,
759
      cs           => keyboard_cs,
760
      rw           => cpu_rw,
761
      addr         => cpu_addr(0),
762
      data_in      => cpu_data_out(7 downto 0),
763
      data_out     => keyboard_data_out(7 downto 0),
764
      irq          => keyboard_irq,
765
      kbd_clk      => ps2_clk,
766
      kbd_data     => ps2_dat
767
    );
768 19 dilbert57
 
769 134 davidgb
  ----------------------------------------
770
  --
771
  -- Video Display Unit instantiation
772
  --
773
  ----------------------------------------
774
  my_vdu : vdu8
775
    generic map(
776 115 davidgb
      VDU_CLK_FREQ           => CPU_CLK_FREQ, -- HZ
777
      VGA_CLK_FREQ           => VGA_CLK_FREQ, -- HZ
778 134 davidgb
      VGA_HOR_CHARS          => 80, -- CHARACTERS
779
      VGA_VER_CHARS          => 25, -- CHARACTERS
780
      VGA_PIX_PER_CHAR       => 8,  -- PIXELS
781
      VGA_LIN_PER_CHAR       => 16, -- LINES
782
      VGA_HOR_BACK_PORCH     => 40, -- PIXELS
783
      VGA_HOR_SYNC           => 96, -- PIXELS
784
      VGA_HOR_FRONT_PORCH    => 24, -- PIXELS
785
      VGA_VER_BACK_PORCH     => 13, -- LINES
786
      VGA_VER_SYNC           => 2,  -- LINES
787
      VGA_VER_FRONT_PORCH    => 35  -- LINES
788
    )
789
    port map(
790
      -- Control Registers
791
      vdu_clk       => cpu_clk,               -- 12.5 MHz System Clock in
792 19 dilbert57
      vdu_rst       => cpu_reset,
793 134 davidgb
      vdu_cs        => vdu_cs,
794
      vdu_rw        => cpu_rw,
795
      vdu_addr      => cpu_addr(2 downto 0),
796
      vdu_data_in   => cpu_data_out,
797
      vdu_data_out  => vdu_data_out,
798 19 dilbert57
      -- vga port connections
799 134 davidgb
      vga_clk       => vga_clk,               -- 25 MHz VDU pixel clock
800 19 dilbert57
      vga_red_o     => vga_red_o,
801
      vga_green_o   => vga_green_o,
802
      vga_blue_o    => vga_blue_o,
803
      vga_hsync_o   => vga_hsync_n,
804
      vga_vsync_o   => vga_vsync_n
805
   );
806
 
807 134 davidgb
  ----------------------------------------
808
  --
809
  -- Timer Module
810
  --
811
  ----------------------------------------
812
  my_timer  : timer
813
    port map (
814
      clk       => cpu_clk,
815
      rst       => cpu_reset,
816
      cs        => timer_cs,
817
      rw        => cpu_rw,
818
      addr      => cpu_addr(0),
819
      data_in   => cpu_data_out,
820
      data_out  => timer_data_out,
821
      irq       => timer_irq
822 19 dilbert57
    );
823
 
824 134 davidgb
  ----------------------------------------
825
  --
826
  -- Bus Trap Interrupt logic
827
  --
828
  ----------------------------------------
829
  my_trap : trap
830
    port map (
831
      clk        => cpu_clk,
832
      rst        => cpu_reset,
833
      cs         => trap_cs,
834
      rw         => cpu_rw,
835
      vma        => cpu_vma,
836
      addr       => cpu_addr,
837
      data_in    => cpu_data_out,
838
      data_out   => trap_data_out,
839
      irq        => trap_irq
840 19 dilbert57
    );
841
 
842 134 davidgb
  my_dat : dat_ram
843
    port map (
844
      clk       => cpu_clk,
845
      rst       => cpu_reset,
846
      cs        => dat_cs,
847
      rw        => cpu_rw,
848
      addr_hi   => cpu_addr(15 downto 12),
849
      addr_lo   => cpu_addr(3 downto 0),
850
      data_in   => cpu_data_out,
851
      data_out  => dat_addr(7 downto 0)
852
    );
853 19 dilbert57
 
854 22 dilbert57
  ------------------------------------------------------------------------
855
  -- Instantiate the SDRAM controller that connects to the memory tester
856
  -- module and interfaces to the external SDRAM chip.
857
  ------------------------------------------------------------------------
858
  u1 : xsaSDRAMCntl
859
    generic map(
860 134 davidgb
      FREQ                 => MEM_CLK_FREQ,
861
      CLK_DIV              => SYS_CLK_DIV,
862
      PIPE_EN              => PIPE_EN,
863
      MAX_NOP              => MAX_NOP,
864 115 davidgb
      MULTIPLE_ACTIVE_ROWS => MULTIPLE_ACTIVE_ROWS,
865 22 dilbert57
      DATA_WIDTH           => DATA_WIDTH,
866
      NROWS                => NROWS,
867
      NCOLS                => NCOLS,
868
      HADDR_WIDTH          => HADDR_WIDTH,
869
      SADDR_WIDTH          => SADDR_WIDTH
870 134 davidgb
    )
871 22 dilbert57
    port map(
872 134 davidgb
      -- Host Side
873 22 dilbert57
      clk                  => CLKA,     -- master clock from external clock source (unbuffered)
874
      bufclk               => open,     -- buffered master clock output
875
      clk1x                => clk_i,    -- synchronized master clock (accounts for delays to external SDRAM)
876
      clk2x                => open,     -- synchronized doubled master clock
877
      lock                 => lock,     -- DLL lock indicator
878
      rst                  => rst_i,    -- reset
879
      rd                   => hRd,      -- host-side SDRAM read control from memory tester
880
      wr                   => hWr,      -- host-side SDRAM write control from memory tester
881 134 davidgb
      uds                  => hUds,     -- host-side SDRAM upper data strobe
882
      lds                  => hLds,     -- host-side SDRAM lower data strobe
883 22 dilbert57
      rdPending            => rdPending,-- read operation to SDRAM is in progress
884
      opBegun              => opBegun,  -- indicates memory read/write has begun
885
      earlyOpBegun         => earlyBegun,  -- early indicator that memory operation has begun
886
      rdDone               => rdDone,   -- indicates SDRAM memory read operation is done
887
      done                 => ramDone, -- indicates SDRAM memory read or write operation is done
888
      hAddr                => hAddr,    -- host-side address from memory tester to SDRAM
889
      hDIn                 => hDIn,     -- test data pattern from memory tester to SDRAM
890
      hDOut                => hDOut,    -- SDRAM data output to memory tester
891
      status               => open,     -- SDRAM controller state (for diagnostics)
892 134 davidgb
      -- SDRAM Side
893 22 dilbert57
      sclkfb               => SDRAM_clkfb,    -- clock feedback with added external PCB delays
894
      sclk                 => SDRAM_clkout,   -- synchronized clock to external SDRAM
895
      cke                  => SDRAM_cke,      -- SDRAM clock enable
896
      cs_n                 => SDRAM_cs_n,     -- SDRAM chip-select
897
      ras_n                => SDRAM_ras_n,    -- SDRAM RAS
898
      cas_n                => SDRAM_cas_n,    -- SDRAM CAS
899
      we_n                 => SDRAM_we_n,     -- SDRAM write-enable
900
      ba                   => SDRAM_ba,       -- SDRAM bank address
901
      sAddr                => SDRAM_A,        -- SDRAM address
902
      sData                => SDRAM_D,        -- SDRAM databus
903
      dqmh                 => SDRAM_dqmh,     -- SDRAM DQMH
904
      dqml                 => SDRAM_dqml      -- SDRAM DQML
905 134 davidgb
    );
906 19 dilbert57
 
907 134 davidgb
  cpu_clk_buffer : BUFG
908
    port map(
909
      i => Clk25,
910
      o => cpu_clk
911
    );
912 19 dilbert57
 
913 134 davidgb
  vga_clk_buffer : BUFG
914
    port map(
915
      i => Clk25,
916
      o => vga_clk
917
    );
918
 
919
  ----------------------------------------------------------------------
920
  --
921
  -- Process to decode memory map
922
  --
923
  ----------------------------------------------------------------------
924 19 dilbert57
 
925 134 davidgb
  mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
926
                     dat_addr,
927
                     rom_data_out,
928
                     flex_data_out,
929
                     acia_data_out,
930
                     keyboard_data_out,
931
                     vdu_data_out,
932
                     pb_data_out,
933
                     timer_data_out,
934
                     trap_data_out,
935
                     ram_data_out
936
                     )
937
  begin
938
    cpu_data_in <= (others=>'0');
939
    dat_cs      <= '0';
940
    rom_cs      <= '0';
941
    flex_cs     <= '0';
942
    acia_cs     <= '0';
943
    keyboard_cs <= '0';
944
    vdu_cs      <= '0';
945
    timer_cs    <= '0';
946
    trap_cs     <= '0';
947
    pb_cs       <= '0';
948
    ide_cs      <= '0';
949
    ether_cs    <= '0';
950
    slot1_cs    <= '0';
951
    slot2_cs    <= '0';
952
    ram_cs      <= '0';
953 19 dilbert57
 
954 134 davidgb
    if cpu_addr( 15 downto 8 ) = "11111111" then  -- $FFxx
955
      cpu_data_in <= rom_data_out;
956
      dat_cs      <= cpu_vma;              -- write DAT
957
      rom_cs      <= cpu_vma;              -- read  ROM
958 19 dilbert57
 
959 134 davidgb
    --
960
    -- Sys09Bug Monitor ROM $F000 - $FFFF
961
    --
962
    elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
963
      cpu_data_in <= rom_data_out;
964
      rom_cs      <= cpu_vma;
965 19 dilbert57
 
966 134 davidgb
    --
967
    -- IO Devices $E000 - $E7FF
968
    --
969
    elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
970
      case cpu_addr(11 downto 8) is
971
        --
972
        -- SWTPC peripherals from $E000 to $E0FF
973
        --
974
        when "0000" =>
975
          case cpu_addr(7 downto 4) is
976
          --
977
          -- Console Port ACIA $E000 - $E00F
978
          --
979
            when "0000" => -- $E000
980
              cpu_data_in <= acia_data_out;
981
              acia_cs     <= cpu_vma;
982 19 dilbert57
 
983 134 davidgb
            --
984
            -- Reserved
985
            -- Floppy Disk Controller port $E010 - $E01F
986
            --
987 19 dilbert57
 
988 134 davidgb
            --
989
            -- Keyboard port $E020 - $E02F
990
            --
991
            when "0010" => -- $E020
992
              cpu_data_in <= keyboard_data_out;
993
              keyboard_cs <= cpu_vma;
994 22 dilbert57
 
995 134 davidgb
            --
996
            -- VDU port $E030 - $E03F
997
            --
998
            when "0011" => -- $E030
999
              cpu_data_in <= vdu_data_out;
1000
              vdu_cs      <= cpu_vma;
1001 22 dilbert57
 
1002 134 davidgb
            --
1003
            -- Reserved SWTPc MP-T Timer $E040 - $E04F
1004
            --
1005
            when "0100" => -- $E040
1006
              cpu_data_in <= (others=> '0');
1007 22 dilbert57
 
1008 134 davidgb
            --
1009
            -- Timer $E050 - $E05F
1010
            --
1011
            when "0101" => -- $E050
1012
              cpu_data_in <= timer_data_out;
1013
              timer_cs    <= cpu_vma;
1014 22 dilbert57
 
1015 134 davidgb
            --
1016
            -- Bus Trap Logic $E060 - $E06F
1017
            --
1018
            when "0110" => -- $E060
1019
              cpu_data_in <= trap_data_out;
1020
              trap_cs     <= cpu_vma;
1021 19 dilbert57
 
1022 134 davidgb
            --
1023
            -- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
1024
            --
1025 19 dilbert57
 
1026 134 davidgb
            --
1027
            -- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
1028
            --
1029 22 dilbert57
 
1030 134 davidgb
            --
1031
            -- Remaining 6 slots reserved for non SWTPc Peripherals
1032
            --
1033
            when others => -- $E0A0 to $E0FF
1034
              null;
1035
          end case;
1036
 
1037
        --
1038
        -- XST-3.0 Peripheral Bus goes here
1039
        -- $E100 to $E1FF
1040
        -- Four devices
1041
        -- IDE, Ethernet, Slot1, Slot2
1042
        --
1043
        when "0001" =>
1044
          cpu_data_in <= pb_data_out;
1045
          pb_cs       <= cpu_vma;
1046
          case cpu_addr(7 downto 6) is
1047
            --
1048
            -- IDE Interface $E100 to $E13F
1049
            --
1050
            when "00" =>
1051
              ide_cs   <= cpu_vma;
1052
            --
1053
            -- Ethernet Interface $E140 to $E17F
1054
            --
1055
            when "01" =>
1056
              ether_cs <= cpu_vma;
1057
            --
1058
            -- Slot 1 Interface $E180 to $E1BF
1059
            --
1060
            when "10" =>
1061
              slot1_cs <= cpu_vma;
1062
            --
1063
            -- Slot 2 Interface $E1C0 to $E1FF
1064
            --
1065
            when "11" =>
1066
              slot2_cs <= cpu_vma;
1067
            --
1068
            -- Nothing else
1069
            --
1070
            when others =>
1071
              null;
1072
          end case;
1073
 
1074
        --
1075
        -- $E200 to $EFFF reserved for future use
1076
        --
1077
        when others =>
1078
           null;
1079
      end case;
1080
 
1081
    --
1082
    -- Flex RAM $0C000 - $0DFFF
1083
    --
1084
    elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
1085
      cpu_data_in <= flex_data_out;
1086
      flex_cs     <= cpu_vma;
1087
 
1088
    --
1089
    -- Everything else is RAM
1090
    --
1091
    else
1092
      cpu_data_in <= ram_data_out;
1093
      ram_cs      <= cpu_vma;
1094
    end if;
1095
 
1096
  end process;
1097
 
1098 22 dilbert57
  --
1099 134 davidgb
  -- 16-bit Peripheral Bus
1100
  -- 6809 Big endian
1101
  -- ISA bus little endian
1102
  -- Not sure about IDE interface
1103 22 dilbert57
  --
1104 134 davidgb
  peripheral_bus: process( clk_i, cpu_reset, cpu_rw, cpu_addr, cpu_data_out,
1105
                         pb_cs, pb_wreg, pb_rreg )
1106
  begin
1107
    pb_wru <= pb_cs and (not cpu_rw) and (not cpu_addr(0));
1108
    pb_wrl <= pb_cs and (not cpu_rw) and      cpu_addr(0) ;
1109
    pb_rdu <= pb_cs and      cpu_rw  and (not cpu_addr(0));
1110
    pb_rdl <= pb_cs and      cpu_rw  and      cpu_addr(0) ;
1111
    pb_a   <= cpu_addr(5 downto 1);
1112
 
1113
    --
1114
    -- Register upper byte from CPU on first CPU write
1115
    -- and lower byte from the peripheral bus on first CPU read
1116
    --
1117
    if cpu_reset = '1' then
1118
      pb_wreg <= (others => '0');
1119
      pb_rreg <= (others => '0');
1120
    elsif clk_i'event and clk_i ='1' then
1121
      if pb_wru = '1' then
1122
        pb_wreg <= cpu_data_out;
1123
      end if;
1124
      if pb_rdu = '1' then
1125
        pb_rreg <= pb_d(7 downto 0);
1126
      end if;
1127 22 dilbert57
    end if;
1128 134 davidgb
    --
1129
    -- Peripheral bus read and write strobes are
1130
    -- Syncronized with the 50 MHz clock
1131
    -- and are asserted until the peripheral bus hold is released
1132
    --
1133
    if cpu_reset = '1' then
1134 22 dilbert57
      pb_wr_n <= '1';
1135
      pb_rd_n <= '1';
1136 134 davidgb
    elsif clk_i'event and clk_i ='1' then
1137
      if pb_hold = '1' then
1138
        pb_wr_n  <= not pb_wrl;
1139
        pb_rd_n  <= not pb_rdu;
1140
      else
1141
        pb_wr_n <= '1';
1142
        pb_rd_n <= '1';
1143
      end if;
1144 22 dilbert57
    end if;
1145 134 davidgb
    --
1146
    -- The peripheral bus will be an output 
1147
    -- the registered even byte on data(15 downto 8)
1148
    -- and the CPU odd bytes on data(7 downto 0)
1149
    -- on odd byte writes
1150
    --
1151
    if pb_wrl = '1' then
1152
      pb_d <= pb_wreg & cpu_data_out;
1153
    else
1154
      pb_d <= (others => 'Z');
1155
    end if;
1156 22 dilbert57
 
1157 134 davidgb
    --
1158
    -- On even byte reads,
1159
    -- the CPU reads the low (even) byte of the peripheral bus
1160
    -- On odd byte reads,
1161
    -- the CPU reads the registered (odd byte) input from the peripheral bus
1162
    --
1163
    if pb_rdu = '1' then
1164
      pb_data_out <= pb_d(15 downto 8);
1165
    elsif pb_rdl = '1' then
1166
      pb_data_out <= pb_rreg;
1167
    else
1168
      pb_data_out <= (others => '0');
1169
    end if;
1170
 
1171
  end process;
1172
 
1173 22 dilbert57
  --
1174 134 davidgb
  -- Hold Peripheral bus accesses for a few cycles
1175 22 dilbert57
  --
1176 134 davidgb
  peripheral_bus_hold: process( cpu_clk, cpu_reset, pb_rdu, pb_wrl ) --, ether_rdy )
1177
  begin
1178 22 dilbert57
    if cpu_reset = '1' then
1179 134 davidgb
      pb_release    <= '0';
1180
      pb_count      <= "0000";
1181
      pb_hold_state <= hold_release_state;
1182
    elsif rising_edge(cpu_clk) then
1183
      --
1184
      -- The perpheral bus hold signal should be generated on 
1185
      -- 16 bit bus read which will be on even byte reads or 
1186
      -- 16 bit bus write which will be on odd byte writes.
1187
      -- 
1188
      case pb_hold_state is
1189
        when hold_release_state =>
1190 22 dilbert57
          pb_release <= '0';
1191 134 davidgb
          if (pb_rdu = '1') or (pb_wrl = '1') then
1192
            pb_count      <= "0100";
1193
            pb_hold_state <= hold_request_state;
1194 22 dilbert57
          elsif (pb_rdl = '1') or (pb_wru = '1') then
1195 134 davidgb
            pb_release    <= '1';
1196
            pb_hold_state <= hold_release_state;
1197
          end if;
1198 19 dilbert57
 
1199 134 davidgb
        when hold_request_state =>
1200
          if pb_count = "0000" then
1201
--          if ether_rdy = '1' then
1202 22 dilbert57
              pb_release    <= '1';
1203 134 davidgb
              pb_hold_state <= hold_release_state;
1204
--          end if;
1205 22 dilbert57
          else
1206 134 davidgb
            pb_count <= pb_count - "0001";
1207
          end if;
1208
        when others =>
1209
          null;
1210
      end case;
1211
    end if;
1212
  end process;
1213 19 dilbert57
 
1214 134 davidgb
  --
1215
  -- Compact Flash Control
1216
  --
1217
  compact_flash: process( ide_cs, cpu_addr )
1218
  begin
1219
   ide_cs0_n  <= not( ide_cs ) or cpu_addr(4);
1220
   ide_cs1_n  <= not( ide_cs and cpu_addr(4));
1221
   ide_dmack_n  <= '1';
1222
  end process;
1223 22 dilbert57
 
1224 134 davidgb
  --
1225
  -- Interrupts and other bus control signals
1226
  --
1227
  interrupts : process( SW3_N,
1228
                      pb_cs, pb_hold, pb_release, ram_hold,
1229
--                    ether_irq, 
1230 22 dilbert57
                      acia_irq,
1231 134 davidgb
                      keyboard_irq,
1232
                      trap_irq,
1233
                      timer_irq
1234
                      )
1235
  begin
1236 115 davidgb
    pb_hold    <= pb_cs and (not pb_release);
1237
    cpu_irq    <= acia_irq or keyboard_irq;
1238 134 davidgb
    cpu_nmi    <= trap_irq or not( SW3_N );
1239
    cpu_firq   <= timer_irq;
1240
    cpu_halt   <= '0';
1241
    cpu_hold   <= pb_hold or ram_hold;
1242 115 davidgb
    FLASH_CE_N <= '1';
1243 134 davidgb
  end process;
1244 19 dilbert57
 
1245 134 davidgb
  --
1246
  -- Flash 7 segment LEDS
1247
  --
1248
  my_led_flasher: process( clk_i, rst_i, CountL )
1249
  begin
1250 115 davidgb
    if rst_i = '1' then
1251 134 davidgb
         CountL <= "000000000000000000000000";
1252 115 davidgb
    elsif rising_edge(clk_i) then
1253 134 davidgb
         CountL <= CountL + 1;
1254 19 dilbert57
    end if;
1255 134 davidgb
    --  S(7 downto 0) <= CountL(23 downto 16);
1256
  end process;
1257 19 dilbert57
 
1258 134 davidgb
  --
1259
  -- Generate CPU & Pixel Clock from Memory Clock
1260
  --
1261
  my_prescaler : process( clk_i, clk_count )
1262
  begin
1263
    if rising_edge( clk_i ) then
1264
      if clk_count = 0 then
1265
        clk_count <= CPU_CLK_DIV-1;
1266
      else
1267
        clk_count <= clk_count - 1;
1268
      end if;
1269
      if clk_count = 0 then
1270
         clk25 <= '0';
1271
      elsif clk_count = (CPU_CLK_DIV/2) then
1272
         clk25 <= '1';
1273
      end if;
1274 115 davidgb
    end if;
1275 134 davidgb
  end process;
1276 19 dilbert57
 
1277 134 davidgb
  --
1278
  -- Reset button and reset timer
1279
  --
1280
  my_switch_assignments : process( rst_i, SW2_N, lock )
1281
  begin
1282
    rst_i <= not SW2_N;
1283
    cpu_reset <= rst_i or (not lock);
1284
  end process;
1285 19 dilbert57
 
1286 134 davidgb
  --
1287
  -- RS232 signals:
1288
  --
1289
  my_acia_assignments : process( RS232_RXD, RS232_CTS, txd, rts_n )
1290
  begin
1291
    rxd       <= RS232_RXD;
1292
    cts_n     <= RS232_CTS;
1293
    dcd_n     <= '0';
1294
    RS232_TXD <= txd;
1295
    RS232_RTS <= rts_n;
1296
  end process;
1297 19 dilbert57
 
1298 134 davidgb
  --
1299
  -- Pin assignments for ethernet controller
1300
  --
1301
  my_ethernet_assignments : process( clk_i, cpu_reset, ether_cs )
1302
  begin
1303 22 dilbert57
    ether_cs_n  <= not ether_cs;
1304
    ether_aen   <= not ether_cs; -- Ethernet address enable not 
1305
    ether_bhe_n <= '1';          -- Ethernet bus high enable - 8 bit access only
1306 134 davidgb
  end process;
1307 22 dilbert57
 
1308 134 davidgb
  --
1309
  -- I/O expansion slot assignments
1310
  --
1311
  my_slot_assignments : process( slot1_cs, slot2_cs)
1312
  begin
1313 22 dilbert57
    slot1_cs_n <= not slot1_cs;
1314
    slot2_cs_n <= not slot2_cs;
1315 134 davidgb
  end process;
1316 22 dilbert57
 
1317 134 davidgb
  --
1318
  -- VGA ouputs
1319
  --
1320
  my_vga_assignments : process( vga_red_o, vga_green_o, vga_blue_o )
1321
  begin
1322
    VGA_red(0)   <= vga_red_o;
1323
    VGA_red(1)   <= vga_red_o;
1324
    VGA_red(2)   <= vga_red_o;
1325
    VGA_green(0) <= vga_green_o;
1326
    VGA_green(1) <= vga_green_o;
1327
    VGA_green(2) <= vga_green_o;
1328
    VGA_blue(0)  <= vga_blue_o;
1329
    VGA_blue(1)  <= vga_blue_o;
1330
    VGA_blue(2)  <= vga_blue_o;
1331
  end process;
1332
 
1333
  --
1334
  -- SDRAM read write control
1335
  --
1336
  my_sdram_rw : process( clk_i, cpu_reset,
1337 115 davidgb
                       opBegun, ramDone,
1338 134 davidgb
                       ram_state,
1339 115 davidgb
                       ram_rd_req, ram_wr_req )
1340 134 davidgb
  begin
1341
    if( cpu_reset = '1' ) then
1342
      hRd        <= '0';
1343
      hWr        <= '0';
1344
      ram_hold   <= '0';
1345
      ram_state  <= ram_state_0;
1346 19 dilbert57
 
1347 134 davidgb
    elsif( falling_edge(clk_i) ) then
1348
      --
1349
      -- ram state machine
1350
      --
1351
      case ram_state is
1352 22 dilbert57
 
1353 134 davidgb
      when ram_state_0 =>
1354
        if ram_rd_req = '1' then
1355
          ram_hold   <= '1';
1356
          hRd        <= '1';
1357
          ram_state  <= ram_state_rd1;
1358
        elsif ram_wr_req = '1' then
1359
          ram_hold   <= '1';
1360
          hWr        <= '1';
1361
          ram_state  <= ram_state_wr1;
1362
        end if;
1363 22 dilbert57
 
1364 134 davidgb
      when ram_state_rd1 =>
1365
        if opBegun = '1' then
1366
          hRd        <= '0';
1367
          ram_state  <= ram_state_rd2;
1368
        end if;
1369 22 dilbert57
 
1370 134 davidgb
      when ram_state_rd2 =>
1371
        if ramDone = '1' then
1372
          ram_hold   <= '0';
1373
          ram_state  <= ram_state_3;
1374
        end if;
1375 22 dilbert57
 
1376 134 davidgb
      when ram_state_wr1 =>
1377
        if opBegun = '1' then
1378
          ram_hold   <= '0';
1379
          hWr        <= '0';
1380
          ram_state  <= ram_state_3;
1381
        end if;
1382 22 dilbert57
 
1383 134 davidgb
      when ram_state_3 =>
1384
        if ram_release = '1' then
1385
          ram_state  <= ram_state_0;
1386
        end if;
1387 22 dilbert57
 
1388 134 davidgb
      when others =>
1389
        hRd        <= '0';
1390
        hWr        <= '0';
1391
        ram_hold   <= '0';
1392
        ram_state  <= ram_state_0;
1393
    end case;
1394 22 dilbert57
 
1395 134 davidgb
    end if;
1396
  end process;
1397
 
1398
  --
1399
  -- SDRAM Address and data bus assignments
1400
  --
1401
  my_sdram_addr_data : process( cpu_addr, dat_addr,
1402 115 davidgb
                                cpu_data_out, hDout )
1403 134 davidgb
  begin
1404
    hAddr(23 downto 19)  <= "00000";
1405
    hAddr(18 downto 11)  <= dat_addr;
1406
    hAddr(10 downto 0)   <= cpu_addr(11 downto 1);
1407
    hUds                 <= not cpu_addr(0);
1408
    hLds                 <=     cpu_addr(0);
1409
    if cpu_addr(0) = '0' then
1410
      hDin( 7 downto 0) <= (others=>'0');
1411
      hDin(15 downto 8) <= cpu_data_out;
1412
      ram_data_out      <= hDout(15 downto 8);
1413
    else
1414
      hDin( 7 downto 0) <= cpu_data_out;
1415
      hDin(15 downto 8) <= (others=>'0');
1416
      ram_data_out      <= hDout( 7 downto 0);
1417
    end if;
1418
  end process;
1419
 
1420
  --
1421
  -- Hold RAM until falling CPU clock edge
1422
  --
1423
  ram_bus_hold: process( cpu_clk, cpu_reset, ram_hold )
1424
  begin
1425 115 davidgb
    if ram_hold = '1' then
1426 134 davidgb
      ram_release   <= '0';
1427
    elsif falling_edge(cpu_clk) then
1428
      ram_release   <= '1';
1429
    end if;
1430
  end process;
1431
 
1432
  --
1433
  -- CPU read data request on rising CPU clock edge
1434
  --
1435
  ram_read_request: process( hRd, cpu_clk, ram_cs, cpu_rw, ram_release )
1436
  begin
1437
    if hRd = '1' then
1438
      ram_rd_req   <= '0';
1439
    elsif rising_edge(cpu_clk) then
1440
      if (ram_cs = '1') and (cpu_rw = '1') and (ram_release = '1') then
1441
        ram_rd_req   <= '1';
1442
      end if;
1443
    end if;
1444
  end process;
1445
 
1446
  --
1447
  -- CPU write data to RAM valid on rising CPU clock edge
1448
  --
1449
  ram_write_request: process( hWr, cpu_clk, ram_cs, cpu_rw, ram_release )
1450
  begin
1451 115 davidgb
    if hWr = '1' then
1452 134 davidgb
       ram_wr_req   <= '0';
1453
    elsif rising_edge(cpu_clk) then
1454
      if (ram_cs = '1') and (cpu_rw = '0') and (ram_release = '1') then
1455
        ram_wr_req   <= '1';
1456 115 davidgb
      end if;
1457 134 davidgb
    end if;
1458
  end process;
1459 22 dilbert57
 
1460 134 davidgb
  status_leds : process( rst_i, cpu_reset, lock )
1461
  begin
1462
    S(0) <= rst_i;
1463
    S(1) <= cpu_reset;
1464
    S(2) <= lock;
1465
    S(3) <= countL(23);
1466
    S(7 downto 4) <= "0000";
1467
  end process;
1468 22 dilbert57
 
1469 134 davidgb
--  debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
1470
--                      cpu_halt, cpu_hold,
1471
--                      cpu_firq, cpu_irq, cpu_nmi,
1472
--                      cpu_addr, cpu_data_out, cpu_data_in )
1473
--  begin
1474
--    cpu_reset_o    <= cpu_reset;
1475
--    cpu_clk_o      <= cpu_clk;
1476
--    cpu_rw_o       <= cpu_rw;
1477
--    cpu_vma_o      <= cpu_vma;
1478
--    cpu_halt_o     <= cpu_halt;
1479
--    cpu_hold_o     <= cpu_hold;
1480
--    cpu_firq_o     <= cpu_firq;
1481
--    cpu_irq_o      <= cpu_irq;
1482
--    cpu_nmi_o      <= cpu_nmi;
1483
--    cpu_addr_o     <= cpu_addr;
1484
--    cpu_data_out_o <= cpu_data_out;
1485
--    cpu_data_in_o  <= cpu_data_in;
1486
--  end process;
1487 22 dilbert57
 
1488 19 dilbert57
end rtl; --===================== End of architecture =======================--
1489
 

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