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[/] [System09/] [trunk/] [rtl/] [System09_Xess_XuLA/] [System09_XuLA_Readme_Important.txt] - Blame information for rev 159

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System09 XuLA port
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==================
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This is a port of the System09 project to the XESS 200Kgate Spartan3A XuLA board.
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It uses 1MB of the SDRAM. Only half the data bus is used.
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System09 XuLA port was implemented with Xilinx ISE Design Suite 12.4
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Check XuLA.ucf for the pin assignment.
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It uses a MAX3232 for the RS232 interface, PS/2 keyboard interface and 3 bit RGB VGA video output.
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Video format is 80 characters x 25 character with 8 horizontal pixels per character
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The design doubles the 12MHz crystal on the XuLA board for the pixel clock
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Care must be taken with the Spartan3A inputs when connecting to 5V outputs
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as the inputs are normally not diode clamped.
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The UCF file specified PCI inputs on the input pin which should be diode clamped
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but only after the Spartan3A FPGA on the XuLA board is configured.
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Series current limiting resistors should be used when connecting a 5V logic output to an FPGA input.
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Check the UCF file to determine which inputs are diode clamped.
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Series limitted 5V logic outputs should not be connected to Spartan3A inputs until it is configured
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as a PCI33 input.
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John Kent
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2011-10-09
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The System09 XuLA port is licenced under GNU GPL version 3.
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--  Copyright (C) 2011 John Kent
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--
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--  This program is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see .
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--

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