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[/] [System09/] [trunk/] [rtl/] [System09_Xilinx_ML506/] [my_system09.vhd] - Blame information for rev 186

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1 59 davidgb
--===========================================================================----
2
--
3
--  S Y N T H E Z I A B L E    System09 - SOC.
4
--
5
--  www.OpenCores.Org - September 2003
6
--  This core adheres to the GNU public license  
7
--
8
-- File name      : System09.vhd
9
--
10
-- Purpose        : Top level file for 6809 compatible system on a chip
11
--                  Designed with Xilinx XC3S200 Spartan 3 FPGA.
12
--                  Implemented With Digilent Xilinx Starter FPGA board,
13
--
14
-- Dependencies   : ieee.Std_Logic_1164
15
--                  ieee.std_logic_unsigned
16
--                  ieee.std_logic_arith
17
--                  ieee.numeric_std
18
--
19
-- Uses           : mon_rom   (sys09bug_rom4k_b16.vhd) Monitor ROM
20
--                  cpu09     (cpu09.vhd)              CPU core
21
--                  dat_ram   (datram.vhd)             Dynamic Address Translation
22
--                  acia_6850 (acia_6850.vhd)          ACIA (UART)
23
--                            (acia_rx.vhd)
24
--                            (acia_tx.vhd)
25
--                  keyboard  (keyboard.vhd)           PS/2 Keyboard
26
--                            (ps2_keyboard.vhd)
27
--                            (keymap_rom)
28
--                  vdu8      (vdu8.vhd)                          Video Display Unit
29
--                            (char_rom2K_b16.vhd)
30
--                            (ram2k_b16.vhd)
31
--                  seven_segment (SevenSegment.vhd)   Seven Segment Display
32
-- 
33
-- Author         : John E. Kent      
34
--                  dilbert57@opencores.org      
35
--
36
--===========================================================================----
37
--
38
-- Revision History:
39
--===========================================================================--
40
-- Version 0.1 - 20 March 2003
41
-- Version 0.2 - 30 March 2003
42
-- Version 0.3 - 29 April 2003
43
-- Version 0.4 - 29 June 2003
44
--
45
-- Version 0.5 - 19 July 2003
46
-- prints out "Hello World"
47
--
48
-- Version 0.6 - 5 September 2003
49
-- Runs SBUG
50
--
51
-- Version 1.0- 6 Sep 2003 - John Kent
52
-- Inverted sys_clk
53
-- Initial release to Open Cores
54
--
55
-- Version 1.1 - 17 Jan 2004 - John Kent
56
-- Updated miniUart.
57
--
58
-- Version 1.2 - 25 Jan 2004 - John Kent
59
-- removed signals "test_alu" and "test_cc" 
60
-- Trap hardware re-instated.
61
--
62
-- Version 1.3 - 11 Feb 2004 - John Kent
63
-- Designed forked off to produce System09_VDU
64
-- Added VDU component
65
--      VDU runs at 25MHz and divides the clock by 2 for the CPU
66
-- UART Runs at 57.6 Kbps
67
--
68
-- Version 2.0 - 2 September 2004 - John Kent
69
-- ported to Digilent Xilinx Spartan3 starter board
70
--      removed Compaact Flash and Trap Logic.
71
-- Replaced SBUG with KBug9s
72
--
73
-- Version 2.1 - 21 November 2006 - John Kent
74
-- Replaced KBug9s with Sys09bug 1.0
75
-- Inverted bottom nybble of DAT register outputs
76
-- Changed ROM & I/O decoding to be compatible with SWTPc
77
-- Upped the serial baud rate to 115.2 KBd
78
-- added multiple global clock buffers
79
-- (Uart would not operate correctly)
80
--
81
-- Version 2.2 - 22 December 2006 - John Kent
82
-- Increased CPU clock from 12.5MHz to 25 MHz.
83
-- Removed some of the global clock buffers
84
-- Added LED output register
85
-- Changed address decoding to 4K Blocks
86
--
87
-- Version 2.3 - 1 June 2007 - John Kent
88
-- Updated VDU & ACIA
89
-- Changed decoding for Sys09Bug
90
--
91
-- Version 2.4 - 31 January 2008 - John Kent
92
--      ACIA does not appear to work.
93
-- Made RAM OE and WE strobes synchonous to sys_clk
94
--
95
--===========================================================================--
96
library ieee;
97
   use ieee.std_logic_1164.all;
98
   use IEEE.STD_LOGIC_ARITH.ALL;
99
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
100
   use ieee.numeric_std.all;
101
 
102
entity my_system09 is
103
  port(
104
    sys_clk     : in  Std_Logic;  -- System Clock input
105
         rst_sw    : in  Std_logic;  -- Master Reset input (active high)
106
         nmi_sw      : in  Std_logic;
107
 
108
    -- Memory Interface signals
109
    ram_addr    : out Std_Logic_Vector(17 downto 0);
110
    ram_wen     : out Std_Logic;
111
    ram_oen     : out Std_Logic;
112
 
113
    ram1_cen    : out Std_Logic;
114
         ram1_ubn    : out Std_Logic;
115
         ram1_lbn    : out Std_Logic;
116
    ram1_data   : inout Std_Logic_Vector(15 downto 0);
117
 
118
    ram2_cen    : out Std_Logic;
119
         ram2_ubn    : out Std_Logic;
120
         ram2_lbn    : out Std_Logic;
121
    ram2_data   : inout Std_Logic_Vector(15 downto 0);
122
 
123
         -- PS/2 Keyboard
124
         ps2c        : inout Std_logic;
125
         ps2d        : inout Std_Logic;
126
 
127
         -- ACIA Interface
128
    rxd         : in  Std_Logic;
129
         txd         : out Std_Logic;
130
 
131
         -- CRTC output signals
132
         vs          : out Std_Logic;
133
    hs          : out Std_Logic;
134
    blue        : out std_logic;
135
    green       : out std_logic;
136
    red         : out std_logic;
137
 
138
         -- LEDS & Switches
139
         leds        : out std_logic_vector(7 downto 0);
140
         switches    : in  std_logic_vector(7 downto 0);
141
 
142
         -- seven segment display
143
         segments    : out std_logic_vector(7 downto 0);
144
         digits      : out std_logic_vector(3 downto 0)
145
         );
146
end my_system09;
147
 
148
-------------------------------------------------------------------------------
149
-- Architecture for System09
150
-------------------------------------------------------------------------------
151
architecture my_computer of my_system09 is
152
  -----------------------------------------------------------------------------
153
  -- constants
154
  -----------------------------------------------------------------------------
155
  constant SYS_Clock_Frequency  : integer := 50000000;  -- FPGA System Clock
156
  constant VGA_Clock_Frequency  : integer := 25000000;  -- VGA Pixel Clock
157
  constant CPU_Clock_Frequency  : integer := 25000000;  -- CPU Clock
158
  constant BAUD_Rate            : integer := 57600;       -- Baud Rate
159
  constant ACIA_Clock_Frequency : integer := BAUD_Rate * 16;
160
 
161
  type hold_state_type is ( hold_release_state, hold_request_state );
162
 
163
  -----------------------------------------------------------------------------
164
  -- Signals
165
  -----------------------------------------------------------------------------
166
  -- BOOT ROM
167
  signal rom_cs        : Std_logic;
168
  signal rom_data_out  : Std_Logic_Vector(7 downto 0);
169
 
170
  -- FLEX9 RAM
171
  signal flex_cs       : Std_logic;
172
  signal flex_data_out : Std_Logic_Vector(7 downto 0);
173
 
174
  -- ACIA Interface signals
175
  signal acia_clk      : std_logic;
176
  signal acia_data_out : Std_Logic_Vector(7 downto 0);
177
  signal acia_cs       : Std_Logic;
178
  signal acia_irq      : Std_Logic;
179
  signal acia_rxd      : Std_Logic;
180
  signal acia_txd      : Std_Logic;
181
  signal acia_dcd_n    : Std_Logic;
182
--  signal acia_rts_n    : Std_Logic;
183
  signal acia_cts_n    : Std_Logic;
184
 
185
  -- keyboard port
186
  signal keyboard_data_out : std_logic_vector(7 downto 0);
187
  signal keyboard_cs       : std_logic;
188
  signal keyboard_irq      : std_logic;
189
 
190
  -- LEDs
191
  signal leds_data_out : std_logic_vector(7 downto 0);
192
  signal leds_cs       : std_logic;
193
 
194
  -- RAM
195
  signal ram_cs       : std_logic; -- memory chip select
196
  signal ram_data_out : std_logic_vector(7 downto 0);
197
  signal ram1_ce      : std_logic;
198
  signal ram1_ub      : std_logic;
199
  signal ram1_lb      : std_logic;
200
  signal ram2_ce      : std_logic;
201
  signal ram2_ub      : std_logic;
202
  signal ram2_lb      : std_logic;
203
  signal ram_we       : std_logic;
204
  signal ram_oe       : std_logic;
205
 
206
  -- CPU Interface signals
207
  signal cpu_reset    : Std_Logic;
208
  signal cpu_clk      : Std_Logic;
209
  signal cpu_rw       : std_logic;
210
  signal cpu_vma      : std_logic;
211
  signal cpu_halt     : std_logic;
212
  signal cpu_hold     : std_logic;
213
  signal cpu_firq     : std_logic;
214
  signal cpu_irq      : std_logic;
215
  signal cpu_nmi      : std_logic;
216
  signal cpu_addr     : std_logic_vector(15 downto 0);
217
  signal cpu_data_in  : std_logic_vector(7 downto 0);
218
  signal cpu_data_out : std_logic_vector(7 downto 0);
219
 
220
  -- Dynamic Address Translation
221
  signal dat_cs       : std_logic;
222
  signal dat_addr     : std_logic_vector(7 downto 0);
223
 
224
  -- Video Display Unit
225
  signal vdu_cs       : std_logic;
226
  signal vdu_data_out : std_logic_vector(7 downto 0);
227
  signal vga_clk      : std_logic;
228
 
229
  -- 7 Segment Display
230
  signal seg_cs       : std_logic;
231
  signal seg_data_out : std_logic_vector(7 downto 0);
232
 
233
  -- System Clock Prescaler
234
  signal clk_count    : std_logic;
235
 
236
-----------------------------------------------------------------
237
--
238
-- CPU09 CPU core
239
--
240
-----------------------------------------------------------------
241
 
242
component cpu09
243
  port (
244
         clk      :     in  std_logic;
245
    rst      : in  std_logic;
246
    rw       :  out std_logic;          -- Asynchronous memory interface
247
    vma      :  out std_logic;
248
    address  : out std_logic_vector(15 downto 0);
249
    data_in  : in        std_logic_vector(7 downto 0);
250
         data_out : out std_logic_vector(7 downto 0);
251
         halt     : in  std_logic;
252
         hold     : in  std_logic;
253
         irq      : in  std_logic;
254
         nmi      : in  std_logic;
255
         firq     : in  std_logic
256
  );
257
end component;
258
 
259
 
260
----------------------------------------
261
--
262
-- 4KByte Block RAM Monitor ROM
263
--
264
----------------------------------------
265
component mon_rom
266
  Port (
267
    clk      : in  std_logic;
268
    rst      : in  std_logic;
269
    cs       : in  std_logic;
270
    rw       : in  std_logic;
271
    addr     : in  std_logic_vector (11 downto 0);
272
    rdata    : out std_logic_vector (7 downto 0);
273
    wdata    : in  std_logic_vector (7 downto 0)
274
    );
275
end component;
276
 
277
----------------------------------------
278
--
279
-- 8KBytes Block RAM for FLEX9
280
-- $C000 - $DFFF
281
--
282
----------------------------------------
283
component flex_ram
284
  Port (
285
    clk      : in  std_logic;
286
    rst      : in  std_logic;
287
    cs       : in  std_logic;
288
    rw       : in  std_logic;
289
    addr     : in  std_logic_vector (12 downto 0);
290
    rdata    : out std_logic_vector (7 downto 0);
291
    wdata    : in  std_logic_vector (7 downto 0)
292
    );
293
end component;
294
 
295
----------------------------------------
296
--
297
-- Dynamic Address Translation Registers
298
--
299
----------------------------------------
300
component dat_ram
301
  port (
302
    clk      : in  std_logic;
303
         rst      : in  std_logic;
304
         cs       : in  std_logic;
305
         rw       : in  std_logic;
306
         addr_lo  : in  std_logic_vector(3 downto 0);
307
         addr_hi  : in  std_logic_vector(3 downto 0);
308
    data_in  : in  std_logic_vector(7 downto 0);
309
         data_out : out std_logic_vector(7 downto 0)
310
  );
311
end component;
312
 
313
-----------------------------------------------------------------
314
--
315
-- 6850 ACIA
316
--
317
-----------------------------------------------------------------
318
 
319
component ACIA_6850
320
  port (
321
    clk      : in  Std_Logic;  -- System Clock
322
    rst      : in  Std_Logic;  -- Reset input (active high)
323
    cs       : in  Std_Logic;  -- ACIA Chip Select
324
    rw       : in  Std_Logic;  -- Read / Not Write
325
    irq      : out Std_Logic;  -- Interrupt
326
    Addr     : in  Std_Logic;  -- Register Select
327
    DataIn   : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
328
    DataOut  : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
329
    RxC      : in  Std_Logic;  -- Receive Baud Clock
330
    TxC      : in  Std_Logic;  -- Transmit Baud Clock
331
    RxD      : in  Std_Logic;  -- Receive Data
332
    TxD      : out Std_Logic;  -- Transmit Data
333
         DCD_n    : in  Std_Logic;  -- Data Carrier Detect
334
    CTS_n    : in  Std_Logic;  -- Clear To Send
335
    RTS_n    : out Std_Logic   -- Request To send
336
  );
337
end component;
338
 
339
-----------------------------------------------------------------
340
--
341
-- ACIA Clock divider
342
--
343
-----------------------------------------------------------------
344
 
345
component ACIA_Clock
346
  generic (
347
     SYS_Clock_Frequency  : integer :=  SYS_Clock_Frequency;
348
          ACIA_Clock_Frequency : integer := ACIA_Clock_Frequency
349
  );
350
  port (
351
     clk      : in  Std_Logic;  -- System Clock Input
352
          ACIA_clk : out Std_logic   -- ACIA Clock output
353
  );
354
end component;
355
 
356
 
357
----------------------------------------
358
--
359
-- PS/2 Keyboard
360
--
361
----------------------------------------
362
 
363
component keyboard
364
  generic(
365
  KBD_Clock_Frequency : integer := CPU_Clock_Frequency
366
  );
367
  port(
368
  clk             : in    std_logic;
369
  rst             : in    std_logic;
370
  cs              : in    std_logic;
371
  rw              : in    std_logic;
372
  addr            : in    std_logic;
373
  data_in         : in    std_logic_vector(7 downto 0);
374
  data_out        : out   std_logic_vector(7 downto 0);
375
  irq             : out   std_logic;
376
  kbd_clk         : inout std_logic;
377
  kbd_data        : inout std_logic
378
  );
379
end component;
380
 
381
----------------------------------------
382
--
383
-- Video Display Unit.
384
--
385
----------------------------------------
386
component vdu8
387
      generic(
388
        VDU_CLOCK_FREQUENCY    : integer := CPU_Clock_Frequency; -- HZ
389
        VGA_CLOCK_FREQUENCY    : integer := VGA_Clock_Frequency; -- HZ
390
             VGA_HOR_CHARS          : integer := 80; -- CHARACTERS
391
             VGA_VER_CHARS          : integer := 25; -- CHARACTERS
392
             VGA_PIXELS_PER_CHAR    : integer := 8;  -- PIXELS
393
             VGA_LINES_PER_CHAR     : integer := 16; -- LINES
394
             VGA_HOR_BACK_PORCH     : integer := 40; -- PIXELS
395
             VGA_HOR_SYNC           : integer := 96; -- PIXELS
396
             VGA_HOR_FRONT_PORCH    : integer := 24; -- PIXELS
397
             VGA_VER_BACK_PORCH     : integer := 13; -- LINES
398
             VGA_VER_SYNC           : integer := 1;  -- LINES
399
             VGA_VER_FRONT_PORCH    : integer := 36  -- LINES
400
      );
401
      port(
402
                -- control register interface
403
      vdu_clk      : in  std_logic;      -- CPU Clock - 12.5MHz
404
      vdu_rst      : in  std_logic;
405
                vdu_cs       : in  std_logic;
406
                vdu_rw       : in  std_logic;
407
                vdu_addr     : in  std_logic_vector(2 downto 0);
408
      vdu_data_in  : in  std_logic_vector(7 downto 0);
409
      vdu_data_out : out std_logic_vector(7 downto 0);
410
 
411
      -- vga port connections
412
                vga_clk      : in  std_logic;   -- VGA Pixel Clock - 25 MHz
413
      vga_red_o    : out std_logic;
414
      vga_green_o  : out std_logic;
415
      vga_blue_o   : out std_logic;
416
      vga_hsync_o  : out std_logic;
417
      vga_vsync_o  : out std_logic
418
   );
419
end component;
420
 
421
----------------------------------------
422
--
423
-- Seven Segment Display driver
424
--
425
----------------------------------------
426
 
427
component seven_segment is
428
        port (
429
          clk         : in  std_logic;
430
     rst         : in  std_logic;
431
     cs          : in  std_logic;
432
     rw          : in  std_logic;
433
     addr        : in  std_logic_vector(1 downto 0);
434
     data_in     : in  std_logic_vector(7 downto 0);
435
          data_out    : out std_logic_vector(7 downto 0);
436
          segments    : out std_logic_vector(7 downto 0);
437
          digits             : out std_logic_vector(3 downto 0)
438
        );
439
end component;
440
 
441
component BUFG
442
  port (
443
    i            : in  std_logic;
444
    o            : out std_logic
445
  );
446
end component;
447
 
448
begin
449
  -----------------------------------------------------------------------------
450
  -- Instantiation of internal components
451
  -----------------------------------------------------------------------------
452
 
453
my_cpu : cpu09  port map (
454
         clk         => cpu_clk,
455
    rst       => cpu_reset,
456
    rw       => cpu_rw,
457
    vma       => cpu_vma,
458
    address   => cpu_addr(15 downto 0),
459
    data_in   => cpu_data_in,
460
         data_out  => cpu_data_out,
461
         halt      => cpu_halt,
462
         hold      => cpu_hold,
463
         irq       => cpu_irq,
464
         nmi       => cpu_nmi,
465
         firq      => cpu_firq
466
    );
467
 
468
my_rom : mon_rom port map (
469
    clk       => cpu_clk,
470
    rst       => cpu_reset,
471
         cs        => rom_cs,
472
         rw        => '1',
473
    addr      => cpu_addr(11 downto 0),
474
    rdata     => rom_data_out,
475
    wdata     => cpu_data_out
476
    );
477
 
478
my_flex : flex_ram port map (
479
    clk       => cpu_clk,
480
    rst       => cpu_reset,
481
         cs        => flex_cs,
482
         rw        => cpu_rw,
483
    addr      => cpu_addr(12 downto 0),
484
    rdata     => flex_data_out,
485
    wdata     => cpu_data_out
486
    );
487
 
488
my_dat : dat_ram port map (
489
    clk       => cpu_clk,
490
         rst       => cpu_reset,
491
         cs        => dat_cs,
492
         rw        => cpu_rw,
493
         addr_hi   => cpu_addr(15 downto 12),
494
         addr_lo   => cpu_addr(3 downto 0),
495
    data_in   => cpu_data_out,
496
         data_out  => dat_addr(7 downto 0)
497
         );
498
 
499
my_acia  : ACIA_6850 port map (
500
         clk         => cpu_clk,
501
         rst       => cpu_reset,
502
    cs        => acia_cs,
503
         rw        => cpu_rw,
504
    irq       => acia_irq,
505
    Addr      => cpu_addr(0),
506
         Datain    => cpu_data_out,
507
         DataOut   => acia_data_out,
508
         RxC       => acia_clk,
509
         TxC       => acia_clk,
510
         RxD       => acia_rxd,
511
         TxD       => acia_txd,
512
         DCD_n     => acia_dcd_n,
513
         CTS_n     => acia_cts_n,
514
         RTS_n     => open
515
         );
516
 
517
 
518
----------------------------------------
519
--
520
-- ACIA Clock
521
--
522
----------------------------------------
523
my_ACIA_Clock : ACIA_Clock
524
  generic map(
525
    SYS_Clock_Frequency  => SYS_Clock_Frequency,
526
         ACIA_Clock_Frequency => ACIA_Clock_Frequency
527
  )
528
  port map(
529
    clk        => sys_clk,
530
    acia_clk   => acia_clk
531
  );
532
 
533
 
534
----------------------------------------
535
--
536
-- PS/2 Keyboard Interface
537
--
538
----------------------------------------
539
my_keyboard : keyboard
540
   generic map (
541
        KBD_Clock_Frequency => CPU_Clock_frequency
542
        )
543
   port map(
544
        clk          => cpu_clk,
545
        rst          => cpu_reset,
546
        cs           => keyboard_cs,
547
        rw           => cpu_rw,
548
        addr         => cpu_addr(0),
549
        data_in      => cpu_data_out(7 downto 0),
550
        data_out     => keyboard_data_out(7 downto 0),
551
        irq          => keyboard_irq,
552
        kbd_clk      => ps2c,
553
        kbd_data     => ps2d
554
        );
555
 
556
----------------------------------------
557
--
558
-- Video Display Unit instantiation
559
--
560
----------------------------------------
561
my_vdu : vdu8
562
  generic map(
563
      VDU_CLOCK_FREQUENCY    => CPU_Clock_Frequency, -- HZ
564
      VGA_CLOCK_FREQUENCY    => VGA_Clock_Frequency, -- HZ
565
           VGA_HOR_CHARS          => 80, -- CHARACTERS
566
           VGA_VER_CHARS          => 25, -- CHARACTERS
567
           VGA_PIXELS_PER_CHAR    => 8,  -- PIXELS
568
           VGA_LINES_PER_CHAR     => 16, -- LINES
569
           VGA_HOR_BACK_PORCH     => 40, -- PIXELS
570
           VGA_HOR_SYNC           => 96, -- PIXELS
571
           VGA_HOR_FRONT_PORCH    => 24, -- PIXELS
572
           VGA_VER_BACK_PORCH     => 13, -- LINES
573
           VGA_VER_SYNC           => 1,  -- LINES
574
           VGA_VER_FRONT_PORCH    => 36  -- LINES
575
  )
576
  port map(
577
 
578
                -- Control Registers
579
                vdu_clk       => cpu_clk,                                        -- 12.5 MHz System Clock in
580
      vdu_rst       => cpu_reset,
581
                vdu_cs        => vdu_cs,
582
                vdu_rw        => cpu_rw,
583
                vdu_addr      => cpu_addr(2 downto 0),
584
                vdu_data_in   => cpu_data_out,
585
                vdu_data_out  => vdu_data_out,
586
 
587
      -- vga port connections
588
      vga_clk       => vga_clk,                                  -- 25 MHz VDU pixel clock
589
      vga_red_o     => red,
590
      vga_green_o   => green,
591
      vga_blue_o    => blue,
592
      vga_hsync_o   => hs,
593
      vga_vsync_o   => vs
594
   );
595
 
596
 
597
----------------------------------------
598
--
599
-- Seven Segment Display instantiation
600
--
601
----------------------------------------
602
 
603
my_seg : seven_segment port map (
604
    clk        => cpu_clk,
605
         rst        => cpu_reset,
606
         cs         => seg_cs,
607
         rw         => cpu_rw,
608
         addr       => cpu_addr(1 downto 0),
609
    data_in    => cpu_data_out,
610
         data_out   => seg_data_out,
611
         segments   => segments,
612
         digits     => digits
613
         );
614
 
615
 
616
vga_clk_buffer : BUFG port map(
617
    i => clk_count,
618
         o => vga_clk
619
    );
620
 
621
cpu_clk_buffer : BUFG port map(
622
    i => clk_count,
623
         o => cpu_clk
624
    );
625
 
626
--
627
-- Clock divider
628
-- Assumes 50 MHz system clock
629
-- 25MHz pixel clock
630
-- 25MHz CPU clock
631
--
632
sys09_clock : process( sys_clk, clk_count )
633
begin
634
        if sys_clk'event and sys_clk='1' then
635
           clk_count <= not clk_count;
636
   end if;
637
end process;
638
 
639
----------------------------------------------------------------------
640
--
641
-- Process to decode memory map
642
--
643
----------------------------------------------------------------------
644
 
645
mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
646
                                              dat_cs, dat_addr,
647
                                              rom_data_out,
648
                                                   acia_data_out,
649
                                                        keyboard_data_out,
650
                                                        vdu_data_out,
651
                                                        seg_data_out,
652
                                                        leds_data_out,
653
                                                        flex_data_out,
654
                                                        ram_data_out
655
                                                        )
656
begin
657
      cpu_data_in <= (others=>'0');
658
      dat_cs      <= '0';
659
      rom_cs      <= '0';
660
      acia_cs     <= '0';
661
      keyboard_cs <= '0';
662
      vdu_cs      <= '0';
663
      seg_cs      <= '0';
664
      leds_cs     <= '0';
665
      flex_cs     <= '0';
666
      ram_cs      <= '0';
667
--           timer_cs    <= '0';
668
--      trap_cs     <= '0';
669
--           pb_cs       <= '0';
670
--      ide_cs      <= '0';
671
--      ether_cs    <= '0';
672
--           slot1_cs    <= '0';
673
--      slot2_cs    <= '0';
674
 
675
      if cpu_addr( 15 downto 8 ) = "11111111" then
676
             cpu_data_in <= rom_data_out;
677
        dat_cs      <= cpu_vma;              -- write DAT
678
        rom_cs      <= cpu_vma;              -- read  ROM
679
           --
680
                -- Sys09Bug Monitor ROM $F000 - $FFFF
681
                --
682
           elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
683
           --
684
                -- Monitor ROM $F000 - $FFFF
685
                --
686
        cpu_data_in <= rom_data_out;
687
        rom_cs      <= cpu_vma;          -- read  ROM
688
 
689
      --
690
                -- IO Devices $E000 - $EFFF
691
                --
692
                elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
693
                        case cpu_addr(11 downto 8) is
694
                        --
695
                        -- SWTPC peripherals from $E000 to $E0FF
696
                        --
697
                        when "0000" =>
698
                     case cpu_addr(7 downto 4) is
699
                          --
700
                          -- ACIA ($E000 - $E00F)
701
                          --
702
                          when "0000" =>
703
                       cpu_data_in <= acia_data_out;
704
                            acia_cs     <= cpu_vma;
705
 
706
                --
707
                          -- Reserved - FD1771 FDC ($E010 - $E01F) (SWTPC)
708
           --
709
 
710
                          --
711
           -- Keyboard port ($E020 - $E02F)
712
                          --
713
                          when "0010" =>
714
             cpu_data_in <= keyboard_data_out;
715
                            keyboard_cs <= cpu_vma;
716
 
717
           --
718
           -- VDU port ($E030 - $E03F)
719
                          --
720
                          when "0011" =>
721
             cpu_data_in <= vdu_data_out;
722
                            vdu_cs      <= cpu_vma;
723
 
724
           --
725
                          -- Reserved - SWTPc MP-T ($E040 - $E04F)
726
                          --
727
 
728
           --
729
           -- Reserved - Timer ($E050 - $E05F) (B5-X300)
730
                          --
731
 
732
           --
733
           -- Reserved - Bus Trap Logic ($E060 - $E06F) (B5-X300)
734
                          --
735
 
736
           --
737
           -- Reserved - I/O port ($E070 - $E07F) (B5-X300)
738
                          --
739
 
740
                          --
741
                          -- Reserved - PTM 6840 ($E080 - $E08F) (SWTPC)
742
                          --
743
 
744
                          --
745
                          -- Reserved - PIA Timer ($E090 - $E09F) (SWTPC)
746
                          --
747
 
748
           --
749
                          -- Read Switched port ($E0A0 - $E0AF)
750
                          -- Write LEDS
751
                          --
752
                          when "1010" =>
753
             cpu_data_in <= leds_data_out;
754
                            leds_cs     <= cpu_vma;
755
 
756
           --
757
           -- 7 segment display port ($E0B0 - $E0BF)
758
                          --
759
                          when "1011" =>
760
             cpu_data_in <= seg_data_out;
761
                            seg_cs      <= cpu_vma;
762
 
763
 
764
                          when others => -- $EXC0 to $EXFF
765
                            null;
766
                     end case;
767
                        --
768
                        -- XST-3.0 Peripheral Bus goes here
769
                        --      $E100 to $E1FF
770
                        --      Four devices
771
                        -- IDE, Ethernet, Slot1, Slot2
772
                        --
773
--                      when "0001" =>
774
--                        cpu_data_in <= pb_data_out;
775
--                        pb_cs       <= cpu_vma;
776
--                   case cpu_addr(7 downto 6) is
777
                          --
778
                          -- IDE Interface $E100 to $E13F
779
                          --
780
--                        when "00" =>
781
--                          ide_cs   <= cpu_vma;
782
                          --
783
                          -- Ethernet Interface $E140 to $E17F
784
                          --
785
--                        when "01" =>
786
--                          ether_cs <= cpu_vma;
787
                          --
788
                          -- Slot 1 Interface $E180 to $E1BF
789
                          --
790
--                        when "10" =>
791
--                          slot1_cs <= cpu_vma;
792
                          --
793
                          -- Slot 2 Interface $E1C0 to $E1FF
794
                          --
795
--                        when "11" =>
796
--                          slot2_cs <= cpu_vma;
797
           --
798
                          -- Nothing else
799
                          --
800
--         when others =>
801
--           null;
802
--         end case;
803
         --
804
                        --      $E200 to $EFFF reserved for future use
805
                        --
806
                when others =>
807
                          null;
808
         end case;
809
           --
810
                -- FLEX RAM $0C000 - $0DFFF
811
                --
812
                elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
813
        cpu_data_in <= flex_data_out;
814
        flex_cs     <= cpu_vma;
815
                --
816
                -- Everything else is RAM
817
                --
818
                else
819
                  cpu_data_in <= ram_data_out;
820
                  ram_cs      <= cpu_vma;
821
    end if;
822
end process;
823
 
824
 
825
--
826
-- 1M byte SRAM Control
827
-- Processes to read and write memory based on bus signals
828
--
829
ram_process: process( cpu_reset, sys_clk,
830
                      cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
831
                                               dat_addr, ram_cs,
832
                      ram1_ce, ram1_ub, ram1_lb, ram1_data,
833
                      ram2_ce, ram2_ub, ram2_lb, ram2_data,
834
                                                         ram_we, ram_oe )
835
begin
836
    --
837
    -- ram_hold signal helps 
838
    --
839
    if( cpu_reset = '1' ) then
840
           ram_we   <= '0';
841
           ram_oe   <= '0';
842
    --
843
         -- Clock Hold on rising edge
844
         --
845
    elsif( sys_clk'event and sys_clk='1' ) then
846
           if (ram_cs = '1') and (ram_we = '0') and (ram_oe = '0') then
847
             ram_we   <= not cpu_rw;
848
             ram_oe   <=     cpu_rw;
849
      else
850
             ram_we   <= '0';
851
             ram_oe   <= '0';
852
      end if;
853
    end if;
854
 
855
         ram_wen  <= not ram_we;
856
         ram_oen  <= not ram_oe;
857
 
858
    ram1_ce   <= ram_cs and (not cpu_addr(1));
859
    ram1_ub   <= not cpu_addr(0);
860
    ram1_lb   <= cpu_addr(0);
861
    ram1_cen  <= not ram1_ce;
862
    ram1_ubn  <= not ram1_ub;
863
    ram1_lbn  <= not ram1_lb;
864
 
865
    ram2_ce   <= ram_cs and cpu_addr(1);
866
    ram2_ub   <= not cpu_addr(0);
867
    ram2_lb   <= cpu_addr(0);
868
    ram2_cen  <= not ram2_ce;
869
    ram2_ubn  <= not ram2_ub;
870
    ram2_lbn  <= not ram2_lb;
871
 
872
         ram_addr(17 downto 10) <= dat_addr(7 downto 0);
873
         ram_addr(9 downto 0) <= cpu_addr(11 downto 2);
874
 
875
    if ram_we = '1' and ram1_ce = '1' and ram1_lb = '1' then
876
                ram1_data(7 downto 0) <= cpu_data_out;
877
         else
878
      ram1_data(7 downto 0)  <= "ZZZZZZZZ";
879
         end if;
880
 
881
    if ram_we = '1' and ram1_ce = '1' and ram1_ub = '1' then
882
                ram1_data(15 downto 8) <= cpu_data_out;
883
         else
884
      ram1_data(15 downto 8)  <= "ZZZZZZZZ";
885
         end if;
886
 
887
    if ram_we = '1' and ram2_ce = '1' and ram2_lb = '1' then
888
                ram2_data(7 downto 0) <= cpu_data_out;
889
         else
890
      ram2_data(7 downto 0)  <= "ZZZZZZZZ";
891
         end if;
892
 
893
    if ram_we = '1' and ram2_ce = '1' and ram2_ub = '1' then
894
                ram2_data(15 downto 8) <= cpu_data_out;
895
         else
896
      ram2_data(15 downto 8)  <= "ZZZZZZZZ";
897
         end if;
898
 
899
         case cpu_addr(1 downto 0) is
900
         when "00" =>
901
      ram_data_out <= ram1_data(15 downto 8);
902
         when "01" =>
903
      ram_data_out <= ram1_data(7 downto 0);
904
         when "10" =>
905
      ram_data_out <= ram2_data(15 downto 8);
906
    when others =>
907
      ram_data_out <= ram2_data(7 downto 0);
908
    end case;
909
end process;
910
 
911
--
912
-- LEDS output register
913
--
914
leds_output : process( cpu_clk, cpu_reset, switches )
915
begin
916
        if cpu_reset = '1' then
917
                leds <= "00000000";
918
        elsif cpu_clk'event and cpu_clk='0' then
919
                if      leds_cs = '1' and cpu_rw = '0' then
920
                        leds <= cpu_data_out;
921
                end if;
922
        end if;
923
        leds_data_out <= switches;
924
end process;
925
 
926
--
927
-- Interrupts and other bus control signals
928
--
929
interrupts : process(   rst_sw,
930
                                                                acia_irq,
931
                                                                keyboard_irq,
932
                                                                nmi_sw
933
                                                         )
934
begin
935
   if sys_clk'event and sys_clk = '1' then
936
          cpu_reset  <= rst_sw; -- CPU reset is active high
937
   end if;
938
        cpu_firq   <= keyboard_irq;
939
        cpu_nmi    <= nmi_sw;
940
        cpu_irq    <= acia_irq;
941
        cpu_halt   <= '0';
942
        cpu_hold   <= '0';
943
end process;
944
 
945
--
946
-- ACIA pin assignments
947
--
948
acia_assignments : process( rxd, acia_txd )
949
begin
950
        acia_dcd_n <= '0';
951
        acia_cts_n <= '0';
952
        acia_rxd   <= rxd;
953
        txd        <= acia_txd;
954
end process;
955
 
956
 
957
end my_computer; --===================== End of architecture =======================--
958
 

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