OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [Testbench/] [testbench4.vhd] - Blame information for rev 189

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 19 dilbert57
--===========================================================================--
2 122 dilbert57
--                                                                           --
3
--             TESTBENCH    testbench4 - CPU09 Testbench.                    --
4
--                                                                           --
5
--===========================================================================--
6 19 dilbert57
--
7 122 dilbert57
-- File name      : Testbench4.vhd
8 19 dilbert57
--
9 122 dilbert57
-- Purpose        : cpu09 Microprocessor Test Bench 4
10
--                  Contains SBUG ROM
11 19 dilbert57
--
12 122 dilbert57
-- Dependencies   : ieee.Std_Logic_1164
13
--                  ieee.std_logic_unsigned
14
--                  ieee.std_logic_arith
15
--                  ieee.numeric_std
16 19 dilbert57
--
17 122 dilbert57
-- Uses           : cpu09    (..\VHDL\cpu09.vhd)              CPU core
18
--                  ram_2k   (..\Spartan3\ram2k_b16.vhd)      2KB block RAM
19
--                  mon_rom  (..\Spartan3\sbug_rom2k_b16.vhd) 2KB SBUG block ROM
20
--                   
21
-- Author         : John E. Kent
22
--                  dilbert57@opencores.org      
23
-- 
24
--  Copyright (C) 2003 - 2011 John Kent
25
--
26
--  This program is free software: you can redistribute it and/or modify
27
--  it under the terms of the GNU General Public License as published by
28
--  the Free Software Foundation, either version 3 of the License, or
29
--  (at your option) any later version.
30
--
31
--  This program is distributed in the hope that it will be useful,
32
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
33
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
34
--  GNU General Public License for more details.
35
--
36
--  You should have received a copy of the GNU General Public License
37
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
38
--
39
--===========================================================================--
40
--                                                                           --
41
--                                Revision History                           --
42
--                                                                           --
43
--===========================================================================--
44 19 dilbert57
--
45 122 dilbert57
-- Rev  Date       Author     Changes
46
-- 0.1  2003-04-12 John Kent  First version
47
-- 1.0  2003-09-06 John Kent  Initial release to Opencores.org
48
-- 1.1  2004-02-25 John kent  removed test_alu and test_cc signals from CPU component.
49
-- 1.2  2011-10-09 John Kent  renamed address to addr on CPU component, updated header
50 19 dilbert57
--
51 122 dilbert57
--===========================================================================--
52
 
53 19 dilbert57
library ieee;
54
   use ieee.std_logic_1164.all;
55
   use IEEE.STD_LOGIC_ARITH.ALL;
56
   use ieee.numeric_std.all;
57
 
58 122 dilbert57
entity my_testbench4 is
59
end my_testbench4;
60 19 dilbert57
 
61
-------------------------------------------------------------------------------
62
-- Architecture for memio Controller Unit
63
-------------------------------------------------------------------------------
64 122 dilbert57
architecture behavior of my_testbench4 is
65 19 dilbert57
  -----------------------------------------------------------------------------
66
  -- Signals
67
  -----------------------------------------------------------------------------
68
  signal cpu_irq    : std_Logic;
69
  signal cpu_firq   : std_logic;
70
  signal cpu_nmi    : std_logic;
71
 
72
  -- CPU Interface signals
73
  signal SysClk      : Std_Logic;
74
  signal cpu_reset   : Std_Logic;
75
  signal cpu_rw      : Std_Logic;
76
  signal cpu_vma     : Std_Logic;
77
  signal cpu_addr    : Std_Logic_Vector(15 downto 0);
78
  signal cpu_data_in : Std_Logic_Vector(7 downto 0);
79
  signal cpu_data_out: Std_Logic_Vector(7 downto 0);
80
  signal cpu_halt    : Std_logic;
81
  signal cpu_hold    : Std_logic;
82
  signal rom_data_out: Std_Logic_Vector(7 downto 0);
83
  signal ram_data_out: Std_Logic_Vector(7 downto 0);
84
  signal ram_cs      : Std_Logic;
85
 
86
component cpu09
87
  port (
88
         clk:        in std_logic;
89
    rst:             in std_logic;
90
    rw:      out        std_logic;              -- Asynchronous memory interface
91
    vma:             out        std_logic;
92 122 dilbert57
    addr:     out       std_logic_vector(15 downto 0);
93 19 dilbert57
    data_in:  in        std_logic_vector(7 downto 0);
94
         data_out: out std_logic_vector(7 downto 0);
95
         halt:     in  std_logic;
96
         hold:     in  std_logic;
97
         irq:      in  std_logic;
98
         nmi:      in  std_logic;
99
         firq:     in  std_logic
100
  );
101
end component;
102
 
103
 
104 122 dilbert57
component mon_rom
105 19 dilbert57
    Port (
106 122 dilbert57
       clk      : in  std_logic;
107
                 rst      : in  std_logic;
108
                 cs       : in  std_logic;
109
                 rw       : in  std_logic;
110
       addr     : in  std_logic_vector (10 downto 0);
111
       data_in  : in  std_logic_vector (7 downto 0);
112
       data_out : out std_logic_vector (7 downto 0)
113 19 dilbert57
    );
114
end component;
115 122 dilbert57
 
116
component ram_2k
117 19 dilbert57
    Port (
118 122 dilbert57
       clk      : in  std_logic;
119
       rst      : in  std_logic;
120
       cs       : in  std_logic;
121
       addr     : in  std_logic_vector (10 downto 0);
122
       rw       : in  std_logic;
123
       data_in  : in  std_logic_vector (7 downto 0);
124
       data_out : out std_logic_vector (7 downto 0)
125 19 dilbert57
    );
126
end component;
127
 
128
begin
129
my_cpu : cpu09  port map (
130
         clk         => SysClk,
131
    rst      => cpu_reset,
132
    rw       => cpu_rw,
133
    vma       => cpu_vma,
134 122 dilbert57
    addr      => cpu_addr(15 downto 0),
135 19 dilbert57
    data_in   => cpu_data_in,
136
         data_out  => cpu_data_out,
137
         halt      => cpu_halt,
138
         hold      => cpu_hold,
139
         irq       => cpu_irq,
140
         nmi       => cpu_nmi,
141
         firq      => cpu_firq
142
  );
143
 
144
 
145 122 dilbert57
my_rom : mon_rom port map (
146
       clk      => SysClk,
147
       rst      => cpu_reset,
148
                 cs       => ram_cs,
149
                 rw       => cpu_rw,
150
       addr     => cpu_addr(10 downto 0),
151
       data_in  => cpu_data_out,
152
       data_out => rom_data_out
153 19 dilbert57
    );
154
 
155 122 dilbert57
 
156
my_ram : ram_2k port map (
157
       clk      => SysClk,
158
       rst      => cpu_reset,
159
                 cs       => ram_cs,
160
                 rw       => cpu_rw,
161
       addr     => cpu_addr(10 downto 0),
162
       data_in  => cpu_data_out,
163
       data_out => ram_data_out
164 19 dilbert57
    );
165 122 dilbert57
 
166 19 dilbert57
  -- *** Test Bench - User Defined Section ***
167
   tb : PROCESS
168
        variable count : integer;
169
   BEGIN
170
 
171
        cpu_reset <= '0';
172
        SysClk <= '0';
173
   cpu_irq <= '0';
174
   cpu_nmi <= '0';
175
        cpu_firq <= '0';
176
   cpu_halt <= '0';
177
        cpu_hold <= '0';
178
 
179
                for count in 0 to 512 loop
180
                        SysClk <= '0';
181
                        if count = 0 then
182
                                cpu_reset <= '1';
183
                        elsif count = 1 then
184
                                cpu_reset <= '0';
185
                        end if;
186
                        wait for 100 ns;
187
                        SysClk <= '1';
188
                        wait for 100 ns;
189
                end loop;
190
 
191
      wait; -- will wait forever
192
   END PROCESS;
193
-- *** End Test Bench - User Defined Section ***
194
 
195
 
196
  rom : PROCESS( cpu_addr, rom_data_out, ram_data_out )
197
  begin
198
    if( cpu_addr(15 downto 11) = "11111" ) then
199
      cpu_data_in <= rom_data_out;
200
                ram_cs <= '0';
201
         else
202
      cpu_data_in <= ram_data_out;
203
                ram_cs <= '1';
204
         end if;
205
  end process;
206
 
207
end behavior; --===================== End of architecture =======================--
208
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.