OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [Testbench/] [testbench6.vhd] - Blame information for rev 76

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 19 dilbert57
--===========================================================================----
2
--
3
--  T E S T B E N C H    tesetbench3 - CPU09 Testbench.
4
--
5
--  www.OpenCores.Org - September 2003
6
--  This core adheres to the GNU public license  
7
--
8
-- File name      : Testbench6.vhd
9
--
10
-- Purpose        : cpu09 Microprocessor Test Bench 6
11
--                  Tests STS indexed
12
--
13
-- Dependencies   : ieee.Std_Logic_1164
14
--                  ieee.std_logic_unsigned
15
--                  ieee.std_logic_arith
16
--                  ieee.numeric_std
17
--
18
-- Uses           : cpu09    (cpu09.vhd)      CPU core
19
--                   
20
-- Author         : John E. Kent
21
--                  dilbert57@opencores.org      
22
--
23
--===========================================================================----
24
--
25
-- Revision History:
26
--===========================================================================--
27
--
28
-- Version 0.1 - 12st April 2003 - John Kent 
29
-- First version
30
--
31
-- Version 1.0 - 6 Sep 2003 - John Kent
32
-- Initial release to Open Cores
33
--
34
-- Version 1.1 - 25th Jan 2004 - John Kent
35
-- removed "test_alu" and "test_cc"
36
--
37
--===========================================================================--
38
 
39
library ieee;
40
   use ieee.std_logic_1164.all;
41
   use IEEE.STD_LOGIC_ARITH.ALL;
42
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
43
   use ieee.numeric_std.all;
44
 
45
entity my_testbench6 is
46
end my_testbench6;
47
 
48
-------------------------------------------------------------------------------
49
-- Architecture for memio Controller Unit
50
-------------------------------------------------------------------------------
51
architecture behavior of my_testbench6 is
52
  -----------------------------------------------------------------------------
53
  -- Signals
54
  -----------------------------------------------------------------------------
55
  signal cpu_irq    : std_Logic;
56
  signal cpu_firq   : std_logic;
57
  signal cpu_nmi    : std_logic;
58
 
59
  -- CPU Interface signals
60
  signal SysClk      : Std_Logic;
61
  signal cpu_reset   : Std_Logic;
62
  signal cpu_rw      : Std_Logic;
63
  signal cpu_vma     : Std_Logic;
64
  signal cpu_addr    : Std_Logic_Vector(15 downto 0);
65
  signal cpu_data_in : Std_Logic_Vector(7 downto 0);
66
  signal cpu_data_out: Std_Logic_Vector(7 downto 0);
67
 
68
  constant width   : integer := 8;
69
  constant memsize : integer := 64;
70
 
71
  type rom_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
72
 
73
  constant rom_data : rom_array :=
74
  (
75
         x"10",x"CE", x"F8", x"30",                      -- F800 - 10CE F830 RET1    LDS #STACK
76
         x"CE",x"B0",x"00",                              -- F804 - CE B000           LDU #$B000
77
         x"10",x"EF",x"C8",x"00",                        -- F807 - 10EF C800         STS $00,U
78
         x"12",x"12",x"12",                              -- F80B - 12 12 12
79
         "00110011",                                     -- F8OE -   33             FCB $33 ; ACCB
80
         "00110100",                                     -- F8OF -   34             FCB $34 ; DPR
81
         "00110101", "00110110",                         -- F810 - 3536             FDB $3536 ; IX
82
    "00110111", "00111000",                         -- F812 - 3738             FDB $3738 ; IY
83
    "00111001", "00111010",                         -- F814 - 393A             FDB $393A ; UP
84
         "11111000", "00001001",                         -- F816 - F809             FDB SWI3VEC ; PC
85
         "10100001",                                     -- F818 -   A1      STACK2 FCB $A1 ; CC
86
         "00100010",                                     -- F819 -   22             FCB $22 ; ACCA
87
         "00100011",                                     -- F81A -   23             FCB $23 ; ACCB
88
         "00100100",                                     -- F81B -   24             FCB $24 ; DPR
89
         "00100101", "00100110",                         -- F81C - 2526             FDB $2526 ; IX
90
    "00100111", "00101000",                         -- F81E - 2728             FDB $2728 ; IY
91
    "00101001", "00101010",                         -- F820 - 292A             FDB $292A ; UP
92
         "11111000", "00001001",                         -- F822 - F809             FDB SWI3VEC ; PC
93
         "10010001",                                     -- F824 -   91      STACK1 FCB $91 ; CC
94
         "00010010",                                     -- F825 -   12             FCB $12 ; ACCA
95
         "00010011",                                     -- F826 -   13             FCB $13 ; ACCB
96
         "00010100",                                     -- F827 -   14             FCB $14 ; DPR
97
         "00010101", "00010110",                         -- F828 - 1516             FDB $1516 ; IX
98
    "00010111", "00011000",                         -- F82A - 1718             FDB $1718 ; IY
99
    "00011001", "00011010",                         -- F82C - 191A             FDB $191A ; UP
100
         "11111000", "00000000",                         -- F82E - F800             FDB RESET ; PC
101
                                                                                                                                         -- F830             STACK  EQU *
102
                                                                                                                                         --
103
                                                                                                                                         -- Interrupt Cectors Start Here
104
                                                                                                                                         --
105
         "11111000", "00000000",                         -- F830 - F800             FDB RESET ; RESV
106
    "11111000", "00001001",                         -- F832 - F809             FDB SWIVEC3 ; SWI3
107
         "11111000", "00000111",                         -- F834 - F807             FDB SWIVEC2 ; SWI2
108
         "11111000", "00000000",                         -- F836 - F800             fdb RESET ; FIRQ
109
         "11111000", "00000000",                         -- F838 - F800             fdb RESET ; IRQ
110
         "11111000", "00000101",                         -- F83A - F805             fdb SWIVEC ; SWI
111
         "11111000", "00000000",                         -- F83C - F800             fcb RESET ; NMI
112
         "11111000", "00000000"                          -- F83E - F800             fdb RESET ; Reset
113
         );
114
 
115
component cpu09
116
  port (
117
         clk:        in std_logic;
118
    rst:             in std_logic;
119
    rw:      out        std_logic;              -- Asynchronous memory interface
120
    vma:             out        std_logic;
121
    address:  out       std_logic_vector(15 downto 0);
122
    data_in:  in        std_logic_vector(7 downto 0);
123
         data_out: out std_logic_vector(7 downto 0);
124
         halt:     in  std_logic;
125
         hold:     in  std_logic;
126
         irq:      in  std_logic;
127
         nmi:      in  std_logic;
128
         firq:     in  std_logic
129
  );
130
end component cpu09;
131
 
132
 
133
begin
134
cpu : cpu09  port map (
135
         clk         => SysClk,
136
    rst      => cpu_reset,
137
    rw       => cpu_rw,
138
    vma       => cpu_vma,
139
    address   => cpu_addr(15 downto 0),
140
    data_in   => cpu_data_in,
141
         data_out  => cpu_data_out,
142
         halt      => '0',
143
         hold      => '0',
144
         irq       => cpu_irq,
145
         nmi       => cpu_nmi,
146
         firq      => cpu_firq
147
  );
148
 
149
  -- *** Test Bench - User Defined Section ***
150
   tb : PROCESS
151
        variable count : integer;
152
   BEGIN
153
 
154
        cpu_reset <= '0';
155
        SysClk <= '0';
156
   cpu_irq <= '0';
157
   cpu_nmi <= '0';
158
        cpu_firq <= '0';
159
 
160
                for count in 0 to 512 loop
161
                        SysClk <= '0';
162
                        if count = 0 then
163
                                cpu_reset <= '1';
164
                        elsif count = 1 then
165
                                cpu_reset <= '0';
166
                        end if;
167
                        wait for 100 ns;
168
                        SysClk <= '1';
169
                        wait for 100 ns;
170
                end loop;
171
 
172
      wait; -- will wait forever
173
   END PROCESS;
174
-- *** End Test Bench - User Defined Section ***
175
 
176
 
177
  rom : PROCESS( cpu_addr )
178
  begin
179
    cpu_data_in <= rom_data(conv_integer(cpu_addr(5 downto 0)));
180
  end process;
181
 
182
end behavior; --===================== End of architecture =======================--
183
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.