OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [VHDL/] [clock_dll.vhd] - Blame information for rev 186

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 118 dilbert57
--===========================================================================--
2
--                                                                           --
3
--  clock_dll.vhd - Synthesible System Clock Divider for Xilinx Spartan 3    --
4
--                                                                           --
5
--===========================================================================--
6 65 davidgb
--
7 118 dilbert57
--  File name      : clock_dll.vhd
8 65 davidgb
--
9 118 dilbert57
--  Purpose        : Implements a a system clock divider for System09. 
10
--                   For Xilinx Spartan 3 and 3E FPGA boards
11
--                   Assumes a 12.5 MHz system clock input
12
--                   Generates a x1 (12.5 MHz) CPU clock 
13
--                   Generates a x2 (25.0 MHz) VGA clock 
14
--                   Generates a x4 (50.0 MHz) MEM clock 
15
--                  
16
--  Dependencies   : ieee.std_logic_1164
17
--                   ieee.std_logic_arith
18 65 davidgb
--                   ieee.std_logic_unsigned
19 118 dilbert57
--                   ieee.numeric_std
20
--                   unisim.vcomponents
21
--
22
--  Author         : John E. Kent
23
--
24
--  Email          : dilbert57@opencores.org      
25
--
26
--  Web            : http://opencores.org/project,system09
27
--
28
--  clock_dll.vhd is a system clock divider for system09. 
29
-- 
30
--  Copyright (C) 2003 - 2010 John Kent
31
--
32
--  This program is free software: you can redistribute it and/or modify
33
--  it under the terms of the GNU General Public License as published by
34
--  the Free Software Foundation, either version 3 of the License, or
35
--  (at your option) any later version.
36
--
37
--  This program is distributed in the hope that it will be useful,
38
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
39
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
40
--  GNU General Public License for more details.
41
--
42
--  You should have received a copy of the GNU General Public License
43
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
44
--
45
--===========================================================================--
46
--                                                                           --
47
--                              Revision  History                            --
48
--                                                                           --
49
--===========================================================================--
50
--
51
-- Revision Name          Date             Description
52
-- 0.1      John E. Kent  7th September 2008 Initial version
53
-- 1.0      John E. Kent  30th May 2010      Added GPL Header
54
--
55 65 davidgb
library ieee;
56
   use ieee.std_logic_1164.all;
57 118 dilbert57
   use ieee.std_logic_arith.all;
58
   use ieee.std_logic_unsigned.all;
59 65 davidgb
   use ieee.numeric_std.all;
60
library unisim;
61
        use unisim.vcomponents.all;
62
 
63 118 dilbert57
entity clock_dll is
64 65 davidgb
  port(
65
    clk_in      : in  std_Logic;  -- System Clock input
66 118 dilbert57
    clk_cpu     : out std_logic;  -- CPU Clock Out       (x1)
67
         clk_vga     : out std_logic;  -- VGA Pixel Clock Out (x2)
68
         clk_mem     : out std_logic;  -- Memory Clock Out    (x4)
69
         locked      : out std_logic   -- DLL in lock
70
  );
71
end entity;
72
 
73 65 davidgb
architecture RTL of clock_dll is
74 118 dilbert57
 
75
  signal CPU_CLK0    : std_ulogic;
76
  signal CPU_CLK90   : std_ulogic;
77
  signal CPU_CLK180  : std_ulogic;
78
  signal CPU_CLK270  : std_ulogic;
79
  signal CPU_CLK2X   : std_ulogic;
80
  signal CPU_CLKDV   : std_ulogic;
81
  signal CPU_LOCKED  : std_ulogic;
82
  signal CPU_CLKFB   : std_ulogic;
83
  signal CPU_CLKIN   : std_ulogic;
84
  signal CPU_RESET   : std_ulogic;
85
 
86
  signal VGA_CLK0    : std_ulogic;
87
  signal VGA_CLK90   : std_ulogic;
88
  signal VGA_CLK180  : std_ulogic;
89
  signal VGA_CLK270  : std_ulogic;
90
  signal VGA_CLK2X   : std_ulogic;
91
  signal VGA_CLKDV   : std_ulogic;
92
  signal VGA_LOCKED  : std_ulogic;
93 65 davidgb
  signal VGA_CLKFB   : std_ulogic;
94 118 dilbert57
  signal VGA_CLKIN   : std_ulogic;
95 65 davidgb
  signal VGA_RESET   : std_ulogic;
96
  signal VGA_RESET_N : std_ulogic;
97 118 dilbert57
 
98
-- Component Declaration for CLKDLL should be placed
99
-- after architecture statement but before begin keyword
100
 
101
component CLKDLL
102
  -- synthesis translate_off
103
  generic (
104
    CLKDV_DIVIDE          : real    := 2.0;  -- (1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0, 16.0)
105
    DUTY_CYCLE_CORRECTION : Boolean := TRUE; -- (TRUE, FALSE)
106
    STARTUP_WAIT          : boolean := FALSE -- (TRUE, FALSE)
107
  );
108
  -- synthesis translate_on
109
  port (
110
    CLK0   : out STD_ULOGIC;
111
    CLK180 : out STD_ULOGIC;
112
    CLK270 : out STD_ULOGIC;
113
    CLK2X  : out STD_ULOGIC;
114
    CLK90  : out STD_ULOGIC;
115
    CLKDV  : out STD_ULOGIC;
116
    LOCKED : out STD_ULOGIC;
117
    CLKFB  : in  STD_ULOGIC;
118
    CLKIN  : in  STD_ULOGIC;
119
    RST    : in  STD_ULOGIC
120
  );
121
end component;
122
 
123 65 davidgb
component IBUFG
124
  port (
125
                i: in  std_logic;
126
                o: out std_logic
127
  );
128
end component;
129
 
130
component BUFG
131
  port (
132
                i: in  std_logic;
133
                o: out std_logic
134
  );
135
end component;
136 118 dilbert57
 
137
component SRL16
138
  port (
139
    Q   : out std_logic;
140
    D   : in  std_logic;
141
    CLK : in  std_logic;
142
    A0  : in  std_logic;
143
    A1  : in  std_logic;
144
    A2  : in  std_logic;
145
    A3  : in  std_logic
146
  );
147
end component;
148
 
149
--
150
-- Start instantiation
151
--
152
begin
153
 
154 65 davidgb
--
155
-- 12.5MHz CPU clock input
156
--
157 118 dilbert57
cpu_clkin_buffer : IBUFG
158 65 davidgb
  port map(
159
    i => clk_in,
160
         o => CPU_CLKIN
161
  );
162 118 dilbert57
 
163 65 davidgb
--
164
-- 12.5MHz CPU clock input
165
--
166 118 dilbert57
cpu_clkout_buffer : BUFG
167 65 davidgb
  port map(
168
    i => CPU_CLKIN,
169
         o => clk_cpu
170
  );
171 118 dilbert57
 
172 65 davidgb
--
173
-- 25 MHz VGA clock input
174
--
175 118 dilbert57
cpu_clkfb_buffer : BUFG
176 65 davidgb
  port map(
177
    i => CPU_CLK2X,
178
         o => CPU_CLKFB
179
  );
180 118 dilbert57
 
181
CLKDLL_CPU : CLKDLL
182
  -- synthesis translate_off
183
  generic map (
184
    CLKDV_DIVIDE          => 2.0,  -- (1.5,2,2.5,3,4,5,8,16)
185
    DUTY_CYCLE_CORRECTION => TRUE, -- (TRUE, FALSE)
186
    STARTUP_WAIT          => FALSE  -- (TRUE, FALSE)
187
  );
188
  -- synthesis translate_on
189
  port map (
190
    CLK0   => CPU_CLK0,
191
    CLK90  => CPU_CLK90,
192
    CLK180 => CPU_CLK180,
193
    CLK270 => CPU_CLK270,
194
    CLK2X  => CPU_CLK2X,
195
    CLKDV  => CPU_CLKDV,
196
    LOCKED => CPU_LOCKED,
197
    CLKFB  => CPU_CLKFB,
198
    CLKIN  => CPU_CLKIN,
199
    RST    => CPU_RESET
200
  );
201
 
202 65 davidgb
--
203
-- 25 MHz VGA clock output
204
--
205 118 dilbert57
vga_clkfb_buffer : BUFG
206 65 davidgb
  port map(
207
    i => VGA_CLK2X,
208
         o => VGA_CLKFB
209
  );
210 118 dilbert57
 
211
CLKDLL_VGA : CLKDLL
212
  -- synthesis translate_off
213
  generic map (
214
    CLKDV_DIVIDE          => 2.0,    -- (1.5,2,2.5,3,4,5,8,16)
215
    DUTY_CYCLE_CORRECTION => TRUE, -- (TRUE, FALSE)
216
    STARTUP_WAIT          => FALSE  -- (TRUE, FALSE)
217
  );
218
  -- synthesis translate_on
219
  port map (
220
    CLK0   => VGA_CLK0,
221
    CLK90  => VGA_CLK90,
222
    CLK180 => VGA_CLK180,
223
    CLK270 => VGA_CLK270,
224
    CLK2X  => VGA_CLK2X,
225
    CLKDV  => VGA_CLKDV,
226
    LOCKED => VGA_LOCKED,
227
    CLKFB  => VGA_CLKFB,
228
    CLKIN  => VGA_CLKIN,
229
    RST    => VGA_RESET
230
  );
231
 
232
my_srl16 : SRL16 port map (
233
  Q   => VGA_RESET_N,
234
  D   => CPU_LOCKED,
235
  CLK => CPU_CLKFB,
236
  A0  => '1',
237
  A1  => '1',
238
  A2  => '1',
239
  A3  => '1'
240
  );
241
 
242
clock_dll_assign : process( VGA_RESET_N, VGA_LOCKED,
243
                            clk_in, CPU_CLKFB, VGA_CLKFB )
244
begin
245
  VGA_RESET <= not VGA_RESET_N;
246
  VGA_CLKIN <= CPU_CLKFB;
247
  CPU_RESET <= '0';
248
  clk_vga   <= CPU_CLKFB;
249
  clk_mem   <= VGA_CLKFB;
250
  locked    <= VGA_LOCKED;
251
end process;
252
 
253
end architecture;
254 65 davidgb
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.