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1 122 dilbert57
--===========================================================================--
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--                                                                           --
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--        Synthesizable 6809 instruction compatible VHDL CPU core            --
4
--                                                                           --
5
--===========================================================================--
6
--
7
-- File name      : cpu09l.vhd
8
--
9
-- Entity name    : cpu09
10
--
11
-- Purpose        : 6809 instruction compatible CPU core written in VHDL
12
--                  with Last Instruction Cycle, bus available, bus status,
13
--                  and instruction fetch signals.
14
--                  Not cycle compatible with the original 6809 CPU
15
--
16
-- Dependencies   : ieee.std_logic_1164
17
--                  ieee.std_logic_unsigned
18
--
19
-- Author         : John E. Kent
20
--
21
-- Email          : dilbert57@opencores.org      
22
--
23
-- Web            : http://opencores.org/project,system09
24
--
25
-- Description    : VMA (valid memory address) is hight whenever a valid memory
26
--                  access is made by an instruction fetch, interrupt vector fetch
27
--                  or a data read or write otherwise it is low indicating an idle
28
--                  bus cycle.
29
--                  IFETCH (instruction fetch output) is high whenever an
30
--                  instruction byte is read i.e. the program counter is applied 
31
--                  to the address bus.
32
--                  LIC (last instruction cycle output) is normally low
33
--                  but goes high on the last cycle of an instruction.
34
--                  BA (bus available output) is normally low but goes high while
35
--                  waiting in a Sync instruction state or the CPU is halted
36
--                  i.e. a DMA grant.
37
--                  BS (bus status output) is normally low but goes high during an
38
--                  interrupt or reset vector fetch or the processor is halted
39
--                  i.e. a DMA grant.
40
-- 
41
--  Copyright (C) 2003 - 2010 John Kent
42
--
43
--  This program is free software: you can redistribute it and/or modify
44
--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
48
--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
50
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
52
--
53
--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
55
--
56
--===========================================================================--
57
--                                                                           --
58
--                                Revision History                           --
59
--                                                                           --
60
--===========================================================================--
61
--
62
-- Version 0.1 - 26 June 2003 - John Kent
63
-- Added extra level in state stack
64
-- fixed some calls to the extended addressing state
65
--
66
-- Version 0.2 - 5 Sept 2003 - John Kent
67
-- Fixed 16 bit indexed offset (was doing read rather than fetch)
68
-- Added/Fixed STY and STS instructions.
69
-- ORCC_STATE ANDed CC state rather than ORed it - Now fixed
70
-- CMPX Loaded ACCA and ACCB - Now fixed 
71
--
72
-- Version 1.0 - 6 Sep 2003 - John Kent 
73
-- Initial release to Open Cores
74
-- reversed clock edge
75
--
76
-- Version 1.1 - 29 November 2003 John kent
77
--      ACCA and ACCB indexed offsets are 2's complement.
78
-- ALU Right Mux now sign extends ACCA & ACCB offsets
79
-- Absolute Indirect addressing performed a read on the
80
-- second byte of the address rather than a fetch
81
-- so it formed an incorrect address. Now fixed. 
82
--
83
-- Version 1.2 - 29 November 2003 John Kent
84
-- LEAX and LEAY affect the Z bit only
85
--      LEAS and LEAU do not affect any condition codes
86
-- added an extra ALU control for LEA.
87
--
88
-- Version 1.3 - 12 December 2003 John Kent
89
-- CWAI did not work, was missed a PUSH_ST on calling
90
-- the ANDCC_STATE. Thanks go to Ghassan Kraidy for
91
-- finding this fault.
92
--
93
-- Version 1.4 - 12 December 2003 John Kent
94
-- Missing cc_ctrl assignment in otherwise case of 
95
-- lea_state resulted in cc_ctrl being latched in
96
-- that state.  
97
-- The otherwise statement should never be reached,
98
-- and has been fixed simply to resolve synthesis warnings.
99
--
100
-- Version 1.5 - 17 january 2004 John kent
101
-- The clear instruction used "alu_ld8" to control the ALU
102
-- rather than "alu_clr". This mean the Carry was not being
103
-- cleared correctly.
104
--
105
-- Version 1.6 - 24 January 2004 John Kent
106
-- Fixed problems in PSHU instruction
107
--
108
-- Version 1.7 - 25 January 2004 John Kent
109
-- removed redundant "alu_inx" and "alu_dex'
110
-- Removed "test_alu" and "test_cc"
111
-- STD instruction did not set condition codes
112
-- JMP direct was not decoded properly
113
-- CLR direct performed an unwanted read cycle
114
-- Bogus "latch_md" in Page2 indexed addressing
115
--
116
-- Version 1.8 - 27 January 2004 John Kent
117
-- CWAI in decode1_state should increment the PC.
118
-- ABX is supposed to be an unsigned addition.
119
-- Added extra ALU function
120
-- ASR8 slightly changed in the ALU.
121
--
122
--      Version 1.9 - 20 August 2005
123
-- LSR8 is now handled in ASR8 and ROR8 case in the ALU,
124
-- rather than LSR16. There was a problem with single 
125
-- operand instructions using the MD register which is
126
-- sign extended on the first 8 bit fetch.
127
--
128
-- Version 1.10 - 13 September 2005
129
-- TFR & EXG instructions did not work for the Condition Code Register
130
-- An extra case has been added to the ALU for the alu_tfr control 
131
-- to assign the left ALU input (alu_left) to the condition code
132
-- outputs (cc_out). 
133
--
134
-- Version 1.11 - 16 September 2005
135
-- JSR ,X should not predecrement S before calculating the jump address.
136
-- The reason is that JSR [0,S] needs S to point to the top of the stack
137
-- to fetch a valid vector address. The solution is to have the addressing
138
-- mode microcode called before decrementing S and then decrementing S in
139
-- JSR_STATE. JSR_STATE in turn calls PUSH_RETURN_LO_STATE rather than
140
-- PUSH_RETURN_HI_STATE so that both the High & Low halves of the PC are
141
-- pushed on the stack. This adds one extra bus cycle, but resolves the
142
-- addressing conflict. I've also removed the pre-decement S in 
143
-- JSR EXTENDED as it also calls JSR_STATE.
144
--
145
-- Version 1.12 - 6th June 2006
146
-- 6809 Programming reference manual says V is not affected by ASR, LSR and ROR
147
-- This is different to the 6800. CLR should reset the V bit.
148
--
149
-- Version 1.13 - 7th July 2006
150
-- Disable NMI on reset until S Stack pointer has been loaded.
151
-- Added nmi_enable signal in sp_reg process and nmi_handler process.
152
--
153
-- Version 1.14 - 11th July 2006
154
-- 1. Added new state to RTI called rti_entire_state.
155
-- This state tests the CC register after it has been loaded
156
-- from the stack. Previously the current CC was tested which
157
-- was incorrect. The Entire Flag should be set before the
158
-- interrupt stacks the CC.
159
-- 2. On bogus Interrupts, int_cc_state went to rti_state,
160
-- which was an enumerated state, but not defined anywhere.
161
-- rti_state has been changed to rti_cc_state so that bogus interrupt
162
-- will perform an RTI after entering that state.
163
-- 3. Sync should generate an interrupt if the interrupt masks
164
-- are cleared. If the interrupt masks are set, then an interrupt
165
-- will cause the the PC to advance to the next instruction.
166
-- Note that I don't wait for an interrupt to be asserted for
167
-- three clock cycles.
168
-- 4. Added new ALU control state "alu_mul". "alu_mul" is used in
169
-- the Multiply instruction replacing "alu_add16". This is similar 
170
-- to "alu_add16" except it sets the Carry bit to B7 of the result
171
-- in ACCB, sets the Zero bit if the 16 bit result is zero, but
172
-- does not affect The Half carry (H), Negative (N) or Overflow (V)
173
-- flags. The logic was re-arranged so that it adds md or zero so 
174
-- that the Carry condition code is set on zero multiplicands.
175
-- 5. DAA (Decimal Adjust Accumulator) should set the Negative (N)
176
-- and Zero Flags. It will also affect the Overflow (V) flag although
177
-- the operation is undefined. It's anyones guess what DAA does to V.
178
--
179
-- Version 1.15 - 25th Feb 2007 - John Kent
180
-- line 9672 changed "if Halt <= '1' then" to "if Halt = '1' then"
181
-- Changed sensitivity lists.
182
--
183
-- Version 1.16 - 5th February 2008 - John Kent
184
-- FIRQ interrupts should take priority over IRQ Interrupts.
185
-- This presumably means they should be tested for before IRQ
186
-- when they happen concurrently.
187
--
188
-- Version 1.17 - 18th February 2008 - John Kent
189
-- NMI in CWAI should mask IRQ and FIRQ interrupts
190
--
191
-- Version 1.18 - 21st February 2008 - John Kent
192
-- Removed default register settings in each case statement
193
-- and placed them at the beginning of the state sequencer.
194
-- Modified the SYNC instruction so that the interrupt vector(iv)
195
-- is not set unless an unmasked FIRQ or IRQ is received.
196
--
197
-- Version 1.19 - 25th February 2008 - John Kent
198
-- Enumerated separate states for FIRQ/FAST and NMIIRQ/ENTIRE
199
-- Enumerated separate states for MASKI and MASKIF states
200
-- Removed code on BSR/JSR in fetch cycle
201
--
202 130 dilbert57
-- Version 1.20 - 8th October 2011 - John Kent
203 122 dilbert57
-- added fetch output which should go high during the fetch cycle
204
--
205 130 dilbert57
-- Version 1.21 - 8th October 2011 - John Kent
206 122 dilbert57
-- added Last Instruction Cycle signal
207
-- replaced fetch with ifetch (instruction fetch) signal
208
-- added ba & bs (bus available & bus status) signals
209
--
210 130 dilbert57
-- Version 1.22 - 2011-10-29 John Kent
211
-- The halt state isn't correct. 
212
-- The halt state is entered into from the fetch_state
213
-- It returned to the fetch state which may re-run an execute cycle
214
-- on the accumulator and it won't necessarily be the last instruction cycle
215
-- I've changed the halt state to return to the decode1_state
216
--
217
-- Version 1.23 - 2011-10-30 John Kent
218
-- sample halt in the change_state process if lic is high (last instruction cycle)
219
--
220
-- Version 1.24 - 2011-11-01 John Kent
221
-- Handle interrupts in change_state process
222
-- Sample interrupt inputs on last instruction cycle
223
-- Remove iv_ctrl and implement iv (interrupt vector) in change_state process.
224
-- Generate fic (first instruction cycle) from lic (last instruction cycle)
225
-- and use it to complete the dual operand execute cycle before servicing
226
-- halt or interrupts requests.
227
-- rename lic to lic_out on the entity declaration so that lic can be tested internally.
228
-- add int_firq1_state and int_nmirq1_state to allow for the dual operand execute cycle
229
-- integrated nmi_ctrl into change_state process
230
-- Reduces the microcode state stack to one entry (saved_state)
231
-- imm16_state jumps directly to the fetch_state
232
-- pull_return_lo states jumps directly to the fetch_state
233
-- duplicate andcc_state as cwai_state
234
-- rename exg1_state as exg2 state and duplicate tfr_state as exg1_state
235
--
236
-- Version 1.25 - 2011-11-27 John Kent
237
-- Changed the microcode for saving registers on an interrupt into a microcode subroutine.
238
-- Removed SWI servicing from the change state process and made SWI, SWI2 & SWI3
239
-- call the interrupt microcode subroutine.
240
-- Added additional states for nmi, and irq for interrupt servicing.
241
-- Added additional states for nmi/irq, firq, and swi interrupts to mask I & F flags.
242
--
243
-- Version 1.26 - 2013-03-18 John Kent
244
-- pre-initialized cond_true variable to true in state sequencer
245
-- re-arranged change_state process slightly
246
--
247
-- Version 1.27 - 2015-05-30 John Kent
248
-- Added test in state machine for masked IRQ and FIRQ in Sync_state.
249
--
250
-- Version 1.28 - 2015-05-30 John Kent.
251
-- Moved IRQ and FIRQ test from state machine to the state sequencer Sync_state.
252
-- 
253 122 dilbert57
library ieee;
254
use ieee.std_logic_1164.all;
255
use ieee.std_logic_unsigned.all;
256
 
257
entity cpu09 is
258
        port (
259
                clk      :      in std_logic;                     -- E clock input (falling edge)
260
                rst      :  in std_logic;                     -- reset input (active high)
261
                vma      : out std_logic;                     -- valid memory address (active high)
262 130 dilbert57
      lic_out  : out std_logic;                     -- last instruction cycle (active high)
263 122 dilbert57
      ifetch   : out std_logic;                     -- instruction fetch cycle (active high)
264 130 dilbert57
      opfetch  : out std_logic;                     -- opcode fetch (active high)
265 122 dilbert57
      ba       : out std_logic;                     -- bus available (high on sync wait or DMA grant)
266
      bs       : out std_logic;                     -- bus status (high on interrupt or reset vector fetch or DMA grant)
267
                addr     : out std_logic_vector(15 downto 0); -- address bus output
268
                rw       : out std_logic;                     -- read not write output
269
           data_out : out std_logic_vector(7 downto 0);  -- data bus output
270
           data_in  :  in std_logic_vector(7 downto 0);  -- data bus input
271
                irq      :  in std_logic;                     -- interrupt request input (active high)
272
                firq     :  in std_logic;                     -- fast interrupt request input (active high)
273
                nmi      :  in std_logic;                     -- non maskable interrupt request input (active high)
274
                halt     :  in std_logic;                     -- halt input (active high) grants DMA
275
                hold     :  in std_logic                      -- hold input (active high) extend bus cycle
276
                );
277
end cpu09;
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279
architecture rtl of cpu09 is
280
 
281
  constant EBIT : integer := 7;
282
  constant FBIT : integer := 6;
283
  constant HBIT : integer := 5;
284
  constant IBIT : integer := 4;
285
  constant NBIT : integer := 3;
286
  constant ZBIT : integer := 2;
287
  constant VBIT : integer := 1;
288
  constant CBIT : integer := 0;
289
 
290
  --
291
  -- Interrupt vector modifiers
292
  --
293
  constant RST_VEC  : std_logic_vector(2 downto 0) := "111";
294
  constant NMI_VEC  : std_logic_vector(2 downto 0) := "110";
295
  constant SWI_VEC  : std_logic_vector(2 downto 0) := "101";
296
  constant IRQ_VEC  : std_logic_vector(2 downto 0) := "100";
297
  constant FIRQ_VEC : std_logic_vector(2 downto 0) := "011";
298
  constant SWI2_VEC : std_logic_vector(2 downto 0) := "010";
299
  constant SWI3_VEC : std_logic_vector(2 downto 0) := "001";
300
  constant RESV_VEC : std_logic_vector(2 downto 0) := "000";
301
 
302
        type state_type is (-- Start off in Reset
303
                            reset_state,
304
                                                          -- Fetch Interrupt Vectors (including reset)
305 130 dilbert57
                                                          vect_lo_state, vect_hi_state, vect_idle_state,
306 122 dilbert57
                       -- Fetch Instruction Cycle
307
                       fetch_state,
308
                                                          -- Decode Instruction Cycles
309
                       decode1_state, decode2_state, decode3_state,
310
                                                          -- Calculate Effective Address
311
                                                     imm16_state,
312
                                 indexed_state, index8_state, index16_state, index16_2_state,
313
                                                          pcrel8_state, pcrel16_state, pcrel16_2_state,
314
                                                          indexaddr_state, indexaddr2_state,
315
                                                     postincr1_state, postincr2_state,
316
                                                          indirect_state, indirect2_state, indirect3_state,
317
                       extended_state,
318
                                                          -- single ops
319
                                                          single_op_read_state,
320
                                                     single_op_exec_state,
321
                            single_op_write_state,
322
                                                          -- Dual op states
323
                                                          dual_op_read8_state, dual_op_read16_state, dual_op_read16_2_state,
324
                                                     dual_op_write8_state, dual_op_write16_state,
325
                       -- 
326 130 dilbert57
                                                     sync_state, halt_state, cwai_state,
327 122 dilbert57
                                                          --
328
                                                          andcc_state, orcc_state,
329 130 dilbert57
                                                          tfr_state,
330
                       exg_state, exg1_state, exg2_state,
331 122 dilbert57
                                                          lea_state,
332
                                                          -- Multiplication
333
                                                     mul_state, mulea_state, muld_state,
334
                                                     mul0_state, mul1_state, mul2_state, mul3_state,
335
                                                     mul4_state, mul5_state, mul6_state, mul7_state,
336
                                                          --  Branches
337
                                                          lbranch_state, sbranch_state,
338
                                                          -- Jumps, Subroutine Calls and Returns
339
                       jsr_state, jmp_state,
340
                       push_return_hi_state, push_return_lo_state,
341
                       pull_return_hi_state, pull_return_lo_state,
342
                                                          -- Interrupt cycles
343 130 dilbert57
                                                          int_nmi_state, int_nmi1_state,
344
                                                          int_irq_state, int_irq1_state,
345
                       int_firq_state,  int_firq1_state,
346 122 dilbert57
                                                          int_entire_state, int_fast_state,
347
                                                          int_pcl_state,  int_pch_state,
348
                                                     int_upl_state,  int_uph_state,
349
                                                     int_iyl_state,  int_iyh_state,
350
                                                     int_ixl_state,  int_ixh_state,
351
                                                     int_dp_state,
352
                                           int_accb_state, int_acca_state,
353
                                                     int_cc_state,
354
                                                     int_cwai_state,
355 130 dilbert57
                                                          int_nmimask_state, int_firqmask_state, int_swimask_state, int_irqmask_state,
356 122 dilbert57
                                                          -- Return From Interrupt
357
                                                     rti_cc_state,   rti_entire_state,
358
                                                          rti_acca_state, rti_accb_state,
359
                                                     rti_dp_state,
360
                                                     rti_ixl_state,  rti_ixh_state,
361
                                                     rti_iyl_state,  rti_iyh_state,
362
                                                     rti_upl_state,  rti_uph_state,
363
                                                     rti_pcl_state,  rti_pch_state,
364
                                                          -- Push Registers using SP
365
                                                          pshs_state,
366
                                                     pshs_pcl_state,  pshs_pch_state,
367
                                                     pshs_upl_state,  pshs_uph_state,
368
                                                     pshs_iyl_state,  pshs_iyh_state,
369
                                                     pshs_ixl_state,  pshs_ixh_state,
370
                                                     pshs_dp_state,
371
                                                     pshs_acca_state, pshs_accb_state,
372
                                                     pshs_cc_state,
373
                                                          -- Pull Registers using SP
374
                                                          puls_state,
375
                                                          puls_cc_state,
376
                                                          puls_acca_state, puls_accb_state,
377
                                                          puls_dp_state,
378
                                                     puls_ixl_state,  puls_ixh_state,
379
                                                     puls_iyl_state,  puls_iyh_state,
380
                                                     puls_upl_state,  puls_uph_state,
381
                                                     puls_pcl_state,  puls_pch_state,
382
                                                          -- Push Registers using UP
383
                                                          pshu_state,
384
                                                     pshu_pcl_state,  pshu_pch_state,
385
                                                     pshu_spl_state,  pshu_sph_state,
386
                                                     pshu_iyl_state,  pshu_iyh_state,
387
                                                     pshu_ixl_state,  pshu_ixh_state,
388
                                                     pshu_dp_state,
389
                                                     pshu_acca_state, pshu_accb_state,
390
                                                     pshu_cc_state,
391
                                                          -- Pull Registers using UP
392
                                                          pulu_state,
393
                                                          pulu_cc_state,
394
                                                          pulu_acca_state, pulu_accb_state,
395
                                                          pulu_dp_state,
396
                                                     pulu_ixl_state,  pulu_ixh_state,
397
                                                     pulu_iyl_state,  pulu_iyh_state,
398
                                                     pulu_spl_state,  pulu_sph_state,
399
                                                     pulu_pcl_state,  pulu_pch_state );
400
 
401 130 dilbert57
        type st_type    is (reset_st, push_st, idle_st );
402
        type iv_type    is (latch_iv, swi3_iv, swi2_iv, firq_iv, irq_iv, swi_iv, nmi_iv, reset_iv);
403 122 dilbert57
        type addr_type  is (idle_ad, fetch_ad, read_ad, write_ad, pushu_ad, pullu_ad, pushs_ad, pulls_ad, int_hi_ad, int_lo_ad );
404
        type dout_type  is (cc_dout, acca_dout, accb_dout, dp_dout,
405
                       ix_lo_dout, ix_hi_dout, iy_lo_dout, iy_hi_dout,
406
                       up_lo_dout, up_hi_dout, sp_lo_dout, sp_hi_dout,
407
                       pc_lo_dout, pc_hi_dout, md_lo_dout, md_hi_dout );
408
   type op_type    is (reset_op, fetch_op, latch_op );
409
   type pre_type   is (reset_pre, fetch_pre, latch_pre );
410
   type cc_type    is (reset_cc, load_cc, pull_cc, latch_cc );
411
   type acca_type  is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca );
412
   type accb_type  is (reset_accb, load_accb, pull_accb, latch_accb );
413
   type dp_type    is (reset_dp, load_dp, pull_dp, latch_dp );
414
        type ix_type    is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix );
415
        type iy_type    is (reset_iy, load_iy, pull_lo_iy, pull_hi_iy, latch_iy );
416
        type sp_type    is (reset_sp, latch_sp, load_sp, pull_hi_sp, pull_lo_sp );
417
        type up_type    is (reset_up, latch_up, load_up, pull_hi_up, pull_lo_up );
418
        type pc_type    is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc, incr_pc );
419
   type md_type    is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md );
420
   type ea_type    is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea );
421
        type left_type  is (cc_left, acca_left, accb_left, dp_left,
422
                                                          ix_left, iy_left, up_left, sp_left,
423
                       accd_left, md_left, pc_left, ea_left );
424
        type right_type is (ea_right, zero_right, one_right, two_right,
425
                       acca_right, accb_right, accd_right,
426
                                                          md_right, md_sign5_right, md_sign8_right );
427
   type alu_type   is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc,
428
                       alu_and, alu_ora, alu_eor,
429
                       alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com,
430
                                                     alu_lsr16, alu_lsl16,
431
                                                     alu_ror8, alu_rol8, alu_mul,
432
                                                     alu_asr8, alu_asl8, alu_lsr8,
433
                                                     alu_andcc, alu_orcc, alu_sex, alu_tfr, alu_abx,
434
                                                          alu_seif, alu_sei, alu_see, alu_cle,
435
                                                     alu_ld8, alu_st8, alu_ld16, alu_st16, alu_lea, alu_nop, alu_daa );
436
 
437
        signal op_code:     std_logic_vector(7 downto 0);
438
        signal pre_code:    std_logic_vector(7 downto 0);
439
        signal acca:        std_logic_vector(7 downto 0);
440
        signal accb:        std_logic_vector(7 downto 0);
441
   signal cc:          std_logic_vector(7 downto 0);
442
        signal cc_out:      std_logic_vector(7 downto 0);
443
        signal dp:          std_logic_vector(7 downto 0);
444
        signal xreg:        std_logic_vector(15 downto 0);
445
        signal yreg:        std_logic_vector(15 downto 0);
446
        signal sp:          std_logic_vector(15 downto 0);
447
        signal up:          std_logic_vector(15 downto 0);
448
        signal ea:          std_logic_vector(15 downto 0);
449
        signal pc:              std_logic_vector(15 downto 0);
450
        signal md:          std_logic_vector(15 downto 0);
451
   signal left:        std_logic_vector(15 downto 0);
452
   signal right:       std_logic_vector(15 downto 0);
453
        signal out_alu:     std_logic_vector(15 downto 0);
454
        signal iv:          std_logic_vector(2 downto 0);
455
        signal nmi_req:     std_logic;
456
        signal nmi_ack:     std_logic;
457
        signal nmi_enable:  std_logic;
458 130 dilbert57
   signal fic:         std_logic; -- first instruction cycle
459
   signal lic:         std_logic; -- last instruction cycle
460 122 dilbert57
 
461
        signal state:        state_type;
462
        signal next_state:   state_type;
463 130 dilbert57
        signal return_state: state_type;
464 122 dilbert57
        signal saved_state:  state_type;
465
        signal st_ctrl:      st_type;
466 130 dilbert57
        signal iv_ctrl:      iv_type;
467 122 dilbert57
   signal pc_ctrl:      pc_type;
468
   signal ea_ctrl:      ea_type;
469
   signal op_ctrl:      op_type;
470
        signal pre_ctrl:     pre_type;
471
        signal md_ctrl:      md_type;
472
        signal acca_ctrl:    acca_type;
473
        signal accb_ctrl:    accb_type;
474
        signal ix_ctrl:      ix_type;
475
        signal iy_ctrl:      iy_type;
476
        signal cc_ctrl:      cc_type;
477
        signal dp_ctrl:      dp_type;
478
        signal sp_ctrl:      sp_type;
479
        signal up_ctrl:      up_type;
480
        signal left_ctrl:    left_type;
481
        signal right_ctrl:   right_type;
482
   signal alu_ctrl:     alu_type;
483
   signal addr_ctrl:    addr_type;
484
   signal dout_ctrl:    dout_type;
485
 
486
 
487
begin
488
 
489
----------------------------------
490
--
491
-- State machine stack
492
--
493
----------------------------------
494
--state_stack_proc: process( clk, hold, state_stack, st_ctrl, 
495
--                           return_state, fetch_state  )
496 130 dilbert57
state_stack_proc: process( clk, st_ctrl, return_state )
497 122 dilbert57
begin
498
  if clk'event and clk = '0' then
499 130 dilbert57
    if hold = '0' then
500 122 dilbert57
           case st_ctrl is
501 130 dilbert57
      when reset_st =>
502
        saved_state <= fetch_state;
503 122 dilbert57
      when push_st =>
504 130 dilbert57
                  saved_state <= return_state;
505 122 dilbert57
                when others =>
506 130 dilbert57
        null;
507 122 dilbert57
           end case;
508
    end if;
509
  end if;
510
end process;
511
 
512
----------------------------------
513
--
514 130 dilbert57
-- Interrupt Vector control
515
--
516
----------------------------------
517
--
518
int_vec_proc: process( clk, iv_ctrl )
519
begin
520
  if clk'event and clk = '0' then
521
    if hold = '0' then
522
      case iv_ctrl is
523
      when reset_iv =>
524
        iv <= RST_VEC;
525
      when nmi_iv =>
526
        iv <= NMI_VEC;
527
      when swi_iv =>
528
        iv <= SWI_VEC;
529
      when irq_iv =>
530
        iv <= IRQ_VEC;
531
      when firq_iv =>
532
        iv <= FIRQ_VEC;
533
      when swi2_iv =>
534
        iv <= SWI2_VEC;
535
      when swi3_iv =>
536
        iv <= SWI3_VEC;
537
                when others =>
538
                  null;
539
      end case;
540
    end if; -- hold
541
  end if; -- clk
542
end process;
543
 
544
----------------------------------
545
--
546 122 dilbert57
-- Program Counter Control
547
--
548
----------------------------------
549
 
550
--pc_reg: process( clk, pc_ctrl, hold, pc, out_alu, data_in )
551
pc_reg: process( clk )
552
begin
553
  if clk'event and clk = '0' then
554 130 dilbert57
    if hold = '0' then
555 122 dilbert57
    case pc_ctrl is
556
         when reset_pc =>
557 130 dilbert57
           pc <= (others=>'0');
558 122 dilbert57
         when load_pc =>
559
           pc <= out_alu(15 downto 0);
560
         when pull_lo_pc =>
561
           pc(7 downto 0) <= data_in;
562
         when pull_hi_pc =>
563
           pc(15 downto 8) <= data_in;
564
         when incr_pc =>
565
           pc <= pc + 1;
566
         when others =>
567 130 dilbert57
      null;
568 122 dilbert57
    end case;
569
         end if;
570
  end if;
571
end process;
572
 
573
----------------------------------
574
--
575
-- Effective Address  Control
576
--
577
----------------------------------
578
 
579
--ea_reg: process( clk, ea_ctrl, hold, ea, out_alu, data_in, dp )
580
ea_reg: process( clk )
581
begin
582
 
583
  if clk'event and clk = '0' then
584 130 dilbert57
    if hold= '0' then
585 122 dilbert57
    case ea_ctrl is
586
         when reset_ea =>
587 130 dilbert57
           ea <= (others=>'0');
588 122 dilbert57
         when fetch_first_ea =>
589
           ea(7 downto 0) <= data_in;
590
      ea(15 downto 8) <= dp;
591
         when fetch_next_ea =>
592
           ea(15 downto 8) <= ea(7 downto 0);
593
      ea(7 downto 0)  <= data_in;
594
         when load_ea =>
595
           ea <= out_alu(15 downto 0);
596
         when others =>
597 130 dilbert57
      null;
598 122 dilbert57
    end case;
599
         end if;
600
  end if;
601
end process;
602
 
603
--------------------------------
604
--
605
-- Accumulator A
606
--
607
--------------------------------
608
--acca_reg : process( clk, acca_ctrl, hold, out_alu, acca, data_in )
609
acca_reg : process( clk )
610
begin
611
  if clk'event and clk = '0' then
612 130 dilbert57
    if hold = '0' then
613 122 dilbert57
    case acca_ctrl is
614
    when reset_acca =>
615 130 dilbert57
           acca <= (others=>'0');
616 122 dilbert57
         when load_acca =>
617
           acca <= out_alu(7 downto 0);
618
         when load_hi_acca =>
619
           acca <= out_alu(15 downto 8);
620
         when pull_acca =>
621
           acca <= data_in;
622
         when others =>
623 130 dilbert57
      null;
624 122 dilbert57
    end case;
625
         end if;
626
  end if;
627
end process;
628
 
629
--------------------------------
630
--
631
-- Accumulator B
632
--
633
--------------------------------
634
--accb_reg : process( clk, accb_ctrl, hold, out_alu, accb, data_in )
635
accb_reg : process( clk )
636
begin
637
  if clk'event and clk = '0' then
638 130 dilbert57
    if hold = '0' then
639 122 dilbert57
    case accb_ctrl is
640
    when reset_accb =>
641 130 dilbert57
           accb <= (others=>'0');
642 122 dilbert57
         when load_accb =>
643
           accb <= out_alu(7 downto 0);
644
         when pull_accb =>
645
           accb <= data_in;
646
         when others =>
647 130 dilbert57
      null;
648 122 dilbert57
    end case;
649
         end if;
650
  end if;
651
end process;
652
 
653
--------------------------------
654
--
655
-- X Index register
656
--
657
--------------------------------
658
--ix_reg : process( clk, ix_ctrl, hold, out_alu, xreg, data_in )
659
ix_reg : process( clk )
660
begin
661
  if clk'event and clk = '0' then
662 130 dilbert57
    if hold = '0' then
663 122 dilbert57
    case ix_ctrl is
664
    when reset_ix =>
665 130 dilbert57
           xreg <= (others=>'0');
666 122 dilbert57
         when load_ix =>
667
           xreg <= out_alu(15 downto 0);
668
         when pull_hi_ix =>
669
           xreg(15 downto 8) <= data_in;
670
         when pull_lo_ix =>
671
           xreg(7 downto 0) <= data_in;
672
         when others =>
673 130 dilbert57
      null;
674 122 dilbert57
    end case;
675
         end if;
676
  end if;
677
end process;
678
 
679
--------------------------------
680
--
681
-- Y Index register
682
--
683
--------------------------------
684
--iy_reg : process( clk, iy_ctrl, hold, out_alu, yreg, data_in )
685
iy_reg : process( clk )
686
begin
687
  if clk'event and clk = '0' then
688 130 dilbert57
    if hold = '0' then
689 122 dilbert57
    case iy_ctrl is
690
    when reset_iy =>
691 130 dilbert57
           yreg <= (others=>'0');
692 122 dilbert57
         when load_iy =>
693
           yreg <= out_alu(15 downto 0);
694
         when pull_hi_iy =>
695
           yreg(15 downto 8) <= data_in;
696
         when pull_lo_iy =>
697
           yreg(7 downto 0) <= data_in;
698
         when others =>
699 130 dilbert57
      null;
700 122 dilbert57
    end case;
701
         end if;
702
  end if;
703
end process;
704
 
705
--------------------------------
706
--
707
-- S stack pointer
708
--
709
--------------------------------
710
--sp_reg : process( clk, sp_ctrl, hold, sp, out_alu, data_in, nmi_enable )
711
sp_reg : process( clk )
712
begin
713
  if clk'event and clk = '0' then
714 130 dilbert57
    if hold = '0' then
715 122 dilbert57
    case sp_ctrl is
716
    when reset_sp =>
717 130 dilbert57
           sp <= (others=>'0');
718 122 dilbert57
                nmi_enable <= '0';
719
         when load_sp =>
720
           sp <= out_alu(15 downto 0);
721
                nmi_enable <= '1';
722
         when pull_hi_sp =>
723
           sp(15 downto 8) <= data_in;
724
         when pull_lo_sp =>
725
           sp(7 downto 0) <= data_in;
726
                nmi_enable <= '1';
727
         when others =>
728 130 dilbert57
      null;
729 122 dilbert57
    end case;
730
         end if;
731
  end if;
732
end process;
733
 
734
--------------------------------
735
--
736
-- U stack pointer
737
--
738
--------------------------------
739
--up_reg : process( clk, up_ctrl, hold, up, out_alu, data_in )
740
up_reg : process( clk )
741
begin
742
  if clk'event and clk = '0' then
743 130 dilbert57
    if hold = '0' then
744 122 dilbert57
    case up_ctrl is
745
    when reset_up =>
746 130 dilbert57
           up <= (others=>'0');
747 122 dilbert57
         when load_up =>
748
           up <= out_alu(15 downto 0);
749
         when pull_hi_up =>
750
           up(15 downto 8) <= data_in;
751
         when pull_lo_up =>
752
           up(7 downto 0) <= data_in;
753
         when others =>
754 130 dilbert57
      null;
755 122 dilbert57
    end case;
756
         end if;
757
  end if;
758
end process;
759
 
760
--------------------------------
761
--
762
-- Memory Data
763
--
764
--------------------------------
765
--md_reg : process( clk, md_ctrl, hold, out_alu, data_in, md )
766
md_reg : process( clk )
767
begin
768
  if clk'event and clk = '0' then
769 130 dilbert57
    if hold = '0' then
770 122 dilbert57
    case md_ctrl is
771
    when reset_md =>
772 130 dilbert57
           md <= (others=>'0');
773 122 dilbert57
         when load_md =>
774
           md <= out_alu(15 downto 0);
775
         when fetch_first_md => -- sign extend md for branches
776
           md(15 downto 8) <= data_in(7) & data_in(7) & data_in(7) & data_in(7) &
777
                              data_in(7) & data_in(7) & data_in(7) & data_in(7) ;
778
           md(7 downto 0) <= data_in;
779
         when fetch_next_md =>
780
           md(15 downto 8) <= md(7 downto 0);
781
                md(7 downto 0) <= data_in;
782
         when shiftl_md =>
783
           md(15 downto 1) <= md(14 downto 0);
784
                md(0) <= '0';
785
         when others =>
786 130 dilbert57
      null;
787 122 dilbert57
    end case;
788
         end if;
789
  end if;
790
end process;
791
 
792
 
793
----------------------------------
794
--
795
-- Condition Codes
796
--
797
----------------------------------
798
 
799
--cc_reg: process( clk, cc_ctrl, hold, cc_out, cc, data_in )
800
cc_reg: process( clk )
801
begin
802
  if clk'event and clk = '0' then
803 130 dilbert57
    if hold = '0' then
804 122 dilbert57
    case cc_ctrl is
805
         when reset_cc =>
806
           cc <= "11010000"; -- set EBIT, FBIT & IBIT
807
         when load_cc =>
808
           cc <= cc_out;
809
         when pull_cc =>
810
      cc <= data_in;
811
         when others =>
812 130 dilbert57
      null;
813 122 dilbert57
    end case;
814
         end if;
815
  end if;
816
end process;
817
 
818
----------------------------------
819
--
820
-- Direct Page register
821
--
822
----------------------------------
823
 
824
--dp_reg: process( clk, dp_ctrl, hold, out_alu, dp, data_in )
825
dp_reg: process( clk )
826
begin
827
  if clk'event and clk = '0' then
828 130 dilbert57
    if hold = '0' then
829 122 dilbert57
    case dp_ctrl is
830
         when reset_dp =>
831 130 dilbert57
           dp <= (others=>'0');
832 122 dilbert57
         when load_dp =>
833
           dp <= out_alu(7 downto 0);
834
         when pull_dp =>
835
      dp <= data_in;
836
         when others =>
837 130 dilbert57
      null;
838 122 dilbert57
    end case;
839
         end if;
840
  end if;
841
end process;
842
 
843
 
844
----------------------------------
845
--
846
-- op code register
847
--
848
----------------------------------
849
 
850
--op_reg: process( clk, op_ctrl, hold, op_code, data_in )
851
op_reg: process( clk )
852
begin
853
  if clk'event and clk = '0' then
854 130 dilbert57
    if hold = '0' then
855 122 dilbert57
    case op_ctrl is
856
         when reset_op =>
857
           op_code <= "00010010";
858
         when fetch_op =>
859
      op_code <= data_in;
860
         when others =>
861 130 dilbert57
      null;
862 122 dilbert57
    end case;
863
         end if;
864
  end if;
865
end process;
866
 
867
 
868
----------------------------------
869
--
870
-- pre byte op code register
871
--
872
----------------------------------
873
 
874
--pre_reg: process( clk, pre_ctrl, hold, pre_code, data_in )
875
pre_reg: process( clk )
876
begin
877
  if clk'event and clk = '0' then
878 130 dilbert57
    if hold = '0' then
879 122 dilbert57
    case pre_ctrl is
880
         when reset_pre =>
881 130 dilbert57
           pre_code <= (others=>'0');
882 122 dilbert57
         when fetch_pre =>
883
      pre_code <= data_in;
884
         when others =>
885 130 dilbert57
      null;
886 122 dilbert57
    end case;
887
         end if;
888
  end if;
889
end process;
890
 
891
--------------------------------
892
--
893
-- state machine
894
--
895
--------------------------------
896
 
897
--change_state: process( clk, rst, state, hold, next_state )
898
change_state: process( clk )
899
begin
900
  if clk'event and clk = '0' then
901
    if rst = '1' then
902 130 dilbert57
      fic     <= '0';
903
           nmi_ack <= '0';
904
           state   <= reset_state;
905
    elsif hold = '0' then
906
                  fic <= lic;
907
                  --
908
                  -- nmi request is not cleared until nmi input goes low
909
                  --
910
                  if (nmi_req = '0') and (nmi_ack='1') then
911
          nmi_ack <= '0';
912
                  end if;
913
 
914
                  if (nmi_req = '1') and (nmi_ack = '0')  and (state = int_nmimask_state) then
915
          nmi_ack <= '1';
916
                  end if;
917
 
918
        if lic = '1'  then
919
          if halt = '1' then
920
                           state <= halt_state;
921
 
922
          -- service non maskable interrupts
923
          elsif (nmi_req = '1') and (nmi_ack = '0') then
924
                           state <= int_nmi_state;
925
                                 --
926
                                 -- FIRQ & IRQ are level sensitive
927
                                 --
928
          elsif (firq = '1') and (cc(FBIT) = '0') then
929
                           state  <= int_firq_state;
930
 
931
                         elsif (irq = '1') and (cc(IBIT) = '0') then
932
                           state <= int_irq_state;
933
                         --
934
                         -- Version 1.27 2015-05-30
935
                         -- Exit sync_state on masked interrupt.
936
                         --
937
                         -- Version 1.28 2015-05-30
938
                         -- Move this code to the state sequencer
939
                         -- near line 5566.
940
                         --
941
                         -- elsif  (state = sync_state) and ((firq = '1') or (irq = '1'))then
942
                         --   state <= fetch_state;
943
          --
944
                         else
945
                           state <= next_state;
946
          end if; -- halt, nmi, firq, irq
947
                  else
948
                    state <= next_state;
949
        end if; -- lic
950
         end if; -- reset/hold
951
  end if; -- clk
952 122 dilbert57
end process;
953
 
954
------------------------------------
955
--
956
-- Detect Edge of NMI interrupt
957
--
958
------------------------------------
959
 
960
--nmi_handler : process( clk, rst, nmi, nmi_ack, nmi_req, nmi_enable )
961
nmi_handler : process( rst, clk )
962
begin
963
  if rst='1' then
964
         nmi_req <= '0';
965
  elsif clk'event and clk='0' then
966
           if (nmi='1') and (nmi_ack='0') and (nmi_enable='1') then
967
             nmi_req <= '1';
968
           else
969
                  if (nmi='0') and (nmi_ack='1') then
970
               nmi_req <= '0';
971
                  end if;
972
                end if;
973
  end if;
974
end process;
975
 
976
 
977
----------------------------------
978
--
979
-- Address output multiplexer
980
--
981
----------------------------------
982
 
983
addr_mux: process( addr_ctrl, pc, ea, up, sp, iv )
984
begin
985
  ifetch <= '0';
986
  vma    <= '1';
987
  case addr_ctrl is
988
    when fetch_ad =>
989
           addr   <= pc;
990 130 dilbert57
      rw     <= '1';
991 122 dilbert57
      ifetch <= '1';
992
         when read_ad =>
993 130 dilbert57
           addr   <= ea;
994
      rw     <= '1';
995 122 dilbert57
    when write_ad =>
996 130 dilbert57
           addr   <= ea;
997
                rw     <= '0';
998 122 dilbert57
         when pushs_ad =>
999 130 dilbert57
           addr   <= sp;
1000
                rw     <= '0';
1001 122 dilbert57
    when pulls_ad =>
1002 130 dilbert57
           addr   <= sp;
1003
      rw     <= '1';
1004 122 dilbert57
         when pushu_ad =>
1005 130 dilbert57
           addr   <= up;
1006
                rw     <= '0';
1007 122 dilbert57
    when pullu_ad =>
1008 130 dilbert57
           addr   <= up;
1009
      rw     <= '1';
1010 122 dilbert57
         when int_hi_ad =>
1011 130 dilbert57
           addr   <= "111111111111" & iv & "0";
1012
      rw     <= '1';
1013 122 dilbert57
    when int_lo_ad =>
1014 130 dilbert57
           addr   <= "111111111111" & iv & "1";
1015
      rw     <= '1';
1016 122 dilbert57
         when others =>
1017 130 dilbert57
      addr   <= "1111111111111111";
1018
      rw     <= '1';
1019
      vma    <= '0';
1020 122 dilbert57
  end case;
1021
end process;
1022
 
1023
--------------------------------
1024
--
1025
-- Data Bus output
1026
--
1027
--------------------------------
1028
dout_mux : process( dout_ctrl, md, acca, accb, dp, xreg, yreg, sp, up, pc, cc )
1029
begin
1030
    case dout_ctrl is
1031
         when cc_dout => -- condition code register
1032
           data_out <= cc;
1033
         when acca_dout => -- accumulator a
1034
           data_out <= acca;
1035
         when accb_dout => -- accumulator b
1036
           data_out <= accb;
1037
         when dp_dout => -- direct page register
1038
           data_out <= dp;
1039
         when ix_lo_dout => -- X index reg
1040
           data_out <= xreg(7 downto 0);
1041
         when ix_hi_dout => -- X index reg
1042
           data_out <= xreg(15 downto 8);
1043
         when iy_lo_dout => -- Y index reg
1044
           data_out <= yreg(7 downto 0);
1045
         when iy_hi_dout => -- Y index reg
1046
           data_out <= yreg(15 downto 8);
1047
         when up_lo_dout => -- U stack pointer
1048
           data_out <= up(7 downto 0);
1049
         when up_hi_dout => -- U stack pointer
1050
           data_out <= up(15 downto 8);
1051
         when sp_lo_dout => -- S stack pointer
1052
           data_out <= sp(7 downto 0);
1053
         when sp_hi_dout => -- S stack pointer
1054
           data_out <= sp(15 downto 8);
1055
         when md_lo_dout => -- alu output
1056
           data_out <= md(7 downto 0);
1057
         when md_hi_dout => -- alu output
1058
           data_out <= md(15 downto 8);
1059
         when pc_lo_dout => -- low order pc
1060
           data_out <= pc(7 downto 0);
1061
         when pc_hi_dout => -- high order pc
1062
           data_out <= pc(15 downto 8);
1063
    end case;
1064
end process;
1065
 
1066
----------------------------------
1067
--
1068
-- Left Mux
1069
--
1070
----------------------------------
1071
 
1072
left_mux: process( left_ctrl, acca, accb, cc, dp, xreg, yreg, up, sp, pc, ea, md )
1073
begin
1074
  case left_ctrl is
1075
         when cc_left =>
1076
           left(15 downto 8) <= "00000000";
1077
                left(7 downto 0)  <= cc;
1078
         when acca_left =>
1079
           left(15 downto 8) <= "00000000";
1080
                left(7 downto 0)  <= acca;
1081
         when accb_left =>
1082
           left(15 downto 8) <= "00000000";
1083
                left(7 downto 0)  <= accb;
1084
         when dp_left =>
1085
           left(15 downto 8) <= "00000000";
1086
                left(7 downto 0)  <= dp;
1087
         when accd_left =>
1088
           left(15 downto 8) <= acca;
1089
                left(7 downto 0)  <= accb;
1090
         when md_left =>
1091
           left <= md;
1092
         when ix_left =>
1093
           left <= xreg;
1094
         when iy_left =>
1095
           left <= yreg;
1096
         when sp_left =>
1097
           left <= sp;
1098
         when up_left =>
1099
           left <= up;
1100
         when pc_left =>
1101
           left <= pc;
1102
         when others =>
1103
--       when ea_left =>
1104
           left <= ea;
1105
    end case;
1106
end process;
1107
 
1108
----------------------------------
1109
--
1110
-- Right Mux
1111
--
1112
----------------------------------
1113
 
1114
right_mux: process( right_ctrl, md, acca, accb, ea )
1115
begin
1116
  case right_ctrl is
1117
         when ea_right =>
1118
           right <= ea;
1119
         when zero_right =>
1120
           right <= "0000000000000000";
1121
         when one_right =>
1122
           right <= "0000000000000001";
1123
         when two_right =>
1124
           right <= "0000000000000010";
1125
         when acca_right =>
1126
           if acca(7) = '0' then
1127
             right <= "00000000" & acca(7 downto 0);
1128
                else
1129
                  right <= "11111111" & acca(7 downto 0);
1130
                end if;
1131
         when accb_right =>
1132
           if accb(7) = '0' then
1133
             right <= "00000000" & accb(7 downto 0);
1134
                else
1135
                  right <= "11111111" & accb(7 downto 0);
1136
                end if;
1137
         when accd_right =>
1138
           right <= acca & accb;
1139
         when md_sign5_right =>
1140
           if md(4) = '0' then
1141
             right <= "00000000000" & md(4 downto 0);
1142
                else
1143
                  right <= "11111111111" & md(4 downto 0);
1144
                end if;
1145
         when md_sign8_right =>
1146
           if md(7) = '0' then
1147
             right <= "00000000" & md(7 downto 0);
1148
                else
1149
                  right <= "11111111" & md(7 downto 0);
1150
                end if;
1151
         when others =>
1152
--       when md_right =>
1153
           right <= md;
1154
    end case;
1155
end process;
1156
 
1157
----------------------------------
1158
--
1159
-- Arithmetic Logic Unit
1160
--
1161
----------------------------------
1162
 
1163
alu: process( alu_ctrl, cc, left, right, out_alu, cc_out )
1164
variable valid_lo, valid_hi : boolean;
1165
variable carry_in : std_logic;
1166
variable daa_reg : std_logic_vector(7 downto 0);
1167
begin
1168
 
1169
  case alu_ctrl is
1170
         when alu_adc | alu_sbc |
1171
              alu_rol8 | alu_ror8 =>
1172
           carry_in := cc(CBIT);
1173
    when alu_asr8 =>
1174
           carry_in := left(7);
1175
         when others =>
1176
           carry_in := '0';
1177
  end case;
1178
 
1179
  valid_lo := left(3 downto 0) <= 9;
1180
  valid_hi := left(7 downto 4) <= 9;
1181
 
1182 130 dilbert57
  --
1183
  -- CBIT HBIT VHI VLO DAA
1184
  --    0    0   0   0 66 (!VHI : hi_nybble>8)
1185
  --    0    0   0   1 60
1186
  --    0    0   1   1 00
1187
  --    0    0   1   0 06 ( VHI : hi_nybble<=8)
1188
  --
1189
  --    0    1   1   0 06
1190
  --    0    1   1   1 06
1191
  --    0    1   0   1 66
1192
  --    0    1   0   0 66
1193
  --
1194
  --    1    1   0   0 66
1195
  --    1    1   0   1 66
1196
  --    1    1   1   1 66
1197
  --    1    1   1   0 66
1198
  --
1199
  --    1    0   1   0 66
1200
  --    1    0   1   1 60
1201
  --    1    0   0   1 60
1202
  --    1    0   0   0 66
1203
  --
1204
  -- 66 = (!VHI & !VLO) + (CBIT & HBIT) + (HBIT & !VHI) + (CBIT & !VLO) 
1205
  --    = (CBIT & (HBIT + !VLO)) + (!VHI & (HBIT + !VLO))
1206
  --    = (!VLO & (CBIT + !VHI)) + (HBIT & (CBIT + !VHI))
1207
  -- 60 = (CBIT & !HBIT & VLO) + (!HBIT & !VHI & VLO) 
1208
  --    = (!HBIT & VLO & (CBIT + !VHI))
1209
  -- 06 = (!CBIT & VHI & (!VLO + VHI)
1210
  -- 00 = (!CBIT & !HBIT & VHI & VLO)
1211
  --
1212 122 dilbert57
  if (cc(CBIT) = '0') then
1213 130 dilbert57
    -- CBIT=0
1214
    if( cc(HBIT) = '0' ) then
1215
           -- HBIT=0
1216 122 dilbert57
                if valid_lo then
1217 130 dilbert57
                  -- lo <= 9 (no overflow in low nybble)
1218 122 dilbert57
                  if valid_hi then
1219 130 dilbert57
                    -- hi <= 9 (no overflow in either low or high nybble)
1220 122 dilbert57
                    daa_reg := "00000000";
1221
                  else
1222 130 dilbert57
                    -- hi > 9 (overflow in high nybble only)
1223 122 dilbert57
                    daa_reg := "01100000";
1224
                  end if;
1225
                else
1226 130 dilbert57
                  -- lo > 9 (overflow in low nybble)
1227
                  --
1228
                  -- since there is already an overflow in the low nybble
1229
                  -- you need to make room in the high nybble for the low nybble carry
1230
                  -- so compare the high nybble with 8 rather than 9
1231
                  -- if the high nybble is 9 there will be an overflow on the high nybble
1232
                  -- after the decimal adjust which means it will roll over to an invalid BCD digit
1233
                  --
1234 122 dilbert57
             if( left(7 downto 4) <= 8 ) then
1235 130 dilbert57
                    -- hi <= 8 (overflow in low nybble only)
1236 122 dilbert57
                    daa_reg := "00000110";
1237
                  else
1238 130 dilbert57
                    -- hi > 8 (overflow in low and high nybble)
1239 122 dilbert57
                         daa_reg := "01100110";
1240
                  end if;
1241
                end if;
1242 130 dilbert57
    else
1243
           -- HBIT=1 (overflow in low nybble)
1244
                if valid_hi then
1245
                  -- hi <= 9 (overflow in low nybble only)
1246
                  daa_reg := "00000110";
1247
                else
1248
                  -- hi > 9 (overflow in low and high nybble)
1249
                  daa_reg := "01100110";
1250
           end if;
1251 122 dilbert57
         end if;
1252
  else
1253 130 dilbert57
    -- CBIT=1 (carry => overflow in high nybble)
1254
    if ( cc(HBIT) = '0' )then
1255
           -- HBIT=0 (half carry clear => may or may not be an overflow in the low nybble)
1256 122 dilbert57
                if valid_lo then
1257 130 dilbert57
                  -- lo <=9  (overflow in high nybble only)
1258 122 dilbert57
                  daa_reg := "01100000";
1259
           else
1260 130 dilbert57
                  -- lo >9  (overflow in low and high nybble)
1261 122 dilbert57
                  daa_reg := "01100110";
1262
                end if;
1263 130 dilbert57
         else
1264
           -- HBIT=1 (overflow in low and high nybble)
1265
                daa_reg := "01100110";
1266 122 dilbert57
         end if;
1267
  end if;
1268
 
1269
  case alu_ctrl is
1270
         when alu_add8 | alu_inc |
1271
              alu_add16 | alu_adc | alu_mul =>
1272
                out_alu <= left + right + ("000000000000000" & carry_in);
1273
         when alu_sub8 | alu_dec |
1274
              alu_sub16 | alu_sbc =>
1275
           out_alu <= left - right - ("000000000000000" & carry_in);
1276
    when alu_abx =>
1277
           out_alu <= left + ("00000000" & right(7 downto 0)) ;
1278
         when alu_and =>
1279
           out_alu   <= left and right;         -- and/bit
1280
         when alu_ora =>
1281
           out_alu   <= left or right;  -- or
1282
         when alu_eor =>
1283
           out_alu   <= left xor right;         -- eor/xor
1284
         when alu_lsl16 | alu_asl8 | alu_rol8 =>
1285
           out_alu   <= left(14 downto 0) & carry_in;    -- rol8/asl8/lsl16
1286
         when alu_lsr16 =>
1287
           out_alu   <= carry_in & left(15 downto 1);   -- lsr16
1288
         when alu_lsr8 | alu_asr8 | alu_ror8 =>
1289
           out_alu   <= "00000000" & carry_in & left(7 downto 1);       -- ror8/asr8/lsr8
1290
         when alu_neg =>
1291
           out_alu   <= right - left;   -- neg (right=0)
1292
         when alu_com =>
1293
           out_alu   <= not left;
1294
         when alu_clr | alu_ld8 | alu_ld16 | alu_lea =>
1295
           out_alu   <= right;           -- clr, ld
1296
         when alu_st8 | alu_st16 | alu_andcc | alu_orcc | alu_tfr =>
1297
           out_alu   <= left;
1298
         when alu_daa =>
1299
           out_alu   <= left + ("00000000" & daa_reg);
1300
         when alu_sex =>
1301
           if left(7) = '0' then
1302
              out_alu <= "00000000" & left(7 downto 0);
1303
                else
1304
                   out_alu <= "11111111" & left(7 downto 0);
1305
                end if;
1306
         when others =>
1307
           out_alu   <= left; -- nop
1308
    end case;
1309
 
1310
         --
1311
         -- carry bit
1312
         --
1313
    case alu_ctrl is
1314
         when alu_add8 | alu_adc  =>
1315
      cc_out(CBIT) <= (left(7) and right(7)) or
1316
                                (left(7) and not out_alu(7)) or
1317
                                                   (right(7) and not out_alu(7));
1318
         when alu_sub8 | alu_sbc =>
1319
      cc_out(CBIT) <= ((not left(7)) and right(7)) or
1320
                                ((not left(7)) and out_alu(7)) or
1321
                                                         (right(7) and out_alu(7));
1322
         when alu_add16  =>
1323
      cc_out(CBIT) <= (left(15) and right(15)) or
1324
                                (left(15) and not out_alu(15)) or
1325
                                                   (right(15) and not out_alu(15));
1326
         when alu_sub16 =>
1327
      cc_out(CBIT) <= ((not left(15)) and right(15)) or
1328
                                ((not left(15)) and out_alu(15)) or
1329
                                                         (right(15) and out_alu(15));
1330
         when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 =>
1331
           cc_out(CBIT) <= left(0);
1332
         when alu_rol8 | alu_asl8 =>
1333
           cc_out(CBIT) <= left(7);
1334
         when alu_lsl16 =>
1335
           cc_out(CBIT) <= left(15);
1336
         when alu_com =>
1337
           cc_out(CBIT) <= '1';
1338
         when alu_neg | alu_clr =>
1339
           cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
1340
                                out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0);
1341
    when alu_mul =>
1342
                cc_out(CBIT) <= out_alu(7);
1343
    when alu_daa =>
1344
           if ( daa_reg(7 downto 4) = "0110" ) then
1345
                  cc_out(CBIT) <= '1';
1346
                else
1347
                  cc_out(CBIT) <= '0';
1348
           end if;
1349
         when alu_andcc =>
1350
      cc_out(CBIT) <= left(CBIT) and cc(CBIT);
1351
         when alu_orcc =>
1352
      cc_out(CBIT) <= left(CBIT) or cc(CBIT);
1353
         when alu_tfr =>
1354
      cc_out(CBIT) <= left(CBIT);
1355
         when others =>
1356
      cc_out(CBIT) <= cc(CBIT);
1357
    end case;
1358
         --
1359
         -- Zero flag
1360
         --
1361
    case alu_ctrl is
1362
         when alu_add8 | alu_sub8 |
1363
              alu_adc | alu_sbc |
1364
              alu_and | alu_ora | alu_eor |
1365
              alu_inc | alu_dec |
1366
                        alu_neg | alu_com | alu_clr |
1367
                        alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
1368
                   alu_ld8  | alu_st8 | alu_sex | alu_daa =>
1369
      cc_out(ZBIT) <= not( out_alu(7)  or out_alu(6)  or out_alu(5)  or out_alu(4)  or
1370
                                out_alu(3)  or out_alu(2)  or out_alu(1)  or out_alu(0) );
1371
         when alu_add16 | alu_sub16 | alu_mul |
1372
              alu_lsl16 | alu_lsr16 |
1373
                   alu_ld16  | alu_st16 | alu_lea =>
1374
      cc_out(ZBIT) <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or
1375
                                out_alu(11) or out_alu(10) or out_alu(9)  or out_alu(8)  or
1376
                                out_alu(7)  or out_alu(6)  or out_alu(5)  or out_alu(4)  or
1377
                                out_alu(3)  or out_alu(2)  or out_alu(1)  or out_alu(0) );
1378
         when alu_andcc =>
1379
      cc_out(ZBIT) <= left(ZBIT) and cc(ZBIT);
1380
         when alu_orcc =>
1381
      cc_out(ZBIT) <= left(ZBIT) or cc(ZBIT);
1382
         when alu_tfr =>
1383
      cc_out(ZBIT) <= left(ZBIT);
1384
         when others =>
1385
      cc_out(ZBIT) <= cc(ZBIT);
1386
    end case;
1387
 
1388
    --
1389
         -- negative flag
1390
         --
1391
    case alu_ctrl is
1392
         when alu_add8 | alu_sub8 |
1393
              alu_adc | alu_sbc |
1394
              alu_and | alu_ora | alu_eor |
1395
              alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
1396
              alu_inc | alu_dec | alu_neg | alu_com | alu_clr |
1397
                        alu_ld8  | alu_st8 | alu_sex | alu_daa =>
1398
      cc_out(NBIT) <= out_alu(7);
1399
         when alu_add16 | alu_sub16 |
1400
              alu_lsl16 | alu_lsr16 |
1401
                        alu_ld16 | alu_st16 =>
1402
                cc_out(NBIT) <= out_alu(15);
1403
         when alu_andcc =>
1404
      cc_out(NBIT) <= left(NBIT) and cc(NBIT);
1405
         when alu_orcc =>
1406
      cc_out(NBIT) <= left(NBIT) or cc(NBIT);
1407
         when alu_tfr =>
1408
      cc_out(NBIT) <= left(NBIT);
1409
         when others =>
1410
      cc_out(NBIT) <= cc(NBIT);
1411
    end case;
1412
 
1413
    --
1414
         -- Interrupt mask flag
1415
    --
1416
    case alu_ctrl is
1417
         when alu_andcc =>
1418
      cc_out(IBIT) <= left(IBIT) and cc(IBIT);
1419
         when alu_orcc =>
1420
      cc_out(IBIT) <= left(IBIT) or cc(IBIT);
1421
         when alu_tfr =>
1422
      cc_out(IBIT) <= left(IBIT);
1423
    when alu_seif | alu_sei =>
1424
           cc_out(IBIT) <= '1';
1425
         when others =>
1426
                cc_out(IBIT) <= cc(IBIT);             -- interrupt mask
1427
    end case;
1428
 
1429
    --
1430
    -- Half Carry flag
1431
         --
1432
    case alu_ctrl is
1433
         when alu_add8 | alu_adc =>
1434
      cc_out(HBIT) <= (left(3) and right(3)) or
1435
                     (right(3) and not out_alu(3)) or
1436
                      (left(3) and not out_alu(3));
1437
         when alu_andcc =>
1438
      cc_out(HBIT) <= left(HBIT) and cc(HBIT);
1439
         when alu_orcc =>
1440
      cc_out(HBIT) <= left(HBIT) or cc(HBIT);
1441
         when alu_tfr =>
1442
      cc_out(HBIT) <= left(HBIT);
1443
         when others =>
1444
                cc_out(HBIT) <= cc(HBIT);
1445
    end case;
1446
 
1447
    --
1448
    -- Overflow flag
1449
         --
1450
    case alu_ctrl is
1451
         when alu_add8 | alu_adc =>
1452
      cc_out(VBIT) <= (left(7)  and      right(7)  and (not out_alu(7))) or
1453
                 ((not left(7)) and (not right(7)) and      out_alu(7));
1454
         when alu_sub8 | alu_sbc =>
1455
      cc_out(VBIT) <= (left(7)  and (not right(7)) and (not out_alu(7))) or
1456
                 ((not left(7)) and      right(7)  and      out_alu(7));
1457
         when alu_add16 =>
1458
      cc_out(VBIT) <= (left(15)  and      right(15)  and (not out_alu(15))) or
1459
                 ((not left(15)) and (not right(15)) and      out_alu(15));
1460
         when alu_sub16 =>
1461
      cc_out(VBIT) <= (left(15)  and (not right(15)) and (not out_alu(15))) or
1462
                 ((not left(15)) and      right(15) and       out_alu(15));
1463
         when alu_inc =>
1464
           cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and
1465
                                      left(3)  and left(2) and left(1) and left(0));
1466
         when alu_dec | alu_neg =>
1467
           cc_out(VBIT) <= (left(7)  and (not left(6)) and (not left(5)) and (not left(4)) and
1468
                            (not left(3)) and (not left(2)) and (not left(1)) and (not left(0)));
1469
-- 6809 Programming reference manual says
1470
-- V not affected by ASR, LSR and ROR
1471
-- This is different to the 6800
1472
-- John Kent 6th June 2006
1473
--       when alu_asr8 =>
1474
--         cc_out(VBIT) <= left(0) xor left(7);
1475
--       when alu_lsr8 | alu_lsr16 =>
1476
--         cc_out(VBIT) <= left(0);
1477
--       when alu_ror8 =>
1478
--      cc_out(VBIT) <= left(0) xor cc(CBIT);
1479
    when alu_lsl16 =>
1480
      cc_out(VBIT) <= left(15) xor left(14);
1481
         when alu_rol8 | alu_asl8 =>
1482
      cc_out(VBIT) <= left(7) xor left(6);
1483
--
1484
-- 11th July 2006 - John Kent
1485
-- What DAA does with V is anyones guess
1486
-- It is undefined in the 6809 programming manual
1487
--
1488
         when alu_daa =>
1489
      cc_out(VBIT) <= left(7) xor out_alu(7) xor cc(CBIT);
1490
-- CLR resets V Bit
1491
-- John Kent 6th June 2006
1492
         when alu_and | alu_ora | alu_eor | alu_com | alu_clr |
1493
              alu_st8 | alu_st16 | alu_ld8 | alu_ld16 | alu_sex =>
1494
      cc_out(VBIT) <= '0';
1495
         when alu_andcc =>
1496
      cc_out(VBIT) <= left(VBIT) and cc(VBIT);
1497
         when alu_orcc =>
1498
      cc_out(VBIT) <= left(VBIT) or cc(VBIT);
1499
         when alu_tfr =>
1500
      cc_out(VBIT) <= left(VBIT);
1501
         when others =>
1502
                cc_out(VBIT) <= cc(VBIT);
1503
    end case;
1504
 
1505
         case alu_ctrl is
1506
         when alu_andcc =>
1507
      cc_out(FBIT) <= left(FBIT) and cc(FBIT);
1508
         when alu_orcc =>
1509
      cc_out(FBIT) <= left(FBIT) or cc(FBIT);
1510
         when alu_tfr =>
1511
      cc_out(FBIT) <= left(FBIT);
1512
    when alu_seif =>
1513
           cc_out(FBIT) <= '1';
1514
         when others =>
1515
      cc_out(FBIT) <= cc(FBIT);
1516
         end case;
1517
 
1518
         case alu_ctrl is
1519
         when alu_andcc =>
1520
      cc_out(EBIT) <= left(EBIT) and cc(EBIT);
1521
         when alu_orcc =>
1522
      cc_out(EBIT) <= left(EBIT) or cc(EBIT);
1523
         when alu_tfr =>
1524
      cc_out(EBIT) <= left(EBIT);
1525
    when alu_see =>
1526
           cc_out(EBIT) <= '1';
1527
    when alu_cle =>
1528
           cc_out(EBIT) <= '0';
1529
         when others =>
1530
           cc_out(EBIT) <= cc(EBIT);
1531
         end case;
1532
end process;
1533
 
1534
------------------------------------
1535
--
1536
-- state sequencer
1537
--
1538
------------------------------------
1539
process( state, saved_state,
1540
         op_code, pre_code,
1541 130 dilbert57
                        cc, ea, md, iv, fic, halt,
1542
         nmi_req, firq, irq, lic )
1543 122 dilbert57
variable cond_true : boolean;  -- variable used to evaluate coditional branches
1544
begin
1545 130 dilbert57
  cond_true  := (1=1);
1546
  ba         <= '0';
1547
  bs         <= '0';
1548
  lic        <= '0';
1549
  opfetch    <= '0';
1550
  iv_ctrl    <= latch_iv;
1551
  -- Registers preserved
1552
  cc_ctrl    <= latch_cc;
1553
  acca_ctrl  <= latch_acca;
1554
  accb_ctrl  <= latch_accb;
1555
  dp_ctrl    <= latch_dp;
1556
  ix_ctrl    <= latch_ix;
1557
  iy_ctrl    <= latch_iy;
1558
  up_ctrl    <= latch_up;
1559
  sp_ctrl    <= latch_sp;
1560
  pc_ctrl    <= latch_pc;
1561
  md_ctrl    <= latch_md;
1562
  ea_ctrl    <= latch_ea;
1563
  op_ctrl    <= latch_op;
1564
  pre_ctrl   <= latch_pre;
1565
  -- ALU Idle
1566
  left_ctrl  <= pc_left;
1567
  right_ctrl <= zero_right;
1568
  alu_ctrl   <= alu_nop;
1569
  -- Bus idle
1570
  addr_ctrl  <= idle_ad;
1571
  dout_ctrl  <= cc_dout;
1572
  -- Next State Fetch
1573
  st_ctrl      <= idle_st;
1574
  return_state <= fetch_state;
1575
  next_state   <= fetch_state;
1576
 
1577
  case state is
1578
  when reset_state =>        --  released from reset
1579
    -- reset the registers
1580
    iv_ctrl    <= reset_iv;
1581
    op_ctrl    <= reset_op;
1582
    pre_ctrl   <= reset_pre;
1583
    cc_ctrl    <= reset_cc;
1584
    acca_ctrl  <= reset_acca;
1585
    accb_ctrl  <= reset_accb;
1586
    dp_ctrl    <= reset_dp;
1587
    ix_ctrl    <= reset_ix;
1588
    iy_ctrl    <= reset_iy;
1589
    up_ctrl    <= reset_up;
1590
    sp_ctrl    <= reset_sp;
1591
    pc_ctrl    <= reset_pc;
1592
    ea_ctrl    <= reset_ea;
1593
    md_ctrl    <= reset_md;
1594
    st_ctrl    <= reset_st;
1595
    next_state <= vect_hi_state;
1596
 
1597
  --
1598
  -- Jump via interrupt vector
1599
  -- iv holds interrupt type
1600
  -- fetch PC hi from vector location
1601
  --
1602
  when vect_hi_state =>
1603
    -- fetch pc low interrupt vector
1604
    pc_ctrl    <= pull_hi_pc;
1605
    addr_ctrl  <= int_hi_ad;
1606
    bs         <= '1';
1607
    next_state <= vect_lo_state;
1608
 
1609
  --
1610
  -- jump via interrupt vector
1611
  -- iv holds vector type
1612
  -- fetch PC lo from vector location
1613
  --
1614
  when vect_lo_state =>
1615
    -- fetch the vector low byte
1616
    pc_ctrl    <= pull_lo_pc;
1617
    addr_ctrl  <= int_lo_ad;
1618
    bs         <= '1';
1619
    next_state <= fetch_state;
1620
 
1621
  when vect_idle_state =>
1622
    --
1623
    -- Last Instruction Cycle for SWI, SWI2 & SWI3
1624
    --
1625
    if op_code = "00111111" then
1626
      lic      <= '1';
1627
    end if;
1628
    next_state <= fetch_state;
1629
 
1630
  --
1631
  -- Here to fetch an instruction
1632
  -- PC points to opcode
1633
  --
1634
  when fetch_state =>
1635
    -- fetch the op code
1636
    opfetch    <= '1';
1637
    op_ctrl    <= fetch_op;
1638
    pre_ctrl   <= fetch_pre;
1639
    ea_ctrl    <= reset_ea;
1640
    -- Fetch op code
1641
    addr_ctrl  <= fetch_ad;
1642
    -- Advance the PC to fetch next instruction byte
1643
    pc_ctrl    <= incr_pc;
1644
    next_state <= decode1_state;
1645
 
1646
  --
1647
  -- Here to decode instruction
1648
  -- and fetch next byte of intruction
1649
  -- whether it be necessary or not
1650
  --
1651
  when decode1_state =>
1652
        -- fetch first byte of address or immediate data
1653
    ea_ctrl    <= fetch_first_ea;
1654
    md_ctrl    <= fetch_first_md;
1655
    addr_ctrl  <= fetch_ad;
1656
    case op_code(7 downto 4) is
1657
    --
1658
    -- direct single op (2 bytes)
1659
    -- 6809 => 6 cycles
1660
    -- cpu09 => 5 cycles
1661
    -- 1 op=(pc) / pc=pc+1
1662
    -- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
1663
    -- 3 md_lo=(ea) / pc=pc
1664
    -- 4 alu_left=md / md=alu_out / pc=pc
1665
    -- 5 (ea)=md_lo / pc=pc
1666
    --
1667
    -- Exception is JMP
1668
    -- 6809 => 3 cycles
1669
    -- cpu09 => 3 cycles
1670
    -- 1 op=(pc) / pc=pc+1
1671
    -- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
1672
    -- 3 pc=ea
1673
               --
1674
        when "0000" =>
1675
      -- advance the PC
1676
      pc_ctrl    <= incr_pc;
1677
 
1678
      case op_code(3 downto 0) is
1679
      when "1110" => -- jmp
1680
        next_state <= jmp_state;
1681
 
1682
      when "1111" => -- clr
1683
        next_state <= single_op_exec_state;
1684
 
1685
      when others =>
1686
        next_state <= single_op_read_state;
1687
 
1688
      end case;
1689
 
1690
    -- acca / accb inherent instructions
1691
        when "0001" =>
1692
      case op_code(3 downto 0) is
1693
      --
1694
      -- Page2 pre byte
1695
      -- pre=(pc) / pc=pc+1
1696
      -- op=(pc) / pc=pc+1
1697
      --
1698
      when "0000" => -- page2
1699
        opfetch    <= '1';
1700
        op_ctrl    <= fetch_op;
1701
        -- advance pc
1702
        pc_ctrl    <= incr_pc;
1703
        next_state <= decode2_state;
1704
 
1705
      --
1706
      -- Page3 pre byte
1707
      -- pre=(pc) / pc=pc+1
1708
      -- op=(pc) / pc=pc+1
1709
      --
1710
      when "0001" => -- page3
1711
        opfetch    <= '1';
1712
        op_ctrl    <= fetch_op;
1713
        -- advance pc
1714
        pc_ctrl    <= incr_pc;
1715
        next_state <= decode3_state;
1716
 
1717
      --
1718
      -- nop - No operation ( 1 byte )
1719
      -- 6809 => 2 cycles
1720
      -- cpu09 => 2 cycles
1721
      -- 1 op=(pc) / pc=pc+1
1722
      -- 2 decode
1723
      -- 
1724
      when "0010" => -- nop
1725
        lic          <= '1';
1726
        next_state   <= fetch_state;
1727
 
1728
      --
1729
      -- sync - halt execution until an interrupt is received
1730
      -- interrupt may be NMI, IRQ or FIRQ
1731
      -- program execution continues if the 
1732
      -- interrupt is asserted for 3 clock cycles
1733
      -- note that registers are not pushed onto the stack
1734
      -- CPU09 => Interrupts need only be asserted for one clock cycle
1735
      --
1736
      when "0011" => -- sync
1737
        next_state   <= sync_state;
1738
 
1739
      --
1740
      -- lbra -- long branch (3 bytes)
1741
      -- 6809 => 5 cycles
1742
      -- cpu09 => 4 cycles
1743
      -- 1 op=(pc) / pc=pc+1
1744
      -- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
1745
      -- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
1746
      -- 4 pc=pc+md
1747
      --
1748
      when "0110" =>
1749
        -- increment the pc
1750
        pc_ctrl    <= incr_pc;
1751
        next_state <= lbranch_state;
1752
 
1753
      --
1754
      -- lbsr - long branch to subroutine (3 bytes)
1755
      -- 6809 => 9 cycles
1756
      -- cpu09 => 6 cycles
1757
      -- 1 op=(pc) /pc=pc+1
1758
      -- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / sp=sp-1
1759
      -- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
1760
      -- 4 (sp)= pc_lo / sp=sp-1 / pc=pc
1761
      -- 5 (sp)=pc_hi / pc=pc
1762
      -- 6 pc=pc+md
1763
      --
1764
      when "0111" =>
1765
        -- pre decrement sp
1766
        left_ctrl  <= sp_left;
1767
        right_ctrl <= one_right;
1768
        alu_ctrl   <= alu_sub16;
1769
        sp_ctrl    <= load_sp;
1770
        -- increment the pc
1771
        pc_ctrl    <= incr_pc;
1772
        next_state <= lbranch_state;
1773
 
1774
      --
1775
      -- Decimal Adjust Accumulator
1776
      --
1777
      when "1001" => -- daa
1778
        left_ctrl  <= acca_left;
1779
        right_ctrl <= accb_right;
1780
        alu_ctrl   <= alu_daa;
1781
        cc_ctrl    <= load_cc;
1782
        acca_ctrl  <= load_acca;
1783
        lic        <= '1';
1784
        next_state <= fetch_state;
1785
 
1786
      --
1787
      -- OR Condition Codes
1788
      --
1789
      when "1010" => -- orcc
1790
        -- increment the pc
1791
        pc_ctrl      <= incr_pc;
1792
        next_state   <= orcc_state;
1793
 
1794
      --
1795
      -- AND Condition Codes
1796
      --
1797
      when "1100" => -- andcc
1798
        -- increment the pc
1799
        pc_ctrl      <= incr_pc;
1800
        next_state   <= andcc_state;
1801
 
1802
      --
1803
      -- Sign Extend
1804
      --
1805
      when "1101" => -- sex
1806
        left_ctrl  <= accb_left;
1807
        right_ctrl <= zero_right;
1808
        alu_ctrl   <= alu_sex;
1809
        cc_ctrl    <= load_cc;
1810
        acca_ctrl  <= load_hi_acca;
1811
        lic        <= '1';
1812
        next_state <= fetch_state;
1813
 
1814
      --
1815
      -- Exchange Registers
1816
      --
1817
      when "1110" => -- exg
1818
        -- increment the pc
1819
        pc_ctrl    <= incr_pc;
1820
        next_state <= exg_state;
1821
 
1822
      --
1823
      -- Transfer Registers
1824
      --
1825
      when "1111" => -- tfr
1826
        -- increment the pc
1827
        pc_ctrl      <= incr_pc;
1828
        next_state   <= tfr_state;
1829
 
1830
      when others =>
1831
        -- increment the pc
1832
        pc_ctrl    <= incr_pc;
1833
        lic        <= '1';
1834
        next_state <= fetch_state;
1835
      end case;
1836
 
1837
    --
1838
    -- Short branch conditional
1839
    -- 6809 => always 3 cycles
1840
    -- cpu09 => always = 3 cycles
1841
    -- 1 op=(pc) / pc=pc+1
1842
    -- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / test cc
1843
    -- 3 if cc tru pc=pc+md else pc=pc
1844
    --
1845
    when "0010" => -- branch conditional
1846
      -- increment the pc
1847
      pc_ctrl    <= incr_pc;
1848
      next_state <= sbranch_state;
1849
 
1850
    --
1851
    -- Single byte stack operators
1852
    -- Do not advance PC
1853
    --
1854
    when "0011" =>
1855
      --
1856
      -- lea - load effective address (2+ bytes)
1857
      -- 6809 => 4 cycles + addressing mode
1858
      -- cpu09 => 4 cycles + addressing mode
1859
      -- 1 op=(pc) / pc=pc+1
1860
      -- 2 md_lo=(pc) / pc=pc+1
1861
      -- 3 calculate ea
1862
      -- 4 ix/iy/sp/up = ea
1863
      --
1864
      case op_code(3 downto 0) is
1865
           when "0000" |  -- leax
1866
           "0001" |  -- leay
1867
           "0010" |  -- leas
1868
           "0011" => -- leau
1869
        -- advance PC
1870
        pc_ctrl      <= incr_pc;
1871
        st_ctrl      <= push_st;
1872
        return_state <= lea_state;
1873
        next_state   <= indexed_state;
1874
 
1875
      --
1876
      -- pshs - push registers onto sp stack
1877
      -- 6809 => 5 cycles + registers
1878
      -- cpu09 => 3 cycles + registers
1879
      --  1 op=(pc) / pc=pc+1
1880
      --  2 ea_lo=(pc) / pc=pc+1 
1881
      --  3 if ea(7 downto 0) != "00000000" then sp=sp-1
1882
      --  4 if ea(7) = 1 (sp)=pcl, sp=sp-1
1883
      --  5 if ea(7) = 1 (sp)=pch
1884
      --    if ea(6 downto 0) != "0000000" then sp=sp-1
1885
      --  6 if ea(6) = 1 (sp)=upl, sp=sp-1
1886
      --  7 if ea(6) = 1 (sp)=uph
1887
      --    if ea(5 downto 0) != "000000" then sp=sp-1
1888
      --  8 if ea(5) = 1 (sp)=iyl, sp=sp-1
1889
      --  9 if ea(5) = 1 (sp)=iyh
1890
      --    if ea(4 downto 0) != "00000" then sp=sp-1
1891
      -- 10 if ea(4) = 1 (sp)=ixl, sp=sp-1
1892
      -- 11 if ea(4) = 1 (sp)=ixh
1893
      --    if ea(3 downto 0) != "0000" then sp=sp-1
1894
      -- 12 if ea(3) = 1 (sp)=dp
1895
      --    if ea(2 downto 0) != "000" then sp=sp-1
1896
      -- 13 if ea(2) = 1 (sp)=accb
1897
      --    if ea(1 downto 0) != "00" then sp=sp-1
1898
      -- 14 if ea(1) = 1 (sp)=acca
1899
      --    if ea(0 downto 0) != "0" then sp=sp-1
1900
      -- 15 if ea(0) = 1 (sp)=cc
1901
      --
1902
      when "0100" => -- pshs
1903
        -- advance PC
1904
        pc_ctrl    <= incr_pc;
1905
        next_state <= pshs_state;
1906
 
1907
      --
1908
      -- puls - pull registers of sp stack
1909
      -- 6809 => 5 cycles + registers
1910
      -- cpu09 => 3 cycles + registers
1911
      --
1912
      when "0101" => -- puls
1913
        -- advance PC
1914
        pc_ctrl    <= incr_pc;
1915
        next_state <= puls_state;
1916
 
1917
      --
1918
      -- pshu - push registers onto up stack
1919
      -- 6809 => 5 cycles + registers
1920
      -- cpu09 => 3 cycles + registers
1921
      --
1922
      when "0110" => -- pshu
1923
        -- advance PC
1924
        pc_ctrl    <= incr_pc;
1925
        next_state <= pshu_state;
1926
 
1927
      --
1928
      -- pulu - pull registers of up stack
1929
      -- 6809 => 5 cycles + registers
1930
      -- cpu09 => 3 cycles + registers
1931
      --
1932
      when "0111" => -- pulu
1933
        -- advance PC
1934
        pc_ctrl    <= incr_pc;
1935
        next_state <= pulu_state;
1936
 
1937
      --
1938
      -- rts - return from subroutine
1939
      -- 6809 => 5 cycles
1940
      -- cpu09 => 4 cycles 
1941
      -- 1 op=(pc) / pc=pc+1
1942
      -- 2 decode op
1943
      -- 3 pc_hi = (sp) / sp=sp+1
1944
      -- 4 pc_lo = (sp) / sp=sp+1
1945
      --
1946
      when "1001" =>
1947
                  next_state   <= pull_return_hi_state;
1948
 
1949
      --
1950
      -- ADD accb to index register
1951
      -- *** Note: this is an unsigned addition.
1952
      --           does not affect any condition codes
1953
      -- 6809 => 3 cycles
1954
      -- cpu09 => 2 cycles
1955
      -- 1 op=(pc) / pc=pc+1
1956
      -- 2 alu_left=ix / alu_right=accb / ix=alu_out / pc=pc
1957
      --
1958
      when "1010" => -- abx
1959
        lic          <= '1';
1960
        left_ctrl    <= ix_left;
1961
        right_ctrl   <= accb_right;
1962
        alu_ctrl     <= alu_abx;
1963
        ix_ctrl      <= load_ix;
1964
        next_state   <= fetch_state;
1965
 
1966
      --
1967
      -- Return From Interrupt
1968
      --
1969
      when "1011" => -- rti
1970
        next_state   <= rti_cc_state;
1971
 
1972
      --
1973
      -- CWAI
1974
      --
1975
      when "1100" => -- cwai #$<cc_mask>
1976
        -- pre decrement sp
1977
        left_ctrl    <= sp_left;
1978
        right_ctrl   <= one_right;
1979
        alu_ctrl     <= alu_sub16;
1980
        sp_ctrl      <= load_sp;
1981
        -- increment pc
1982
        pc_ctrl      <= incr_pc;
1983
        next_state   <= cwai_state;
1984
 
1985
      --
1986
      -- MUL Multiply
1987
      --
1988
      when "1101" => -- mul
1989
        next_state   <= mul_state;
1990
 
1991
      --
1992
      -- SWI Software Interrupt
1993
      --
1994
      when "1111" => -- swi
1995
        -- predecrement SP
1996
        left_ctrl    <= sp_left;
1997
        right_ctrl   <= one_right;
1998
        alu_ctrl     <= alu_sub16;
1999
        sp_ctrl      <= load_sp;
2000
        iv_ctrl      <= swi_iv;
2001
        st_ctrl      <= push_st;
2002
        return_state <= int_swimask_state;
2003
        next_state   <= int_entire_state;
2004
 
2005
      when others =>
2006
        lic          <= '1';
2007
        next_state   <= fetch_state;
2008
 
2009
      end case;
2010
                                 --
2011
    -- Accumulator A Single operand
2012
    -- source = acca, dest = acca
2013
    -- Do not advance PC
2014
    -- Typically 2 cycles 1 bytes
2015
    -- 1 opcode fetch
2016
    -- 2 post byte fetch / instruction decode
2017
    -- Note that there is no post byte
2018
    -- so do not advance PC in decode cycle
2019
    -- Re-run opcode fetch cycle after decode
2020
    -- 
2021
    when "0100" => -- acca single op
2022
      left_ctrl  <= acca_left;
2023
      case op_code(3 downto 0) is
2024
 
2025
      when "0000" => -- neg
2026
        right_ctrl <= zero_right;
2027
        alu_ctrl   <= alu_neg;
2028
        acca_ctrl  <= load_acca;
2029
        cc_ctrl    <= load_cc;
2030
 
2031
      when "0011" => -- com
2032
        right_ctrl <= zero_right;
2033
        alu_ctrl   <= alu_com;
2034
        acca_ctrl  <= load_acca;
2035
        cc_ctrl    <= load_cc;
2036
 
2037
      when "0100" => -- lsr
2038
        right_ctrl <= zero_right;
2039
        alu_ctrl   <= alu_lsr8;
2040
        acca_ctrl  <= load_acca;
2041
        cc_ctrl    <= load_cc;
2042
 
2043
           when "0110" => -- ror
2044
        right_ctrl <= zero_right;
2045
        alu_ctrl   <= alu_ror8;
2046
        acca_ctrl  <= load_acca;
2047
        cc_ctrl    <= load_cc;
2048
 
2049
      when "0111" => -- asr
2050
        right_ctrl <= zero_right;
2051
        alu_ctrl   <= alu_asr8;
2052
        acca_ctrl  <= load_acca;
2053
        cc_ctrl    <= load_cc;
2054
 
2055
      when "1000" => -- asl
2056
        right_ctrl <= zero_right;
2057
        alu_ctrl   <= alu_asl8;
2058
        acca_ctrl  <= load_acca;
2059
        cc_ctrl    <= load_cc;
2060
 
2061
      when "1001" => -- rol
2062
        right_ctrl <= zero_right;
2063
        alu_ctrl   <= alu_rol8;
2064
        acca_ctrl  <= load_acca;
2065
        cc_ctrl    <= load_cc;
2066
 
2067
      when "1010" => -- dec
2068
        right_ctrl <= one_right;
2069
        alu_ctrl   <= alu_dec;
2070
        acca_ctrl  <= load_acca;
2071
        cc_ctrl    <= load_cc;
2072
 
2073
      when "1011" => -- undefined
2074
        right_ctrl <= zero_right;
2075
        alu_ctrl   <= alu_nop;
2076
        acca_ctrl  <= latch_acca;
2077 122 dilbert57
        cc_ctrl    <= latch_cc;
2078 130 dilbert57
 
2079
      when "1100" => -- inc
2080
        right_ctrl <= one_right;
2081
        alu_ctrl   <= alu_inc;
2082
        acca_ctrl  <= load_acca;
2083
        cc_ctrl    <= load_cc;
2084
 
2085
      when "1101" => -- tst
2086
        right_ctrl <= zero_right;
2087
        alu_ctrl   <= alu_st8;
2088 122 dilbert57
        acca_ctrl  <= latch_acca;
2089 130 dilbert57
        cc_ctrl    <= load_cc;
2090
 
2091
      when "1110" => -- jmp (not defined)
2092 122 dilbert57
        right_ctrl <= zero_right;
2093
        alu_ctrl   <= alu_nop;
2094 130 dilbert57
        acca_ctrl  <= latch_acca;
2095
        cc_ctrl    <= latch_cc;
2096 122 dilbert57
 
2097 130 dilbert57
      when "1111" => -- clr
2098
        right_ctrl <= zero_right;
2099
        alu_ctrl   <= alu_clr;
2100
        acca_ctrl  <= load_acca;
2101
        cc_ctrl    <= load_cc;
2102 122 dilbert57
 
2103 130 dilbert57
      when others =>
2104
        right_ctrl <= zero_right;
2105
        alu_ctrl   <= alu_nop;
2106
        acca_ctrl  <= latch_acca;
2107
        cc_ctrl    <= latch_cc;
2108 122 dilbert57
 
2109 130 dilbert57
      end case;
2110
      lic        <= '1';
2111
      next_state <= fetch_state;
2112 122 dilbert57
 
2113 130 dilbert57
      --
2114
      -- Single Operand accb
2115
      -- source = accb, dest = accb
2116
      -- Typically 2 cycles 1 bytes
2117
      -- 1 opcode fetch
2118
      -- 2 post byte fetch / instruction decode
2119
      -- Note that there is no post byte
2120
      -- so do not advance PC in decode cycle
2121
      -- Re-run opcode fetch cycle after decode
2122
      --
2123
    when "0101" =>
2124
      left_ctrl  <= accb_left;
2125
      case op_code(3 downto 0) is
2126
      when "0000" => -- neg
2127
        right_ctrl <= zero_right;
2128
        alu_ctrl   <= alu_neg;
2129
        accb_ctrl  <= load_accb;
2130
        cc_ctrl    <= load_cc;
2131 122 dilbert57
 
2132 130 dilbert57
      when "0011" => -- com
2133
        right_ctrl <= zero_right;
2134
        alu_ctrl   <= alu_com;
2135
        accb_ctrl  <= load_accb;
2136
        cc_ctrl    <= load_cc;
2137 122 dilbert57
 
2138 130 dilbert57
      when "0100" => -- lsr
2139
        right_ctrl <= zero_right;
2140
        alu_ctrl   <= alu_lsr8;
2141
        accb_ctrl  <= load_accb;
2142
        cc_ctrl    <= load_cc;
2143 122 dilbert57
 
2144 130 dilbert57
      when "0110" => -- ror
2145
        right_ctrl <= zero_right;
2146
        alu_ctrl   <= alu_ror8;
2147
        accb_ctrl  <= load_accb;
2148
        cc_ctrl    <= load_cc;
2149 122 dilbert57
 
2150 130 dilbert57
      when "0111" => -- asr
2151
        right_ctrl <= zero_right;
2152
        alu_ctrl   <= alu_asr8;
2153
        accb_ctrl  <= load_accb;
2154
        cc_ctrl    <= load_cc;
2155 122 dilbert57
 
2156 130 dilbert57
      when "1000" => -- asl
2157
        right_ctrl <= zero_right;
2158
        alu_ctrl   <= alu_asl8;
2159
        accb_ctrl  <= load_accb;
2160
        cc_ctrl    <= load_cc;
2161 122 dilbert57
 
2162 130 dilbert57
      when "1001" => -- rol
2163
        right_ctrl <= zero_right;
2164
        alu_ctrl   <= alu_rol8;
2165
        accb_ctrl  <= load_accb;
2166
        cc_ctrl    <= load_cc;
2167 122 dilbert57
 
2168 130 dilbert57
      when "1010" => -- dec
2169
        right_ctrl <= one_right;
2170
        alu_ctrl   <= alu_dec;
2171
        accb_ctrl  <= load_accb;
2172
        cc_ctrl    <= load_cc;
2173 122 dilbert57
 
2174 130 dilbert57
      when "1011" => -- undefined
2175
        right_ctrl <= zero_right;
2176
        alu_ctrl   <= alu_nop;
2177
        accb_ctrl  <= latch_accb;
2178
        cc_ctrl    <= latch_cc;
2179 122 dilbert57
 
2180 130 dilbert57
      when "1100" => -- inc
2181
        right_ctrl <= one_right;
2182
        alu_ctrl   <= alu_inc;
2183
        accb_ctrl  <= load_accb;
2184
        cc_ctrl    <= load_cc;
2185 122 dilbert57
 
2186 130 dilbert57
      when "1101" => -- tst
2187
        right_ctrl <= zero_right;
2188
        alu_ctrl   <= alu_st8;
2189
        accb_ctrl  <= latch_accb;
2190
        cc_ctrl    <= load_cc;
2191 122 dilbert57
 
2192 130 dilbert57
      when "1110" => -- jmp (undefined)
2193
        right_ctrl <= zero_right;
2194
        alu_ctrl   <= alu_nop;
2195
        accb_ctrl  <= latch_accb;
2196
        cc_ctrl    <= latch_cc;
2197 122 dilbert57
 
2198 130 dilbert57
      when "1111" => -- clr
2199
        right_ctrl <= zero_right;
2200
        alu_ctrl   <= alu_clr;
2201
        accb_ctrl  <= load_accb;
2202
        cc_ctrl    <= load_cc;
2203 122 dilbert57
 
2204 130 dilbert57
      when others =>
2205
        right_ctrl <= zero_right;
2206
        alu_ctrl   <= alu_nop;
2207
        accb_ctrl  <= latch_accb;
2208
        cc_ctrl    <= latch_cc;
2209
      end case;
2210
      lic          <= '1';
2211
      next_state   <= fetch_state;
2212 122 dilbert57
 
2213 130 dilbert57
    --
2214
    -- Single operand indexed
2215
    -- Two byte instruction so advance PC
2216
    -- EA should hold index offset
2217
    --
2218
    when "0110" => -- indexed single op
2219
      -- increment the pc 
2220
      pc_ctrl    <= incr_pc;
2221
      st_ctrl    <= push_st;
2222
 
2223
      case op_code(3 downto 0) is
2224
      when "1110" => -- jmp
2225
        return_state <= jmp_state;
2226 122 dilbert57
 
2227 130 dilbert57
      when "1111" => -- clr
2228
        return_state <= single_op_exec_state;
2229 122 dilbert57
 
2230 130 dilbert57
      when others =>
2231
        return_state <= single_op_read_state;
2232 122 dilbert57
 
2233 130 dilbert57
      end case;
2234
      next_state <= indexed_state;
2235 122 dilbert57
 
2236 130 dilbert57
    --
2237
    -- Single operand extended addressing
2238
    -- three byte instruction so advance the PC
2239
    -- Low order EA holds high order address
2240
    --
2241
    when "0111" => -- extended single op
2242
      -- increment PC
2243
      pc_ctrl    <= incr_pc;
2244
      st_ctrl    <= push_st;
2245 122 dilbert57
 
2246 130 dilbert57
      case op_code(3 downto 0) is
2247
      when "1110" => -- jmp
2248
        return_state <= jmp_state;
2249
 
2250
      when "1111" => -- clr
2251
        return_state <= single_op_exec_state;
2252
 
2253
      when others =>
2254
        return_state <= single_op_read_state;
2255
 
2256
      end case;
2257
      next_state <= extended_state;
2258 122 dilbert57
 
2259 130 dilbert57
    when "1000" => -- acca immediate
2260
      -- increment the pc
2261
      pc_ctrl    <= incr_pc;
2262 122 dilbert57
 
2263 130 dilbert57
      case op_code(3 downto 0) is
2264
      when "0011" | -- subd #
2265
           "1100" | -- cmpx #
2266
           "1110" => -- ldx #
2267
        next_state   <= imm16_state;
2268 122 dilbert57
 
2269 130 dilbert57
      --
2270
      -- bsr offset - Branch to subroutine (2 bytes)
2271
      -- 6809 => 7 cycles
2272
      -- cpu09 => 5 cycles
2273
      -- 1 op=(pc) / pc=pc+1
2274
      -- 2 md_hi=sign(pc) / md_lo=(pc) / sp=sp-1 / pc=pc+1
2275
      -- 3 (sp)=pc_lo / sp=sp-1
2276
      -- 4 (sp)=pc_hi
2277
      -- 5 pc=pc+md
2278
      --
2279
      when "1101" => -- bsr
2280
        -- pre decrement SP
2281
        left_ctrl  <= sp_left;
2282
        right_ctrl <= one_right;
2283
        alu_ctrl   <= alu_sub16;
2284
        sp_ctrl    <= load_sp;
2285
             --
2286
             st_ctrl      <= push_st;
2287
        return_state <= sbranch_state;
2288
        next_state   <= push_return_lo_state;
2289 122 dilbert57
 
2290 130 dilbert57
      when others =>
2291
        lic          <= '1';
2292
        next_state   <= fetch_state;
2293 122 dilbert57
 
2294 130 dilbert57
      end case;
2295 122 dilbert57
 
2296 130 dilbert57
    when "1001" => -- acca direct
2297
      -- increment the pc
2298
      pc_ctrl    <= incr_pc;
2299
      case op_code(3 downto 0) is
2300
      when "0011" | -- subd
2301
           "1100" | -- cmpx
2302
           "1110" => -- ldx
2303
        next_state   <= dual_op_read16_state;
2304 122 dilbert57
 
2305 130 dilbert57
      when "0111" =>  -- sta direct
2306
        next_state <= dual_op_write8_state;
2307 122 dilbert57
 
2308 130 dilbert57
           --
2309
      -- jsr direct - Jump to subroutine in direct page (2 bytes)
2310
      -- 6809 => 7 cycles
2311
      -- cpu09 => 5 cycles
2312
      -- 1 op=(pc) / pc=pc+1
2313
      -- 2 ea_hi=0 / ea_lo=(pc) / sp=sp-1 / pc=pc+1
2314
      -- 3 (sp)=pc_lo / sp=sp-1
2315
      -- 4 (sp)=pc_hi
2316
      -- 5 pc=ea
2317
      --
2318
      when "1101" => -- jsr direct
2319
        -- pre decrement sp
2320
        left_ctrl  <= sp_left;
2321
        right_ctrl <= one_right;
2322
        alu_ctrl   <= alu_sub16;
2323
        sp_ctrl    <= load_sp;
2324
        --
2325
        st_ctrl      <= push_st;
2326
        return_state <= jmp_state;
2327
        next_state   <= push_return_lo_state;
2328 122 dilbert57
 
2329
 
2330 130 dilbert57
      when "1111" => -- stx direct
2331
        -- idle ALU
2332
        left_ctrl  <= ix_left;
2333
        right_ctrl <= zero_right;
2334
        alu_ctrl   <= alu_nop;
2335
        cc_ctrl    <= latch_cc;
2336
        sp_ctrl    <= latch_sp;
2337
        next_state <= dual_op_write16_state;
2338 122 dilbert57
 
2339 130 dilbert57
      when others =>
2340
        next_state   <= dual_op_read8_state;
2341 122 dilbert57
 
2342 130 dilbert57
      end case;
2343 122 dilbert57
 
2344 130 dilbert57
    when "1010" => -- acca indexed
2345
      -- increment the pc
2346
      pc_ctrl    <= incr_pc;
2347
      case op_code(3 downto 0) is
2348
      when "0011" | -- subd
2349
           "1100" | -- cmpx
2350
           "1110" => -- ldx
2351
        st_ctrl      <= push_st;
2352
        return_state <= dual_op_read16_state;
2353
        next_state   <= indexed_state;
2354 122 dilbert57
 
2355 130 dilbert57
      when "0111" =>  -- staa ,x
2356
        st_ctrl      <= push_st;
2357
        return_state <= dual_op_write8_state;
2358
        next_state   <= indexed_state;
2359 122 dilbert57
 
2360 130 dilbert57
      when "1101" => -- jsr ,x
2361
        -- DO NOT pre decrement SP
2362
        st_ctrl      <= push_st;
2363
        return_state <= jsr_state;
2364
        next_state   <= indexed_state;
2365 122 dilbert57
 
2366 130 dilbert57
      when "1111" => -- stx ,x
2367
        st_ctrl      <= push_st;
2368
        return_state <= dual_op_write16_state;
2369
        next_state   <= indexed_state;
2370 122 dilbert57
 
2371 130 dilbert57
      when others =>
2372
        st_ctrl      <= push_st;
2373
        return_state <= dual_op_read8_state;
2374
        next_state   <= indexed_state;
2375
 
2376
      end case;
2377 122 dilbert57
 
2378 130 dilbert57
   when "1011" => -- acca extended
2379
     -- increment the pc
2380
     pc_ctrl    <= incr_pc;
2381
     case op_code(3 downto 0) is
2382
     when "0011" | -- subd
2383
          "1100" | -- cmpx
2384
          "1110" => -- ldx
2385
       st_ctrl      <= push_st;
2386
       return_state <= dual_op_read16_state;
2387
       next_state   <= extended_state;
2388 122 dilbert57
 
2389 130 dilbert57
     when "0111" =>  -- staa >
2390
       st_ctrl      <= push_st;
2391
       return_state <= dual_op_write8_state;
2392
       next_state   <= extended_state;
2393 122 dilbert57
 
2394 130 dilbert57
     when "1101" => -- jsr >extended
2395
     -- DO NOT pre decrement sp
2396
       st_ctrl      <= push_st;
2397
       return_state <= jsr_state;
2398
       next_state   <= extended_state;
2399 122 dilbert57
 
2400 130 dilbert57
     when "1111" => -- stx >
2401
       st_ctrl      <= push_st;
2402
       return_state <= dual_op_write16_state;
2403
       next_state   <= extended_state;
2404 122 dilbert57
 
2405 130 dilbert57
     when others =>
2406
       st_ctrl      <= push_st;
2407
       return_state <= dual_op_read8_state;
2408
       next_state   <= extended_state;
2409 122 dilbert57
 
2410 130 dilbert57
     end case;
2411 122 dilbert57
 
2412 130 dilbert57
   when "1100" => -- accb immediate
2413
     -- increment the pc
2414
     pc_ctrl    <= incr_pc;
2415
     case op_code(3 downto 0) is
2416
     when "0011" | -- addd #
2417
          "1100" | -- ldd #
2418
          "1110" => -- ldu #
2419
       next_state   <= imm16_state;
2420 122 dilbert57
 
2421 130 dilbert57
     when others =>
2422
       lic          <= '1';
2423
       next_state   <= fetch_state;
2424 122 dilbert57
 
2425 130 dilbert57
     end case;
2426 122 dilbert57
 
2427 130 dilbert57
   when "1101" => -- accb direct
2428
     -- increment the pc
2429
     pc_ctrl    <= incr_pc;
2430
     case op_code(3 downto 0) is
2431
     when "0011" | -- addd
2432
          "1100" | -- ldd
2433
          "1110" => -- ldu
2434
       next_state   <= dual_op_read16_state;
2435 122 dilbert57
 
2436 130 dilbert57
     when "0111" =>  -- stab direct
2437
       next_state   <= dual_op_write8_state;
2438 122 dilbert57
 
2439 130 dilbert57
     when "1101" =>  -- std direct
2440
       next_state   <= dual_op_write16_state;
2441 122 dilbert57
 
2442 130 dilbert57
     when "1111" => -- stu direct
2443
       next_state   <= dual_op_write16_state;
2444 122 dilbert57
 
2445 130 dilbert57
     when others =>
2446
       next_state   <= dual_op_read8_state;
2447 122 dilbert57
 
2448 130 dilbert57
     end case;
2449 122 dilbert57
 
2450 130 dilbert57
   when "1110" => -- accb indexed
2451
     -- increment the pc
2452
     pc_ctrl    <= incr_pc;
2453
     case op_code(3 downto 0) is
2454
     when "0011" | -- addd
2455
          "1100" | -- ldd
2456
          "1110" => -- ldu
2457
       st_ctrl      <= push_st;
2458
       return_state <= dual_op_read16_state;
2459
       next_state   <= indexed_state;
2460 122 dilbert57
 
2461 130 dilbert57
     when "0111" =>  -- stab indexed
2462
       st_ctrl      <= push_st;
2463
       return_state <= dual_op_write8_state;
2464
       next_state   <= indexed_state;
2465 122 dilbert57
 
2466 130 dilbert57
     when "1101" =>  -- std indexed
2467
       st_ctrl      <= push_st;
2468
       return_state <= dual_op_write16_state;
2469
       next_state   <= indexed_state;
2470 122 dilbert57
 
2471 130 dilbert57
     when "1111" => -- stu indexed
2472
       st_ctrl      <= push_st;
2473
       return_state <= dual_op_write16_state;
2474
       next_state   <= indexed_state;
2475 122 dilbert57
 
2476 130 dilbert57
     when others =>
2477
       st_ctrl      <= push_st;
2478
       return_state <= dual_op_read8_state;
2479
       next_state   <= indexed_state;
2480
 
2481
     end case;
2482 122 dilbert57
 
2483 130 dilbert57
   when "1111" => -- accb extended
2484
     -- increment the pc
2485
     pc_ctrl    <= incr_pc;
2486
     case op_code(3 downto 0) is
2487
     when "0011" | -- addd
2488
                    "1100" | -- ldd
2489
               "1110" => -- ldu
2490
            st_ctrl      <= push_st;
2491
            return_state <= dual_op_read16_state;
2492
       next_state   <= extended_state;
2493 122 dilbert57
 
2494 130 dilbert57
     when "0111" =>  -- stab extended
2495
            st_ctrl      <= push_st;
2496
            return_state <= dual_op_write8_state;
2497
       next_state   <= extended_state;
2498 122 dilbert57
 
2499 130 dilbert57
     when "1101" =>  -- std extended
2500
       st_ctrl      <= push_st;
2501
            return_state <= dual_op_write16_state;
2502
            next_state   <= extended_state;
2503 122 dilbert57
 
2504 130 dilbert57
          when "1111" => -- stu  extended
2505
            st_ctrl      <= push_st;
2506
            return_state <= dual_op_write16_state;
2507
            next_state   <= extended_state;
2508 122 dilbert57
 
2509 130 dilbert57
          when others =>
2510
            st_ctrl      <= push_st;
2511
            return_state <= dual_op_read8_state;
2512
            next_state   <= extended_state;
2513
     end case;
2514
        --
2515
   -- not sure why I need this
2516
   --   
2517
   when others =>
2518
          lic <= '1';
2519
          next_state <= fetch_state;
2520
        end case;
2521 122 dilbert57
 
2522
                         --
2523
                         -- Here to decode prefix 2 instruction
2524
                         -- and fetch next byte of intruction
2525
                         -- whether it be necessary or not
2526
                         --
2527
          when decode2_state =>
2528
                                 -- fetch first byte of address or immediate data
2529
             ea_ctrl    <= fetch_first_ea;
2530
                                 md_ctrl    <= fetch_first_md;
2531
             addr_ctrl  <= fetch_ad;
2532
                            case op_code(7 downto 4) is
2533
                                 --
2534
                                 -- lbcc -- long branch conditional
2535
                                 -- 6809 => branch 6 cycles, no branch 5 cycles
2536
                                 -- cpu09 => always 5 cycles
2537
                                 -- 1 pre=(pc) / pc=pc+1
2538
                                 -- 2 op=(pc) / pc=pc+1
2539
                                 -- 3 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
2540
             -- 4 md_hi=md_lo / md_lo=(pc) / pc=pc+1
2541
                                 -- 5 if cond pc=pc+md else pc=pc
2542
                                 --
2543
                  when "0010" =>
2544
                                        -- increment the pc
2545
               pc_ctrl    <= incr_pc;
2546
                                        next_state <= lbranch_state;
2547
 
2548
                                 --
2549
                                 -- Single byte stack operators
2550
                                 -- Do not advance PC
2551
                                 --
2552
                  when "0011" =>
2553
                    case op_code(3 downto 0) is
2554
                         when "1111" => -- swi 2
2555
                                           -- predecrement sp
2556 130 dilbert57
                            left_ctrl    <= sp_left;
2557
                            right_ctrl   <= one_right;
2558
                                                alu_ctrl     <= alu_sub16;
2559
                                                sp_ctrl      <= load_sp;
2560
                                                iv_ctrl      <= swi2_iv;
2561
                                                st_ctrl      <= push_st;
2562
                                                return_state <= vect_hi_state;
2563
                                                next_state   <= int_entire_state;
2564 122 dilbert57
 
2565
                         when others =>
2566
                 lic          <= '1';
2567
                                          next_state   <= fetch_state;
2568
                         end case;
2569
 
2570
                  when "1000" => -- acca immediate
2571
                                   -- increment the pc
2572
               pc_ctrl    <= incr_pc;
2573
                                        case op_code(3 downto 0) is
2574
               when "0011" | -- cmpd #
2575
                                             "1100" | -- cmpy #
2576
                                             "1110" => -- ldy #
2577
                                          next_state   <= imm16_state;
2578
 
2579
                                        when others =>
2580
                 lic          <= '1';
2581
                                     next_state   <= fetch_state;
2582
 
2583
               end case;
2584
 
2585
                  when "1001" => -- acca direct
2586
                                        -- increment the pc
2587
               pc_ctrl    <= incr_pc;
2588
                                        case op_code(3 downto 0) is
2589
               when "0011" | -- cmpd <
2590
                                             "1100" | -- cmpy <
2591
                                             "1110" => -- ldy <
2592
                                          next_state   <= dual_op_read16_state;
2593
 
2594
                                        when "1111" => -- sty <
2595
                                     next_state   <= dual_op_write16_state;
2596
 
2597
                                        when others =>
2598
                 lic          <= '1';
2599
                                     next_state   <= fetch_state;
2600
 
2601
               end case;
2602
 
2603
                  when "1010" => -- acca indexed
2604
                                        -- increment the pc
2605
               pc_ctrl    <= incr_pc;
2606
                                        case op_code(3 downto 0) is
2607
               when "0011" | -- cmpd ,ind
2608
                                             "1100" | -- cmpy ,ind
2609
                                             "1110" => -- ldy ,ind
2610
                                     st_ctrl      <= push_st;
2611
                                     return_state <= dual_op_read16_state;
2612
                                          next_state   <= indexed_state;
2613
 
2614
                                        when "1111" => -- sty ,ind
2615
                                     st_ctrl      <= push_st;
2616
                                     return_state <= dual_op_write16_state;
2617
                                     next_state   <= indexed_state;
2618
 
2619
                                        when others =>
2620
                 lic          <= '1';
2621
                                     next_state   <= fetch_state;
2622
               end case;
2623
 
2624
             when "1011" => -- acca extended
2625
                                        -- increment the pc
2626
               pc_ctrl    <= incr_pc;
2627
                                        case op_code(3 downto 0) is
2628
               when "0011" | -- cmpd <
2629
                                             "1100" | -- cmpy <
2630
                                             "1110" => -- ldy <
2631
                                     st_ctrl      <= push_st;
2632
                                     return_state <= dual_op_read16_state;
2633
                                          next_state   <= extended_state;
2634
 
2635
                                        when "1111" => -- sty >
2636
                                     st_ctrl      <= push_st;
2637
                                     return_state <= dual_op_write16_state;
2638
                                     next_state   <= extended_state;
2639
 
2640
                                        when others =>
2641
                 lic          <= '1';
2642
                                     next_state   <= fetch_state;
2643
 
2644
               end case;
2645
 
2646
                  when "1100" => -- accb immediate
2647
                                        -- increment the pc
2648
               pc_ctrl    <= incr_pc;
2649
                                        case op_code(3 downto 0) is
2650
               when "0011" | -- undef #
2651
                                             "1100" | -- undef #
2652
                                             "1110" => -- lds #
2653
                                          next_state   <= imm16_state;
2654
 
2655
                                        when others =>
2656
                                     next_state   <= fetch_state;
2657
 
2658
               end case;
2659
 
2660
                  when "1101" => -- accb direct
2661
                                        -- increment the pc
2662
               pc_ctrl    <= incr_pc;
2663
                                        case op_code(3 downto 0) is
2664
               when "0011" | -- undef <
2665
                                             "1100" | -- undef <
2666
                                             "1110" => -- lds <
2667
                                          next_state   <= dual_op_read16_state;
2668
 
2669
                                        when "1111" => -- sts <
2670
                                     next_state   <= dual_op_write16_state;
2671
 
2672
                                        when others =>
2673
                 lic          <= '1';
2674
                                     next_state   <= fetch_state;
2675
 
2676
               end case;
2677
 
2678
                  when "1110" => -- accb indexed
2679
                                        -- increment the pc
2680
               pc_ctrl    <= incr_pc;
2681
                                        case op_code(3 downto 0) is
2682
               when "0011" | -- undef ,ind
2683
                                             "1100" | -- undef ,ind
2684
                                             "1110" => -- lds ,ind
2685
                                     st_ctrl      <= push_st;
2686
                                     return_state <= dual_op_read16_state;
2687
                                          next_state   <= indexed_state;
2688
 
2689
                                        when "1111" => -- sts ,ind
2690
                                     st_ctrl      <= push_st;
2691
                                     return_state <= dual_op_write16_state;
2692
                                     next_state   <= indexed_state;
2693
 
2694
                                        when others =>
2695
                 lic          <= '1';
2696
                                     next_state   <= fetch_state;
2697
 
2698
               end case;
2699
 
2700
             when "1111" => -- accb extended
2701
                                        -- increment the pc
2702
               pc_ctrl    <= incr_pc;
2703
                                        case op_code(3 downto 0) is
2704
               when "0011" | -- undef >
2705
                                             "1100" | -- undef >
2706
                                             "1110" => -- lds >
2707
                                     st_ctrl      <= push_st;
2708
                                     return_state <= dual_op_read16_state;
2709
                                          next_state   <= extended_state;
2710
 
2711
                                        when "1111" => -- sts >
2712
                                     st_ctrl      <= push_st;
2713
                                     return_state <= dual_op_write16_state;
2714
                                     next_state   <= extended_state;
2715
 
2716
                                        when others =>
2717
                 lic          <= '1';
2718
                                     next_state   <= fetch_state;
2719
               end case;
2720
 
2721
                  when others =>
2722
               lic          <= '1';
2723
                         next_state   <= fetch_state;
2724
             end case;
2725
                         --
2726
                         -- Here to decode instruction
2727
                         -- and fetch next byte of intruction
2728
                         -- whether it be necessary or not
2729
                         --
2730
          when decode3_state =>
2731
             ea_ctrl    <= fetch_first_ea;
2732
                                 md_ctrl    <= fetch_first_md;
2733
             addr_ctrl  <= fetch_ad;
2734
             dout_ctrl  <= md_lo_dout;
2735
                            case op_code(7 downto 4) is
2736
                                 --
2737
                                 -- Single byte stack operators
2738
                                 -- Do not advance PC
2739
                                 --
2740
                  when "0011" =>
2741
                    case op_code(3 downto 0) is
2742
                         when "1111" => -- swi3
2743
                                           -- predecrement sp
2744 130 dilbert57
                            left_ctrl    <= sp_left;
2745
                            right_ctrl   <= one_right;
2746
                                                alu_ctrl     <= alu_sub16;
2747
                                                sp_ctrl      <= load_sp;
2748
                                                iv_ctrl      <= swi3_iv;
2749
                                                st_ctrl      <= push_st;
2750
                                                return_state <= vect_hi_state;
2751
                                                next_state   <= int_entire_state;
2752 122 dilbert57
                         when others =>
2753
                 lic          <= '1';
2754
                                          next_state   <= fetch_state;
2755
                         end case;
2756
 
2757
                  when "1000" => -- acca immediate
2758
                                   -- increment the pc
2759
               pc_ctrl    <= incr_pc;
2760
                                        case op_code(3 downto 0) is
2761
               when "0011" | -- cmpu #
2762
                                             "1100" | -- cmps #
2763
                                             "1110" => -- undef #
2764
                                          next_state   <= imm16_state;
2765
                                        when others =>
2766
                 lic          <= '1';
2767
                                     next_state   <= fetch_state;
2768
               end case;
2769
 
2770
                  when "1001" => -- acca direct
2771
                                        -- increment the pc
2772
               pc_ctrl    <= incr_pc;
2773
                                        case op_code(3 downto 0) is
2774
               when "0011" | -- cmpu <
2775
                                             "1100" | -- cmps <
2776
                                             "1110" => -- undef <
2777
                                          next_state   <= dual_op_read16_state;
2778
 
2779
                                        when others =>
2780
                 lic          <= '1';
2781
                                     next_state   <= fetch_state;
2782
 
2783
               end case;
2784
 
2785
                  when "1010" => -- acca indexed
2786
                                        -- increment the pc
2787
               pc_ctrl    <= incr_pc;
2788
                                        case op_code(3 downto 0) is
2789
               when "0011" | -- cmpu ,X
2790
                                             "1100" | -- cmps ,X
2791
                                             "1110" => -- undef ,X
2792
                                     st_ctrl      <= push_st;
2793
                                     return_state <= dual_op_read16_state;
2794
                                          next_state   <= indexed_state;
2795
 
2796
                                        when others =>
2797
                 lic          <= '1';
2798
                                     next_state   <= fetch_state;
2799
 
2800
               end case;
2801
 
2802
             when "1011" => -- acca extended
2803
                                        -- increment the pc
2804
               pc_ctrl    <= incr_pc;
2805
                                        case op_code(3 downto 0) is
2806
               when "0011" | -- cmpu >
2807
                                             "1100" | -- cmps >
2808
                                             "1110" => -- undef >
2809
                                     st_ctrl      <= push_st;
2810
                                     return_state <= dual_op_read16_state;
2811
                                          next_state   <= extended_state;
2812
                                        when others =>
2813
                 lic          <= '1';
2814
                                     next_state   <= fetch_state;
2815
               end case;
2816
 
2817
                  when others =>
2818
               lic          <= '1';
2819
                         next_state   <= fetch_state;
2820
             end case;
2821
 
2822
           --
2823
                          -- here if ea holds low byte
2824
                          -- Direct
2825
                          -- Extended
2826
                          -- Indexed
2827
                          -- read memory location
2828
                          --
2829
                          when single_op_read_state =>
2830
                                        -- read memory into md
2831
                                   md_ctrl    <= fetch_first_md;
2832
               addr_ctrl  <= read_ad;
2833
                                        dout_ctrl  <= md_lo_dout;
2834
                                        next_state <= single_op_exec_state;
2835
 
2836
                when single_op_exec_state =>
2837
                    case op_code(3 downto 0) is
2838
                         when "0000" => -- neg
2839
                   left_ctrl  <= md_left;
2840
                                            right_ctrl <= zero_right;
2841
                                            alu_ctrl   <= alu_neg;
2842
                                            cc_ctrl    <= load_cc;
2843
                                       md_ctrl    <= load_md;
2844
                                       next_state <= single_op_write_state;
2845
                    when "0011" => -- com
2846
                   left_ctrl  <= md_left;
2847
                             right_ctrl <= zero_right;
2848
                                            alu_ctrl   <= alu_com;
2849
                                            cc_ctrl    <= load_cc;
2850
                                       md_ctrl    <= load_md;
2851
                                       next_state <= single_op_write_state;
2852
                         when "0100" => -- lsr
2853
                   left_ctrl  <= md_left;
2854
                                                 right_ctrl <= zero_right;
2855
                                            alu_ctrl   <= alu_lsr8;
2856
                                            cc_ctrl    <= load_cc;
2857
                                       md_ctrl    <= load_md;
2858
                                       next_state <= single_op_write_state;
2859
                         when "0110" => -- ror
2860
                   left_ctrl  <= md_left;
2861
                                                 right_ctrl <= zero_right;
2862
                                            alu_ctrl   <= alu_ror8;
2863
                                            cc_ctrl    <= load_cc;
2864
                                       md_ctrl    <= load_md;
2865
                                       next_state <= single_op_write_state;
2866
                         when "0111" => -- asr
2867
                   left_ctrl  <= md_left;
2868
                                                 right_ctrl <= zero_right;
2869
                                            alu_ctrl   <= alu_asr8;
2870
                                            cc_ctrl    <= load_cc;
2871
                                       md_ctrl    <= load_md;
2872
                                       next_state <= single_op_write_state;
2873
                         when "1000" => -- asl
2874
                   left_ctrl  <= md_left;
2875
                                                 right_ctrl <= zero_right;
2876
                                            alu_ctrl   <= alu_asl8;
2877
                                            cc_ctrl    <= load_cc;
2878
                                       md_ctrl    <= load_md;
2879
                                       next_state <= single_op_write_state;
2880
                         when "1001" => -- rol
2881
                   left_ctrl  <= md_left;
2882
                                                 right_ctrl <= zero_right;
2883
                                            alu_ctrl   <= alu_rol8;
2884
                                            cc_ctrl    <= load_cc;
2885
                                       md_ctrl    <= load_md;
2886
                                       next_state <= single_op_write_state;
2887
                         when "1010" => -- dec
2888
                   left_ctrl  <= md_left;
2889
                             right_ctrl <= one_right;
2890
                                            alu_ctrl   <= alu_dec;
2891
                                            cc_ctrl    <= load_cc;
2892
                                       md_ctrl    <= load_md;
2893
                                       next_state <= single_op_write_state;
2894
                         when "1011" => -- undefined
2895
                   lic        <= '1';
2896
                                       next_state <= fetch_state;
2897
                         when "1100" => -- inc
2898
                   left_ctrl  <= md_left;
2899
                             right_ctrl <= one_right;
2900
                                            alu_ctrl   <= alu_inc;
2901
                                            cc_ctrl    <= load_cc;
2902
                                       md_ctrl    <= load_md;
2903
                                       next_state <= single_op_write_state;
2904
                         when "1101" => -- tst
2905
                   left_ctrl  <= md_left;
2906
                             right_ctrl <= zero_right;
2907
                                            alu_ctrl   <= alu_st8;
2908
                                            cc_ctrl    <= load_cc;
2909
                   lic        <= '1';
2910
                                       next_state <= fetch_state;
2911
                         when "1110" => -- jmp
2912
                   left_ctrl  <= md_left;
2913
                                                 right_ctrl <= zero_right;
2914
                                            alu_ctrl   <= alu_ld16;
2915
                   pc_ctrl    <= load_pc;
2916
                   lic          <= '1';
2917
                                       next_state <= fetch_state;
2918
                         when "1111" => -- clr
2919
                   left_ctrl  <= md_left;
2920
                                                 right_ctrl <= zero_right;
2921
                                            alu_ctrl   <= alu_clr;
2922
                                            cc_ctrl    <= load_cc;
2923
                                       md_ctrl    <= load_md;
2924
                                       next_state <= single_op_write_state;
2925
                         when others =>
2926
                 lic        <= '1';
2927
                                     next_state <= fetch_state;
2928
                         end case;
2929
           --
2930
                          -- single operand 8 bit write
2931
                          -- Write low 8 bits of ALU output
2932
                          -- EA holds address
2933
                          -- MD holds data
2934
                          --
2935
                          when single_op_write_state =>
2936
                                 -- write ALU low byte output
2937
             addr_ctrl  <= write_ad;
2938
             dout_ctrl  <= md_lo_dout;
2939
             lic        <= '1';
2940
                                 next_state <= fetch_state;
2941
 
2942
           --
2943
                          -- here if ea holds address of low byte
2944
                          -- read memory location
2945
                          --
2946
                          when dual_op_read8_state =>
2947
                                   -- read first data byte from ea
2948
                                   md_ctrl    <= fetch_first_md;
2949
               addr_ctrl  <= read_ad;
2950
               lic        <= '1';
2951
                                        next_state <= fetch_state;
2952
 
2953
                                --
2954
                                -- Here to read a 16 bit value into MD
2955
                                -- pointed to by the EA register
2956
                                -- The first byte is read
2957
                                -- and the EA is incremented
2958
                                --
2959
                           when dual_op_read16_state =>
2960
                                        -- increment the effective address
2961
               left_ctrl  <= ea_left;
2962
               right_ctrl <= one_right;
2963
               alu_ctrl   <= alu_add16;
2964
               ea_ctrl    <= load_ea;
2965
                                        -- read the high byte of the 16 bit data
2966
                                   md_ctrl    <= fetch_first_md;
2967
               addr_ctrl  <= read_ad;
2968
                                        next_state <= dual_op_read16_2_state;
2969
 
2970
                                --
2971
                                -- here to read the second byte
2972
                           -- pointed to by EA into MD
2973
                                --
2974
                           when dual_op_read16_2_state =>
2975
                                        -- read the low byte of the 16 bit data
2976
                                   md_ctrl    <= fetch_next_md;
2977
               addr_ctrl  <= read_ad;
2978
               lic        <= '1';
2979
                                        next_state <= fetch_state;
2980
 
2981
           --
2982
                          -- 16 bit Write state
2983
                          -- EA hold address of memory to write to
2984
                          -- Advance the effective address in ALU
2985
                          -- decode op_code to determine which
2986
                          -- register to write
2987
                          --
2988
                          when dual_op_write16_state =>
2989
                                 -- increment the effective address
2990
                                 left_ctrl  <= ea_left;
2991
                                 right_ctrl <= one_right;
2992
                                 alu_ctrl   <= alu_add16;
2993
                            ea_ctrl    <= load_ea;
2994
                                 -- write the ALU hi byte at ea
2995
             addr_ctrl  <= write_ad;
2996
                                 if op_code(6) = '0' then
2997
                                   case op_code(3 downto 0) is
2998
                              when "1111" => -- stx / sty
2999
                                          case pre_code is
3000
                                          when "00010000" => -- page 2 -- sty
3001
                        dout_ctrl  <= iy_hi_dout;
3002
                                     when others =>     -- page 1 -- stx
3003
                   dout_ctrl  <= ix_hi_dout;
3004
                                          end case;
3005
                                   when others =>
3006
                 dout_ctrl  <= md_hi_dout;
3007
                                   end case;
3008
             else
3009
                                   case op_code(3 downto 0) is
3010
                              when "1101" => -- std
3011
                 dout_ctrl  <= acca_dout; -- acca is high byte of ACCD
3012
                              when "1111" => -- stu / sts
3013
                                          case pre_code is
3014
                                          when "00010000" => -- page 2 -- sts
3015
                        dout_ctrl  <= sp_hi_dout;
3016
                                          when others =>     -- page 1 -- stu
3017
                        dout_ctrl  <= up_hi_dout;
3018
                                          end case;
3019
                                   when others =>
3020
                 dout_ctrl  <= md_hi_dout;
3021
                                   end case;
3022
             end if;
3023
                                 next_state   <= dual_op_write8_state;
3024
 
3025
           --
3026
                          -- Dual operand 8 bit write
3027
           -- Write 8 bit accumulator
3028
                          -- or low byte of 16 bit register
3029
                          -- EA holds address
3030
                          -- decode opcode to determine
3031
                          -- which register to apply to the bus
3032
                          -- Also set the condition codes here
3033
                          --
3034
                          when dual_op_write8_state =>
3035
                            if op_code(6) = '0' then
3036
                                   case op_code(3 downto 0) is
3037
                                        when "0111" => -- sta
3038
                 dout_ctrl  <= acca_dout;
3039
                                        when "1111" => -- stx / sty
3040
                                          case pre_code is
3041
                                          when "00010000" => -- page 2 -- sty
3042
                        dout_ctrl  <= iy_lo_dout;
3043
                                     when others =>     -- page 1 -- stx
3044
                   dout_ctrl  <= ix_lo_dout;
3045
                                          end case;
3046
                                        when others =>
3047
                 dout_ctrl  <= md_lo_dout;
3048
                                        end case;
3049
             else
3050
                                   case op_code(3 downto 0) is
3051
                                        when "0111" => -- stb
3052
                 dout_ctrl  <= accb_dout;
3053
                                        when "1101" => -- std
3054
                 dout_ctrl  <= accb_dout; -- accb is low byte of accd
3055
                                        when "1111" => -- stu / sts
3056
                                          case pre_code is
3057
                                          when "00010000" => -- page 2 -- sts
3058
                        dout_ctrl  <= sp_lo_dout;
3059
                                          when others =>     -- page 1 -- stu
3060
                        dout_ctrl  <= up_lo_dout;
3061
                                          end case;
3062
                                        when others =>
3063
                 dout_ctrl  <= md_lo_dout;
3064
                                        end case;
3065
             end if;
3066
                                 -- write ALU low byte output
3067
             addr_ctrl    <= write_ad;
3068
             lic          <= '1';
3069
                                 next_state   <= fetch_state;
3070
 
3071
                          --
3072
                          -- 16 bit immediate addressing mode
3073
                          --
3074
                          when imm16_state =>
3075
                                   -- increment pc
3076
               pc_ctrl    <= incr_pc;
3077
                                   -- fetch next immediate byte
3078
                              md_ctrl    <= fetch_next_md;
3079
               addr_ctrl  <= fetch_ad;
3080
               lic        <= '1';
3081 130 dilbert57
                                        next_state <= fetch_state;
3082 122 dilbert57
 
3083
           --
3084
                          -- md & ea holds 8 bit index offset
3085
                          -- calculate the effective memory address
3086
                          -- using the alu
3087
                          --
3088
           when indexed_state =>
3089
                                 --
3090
                                 -- decode indexing mode
3091
                                 --
3092
                                 if md(7) = '0' then
3093
                                   case md(6 downto 5) is
3094
                                        when "00" =>
3095
                                left_ctrl  <= ix_left;
3096
                                        when "01" =>
3097
                                left_ctrl  <= iy_left;
3098
                                        when "10" =>
3099
                                left_ctrl  <= up_left;
3100
                                        when others =>
3101
                                        -- when "11" =>
3102
                                left_ctrl  <= sp_left;
3103
                                        end case;
3104
                                   right_ctrl   <= md_sign5_right;
3105
                                   alu_ctrl     <= alu_add16;
3106
               ea_ctrl      <= load_ea;
3107
                                        next_state   <= saved_state;
3108
 
3109
                                 else
3110
                                   case md(3 downto 0) is
3111
                                        when "0000" =>     -- ,R+
3112
                                     case md(6 downto 5) is
3113
                                          when "00" =>
3114
                                  left_ctrl  <= ix_left;
3115
                                          when "01" =>
3116
                                  left_ctrl  <= iy_left;
3117
                                          when "10" =>
3118
                                  left_ctrl  <= up_left;
3119
                                          when others =>
3120
                                  left_ctrl  <= sp_left;
3121
                                          end case;
3122
                                          --
3123
                                     right_ctrl <= zero_right;
3124
                                     alu_ctrl   <= alu_add16;
3125
                 ea_ctrl    <= load_ea;
3126
                 next_state <= postincr1_state;
3127
 
3128
                                        when "0001" =>     -- ,R++
3129
                                     case md(6 downto 5) is
3130
                                          when "00" =>
3131
                                  left_ctrl  <= ix_left;
3132
                                          when "01" =>
3133
                                  left_ctrl  <= iy_left;
3134
                                          when "10" =>
3135
                                  left_ctrl  <= up_left;
3136
                                          when others =>
3137
                                          -- when "11" =>
3138
                                  left_ctrl  <= sp_left;
3139
                                          end case;
3140
                                     right_ctrl <= zero_right;
3141
                                     alu_ctrl   <= alu_add16;
3142
                 ea_ctrl    <= load_ea;
3143
                 next_state <= postincr2_state;
3144
 
3145
                                        when "0010" =>     -- ,-R
3146
                                     case md(6 downto 5) is
3147
                                          when "00" =>
3148
                                  left_ctrl  <= ix_left;
3149
                   ix_ctrl    <= load_ix;
3150
                                          when "01" =>
3151
                                  left_ctrl  <= iy_left;
3152
                   iy_ctrl    <= load_iy;
3153
                                          when "10" =>
3154
                                  left_ctrl  <= up_left;
3155
                   up_ctrl    <= load_up;
3156
                                          when others =>
3157
                                          -- when "11" =>
3158
                                  left_ctrl  <= sp_left;
3159
                   sp_ctrl    <= load_sp;
3160
                                          end case;
3161
                                     right_ctrl   <= one_right;
3162
                                     alu_ctrl     <= alu_sub16;
3163
                 ea_ctrl      <= load_ea;
3164
                                          next_state   <= saved_state;
3165
 
3166
                                        when "0011" =>     -- ,--R
3167
                                     case md(6 downto 5) is
3168
                                          when "00" =>
3169
                                  left_ctrl  <= ix_left;
3170
                   ix_ctrl    <= load_ix;
3171
                                          when "01" =>
3172
                                  left_ctrl  <= iy_left;
3173
                   iy_ctrl    <= load_iy;
3174
                                          when "10" =>
3175
                                  left_ctrl  <= up_left;
3176
                   up_ctrl    <= load_up;
3177
                                          when others =>
3178
                                          -- when "11" =>
3179
                                  left_ctrl  <= sp_left;
3180
                   sp_ctrl    <= load_sp;
3181
                                          end case;
3182
                                     right_ctrl <= two_right;
3183
                                     alu_ctrl   <= alu_sub16;
3184
                 ea_ctrl    <= load_ea;
3185
                                          if md(4) = '0' then
3186
                                            next_state   <= saved_state;
3187
                                          else
3188
                                            next_state   <= indirect_state;
3189
                                          end if;
3190
 
3191
                                        when "0100" =>     -- ,R (zero offset)
3192
                                     case md(6 downto 5) is
3193
                                          when "00" =>
3194
                                  left_ctrl  <= ix_left;
3195
                                          when "01" =>
3196
                                  left_ctrl  <= iy_left;
3197
                                          when "10" =>
3198
                                  left_ctrl  <= up_left;
3199
                                          when others =>
3200
                                          -- when "11" =>
3201
                                  left_ctrl  <= sp_left;
3202
                                          end case;
3203
                                     right_ctrl <= zero_right;
3204
                                     alu_ctrl   <= alu_add16;
3205
                 ea_ctrl    <= load_ea;
3206
                                          if md(4) = '0' then
3207
                                            next_state   <= saved_state;
3208
                                          else
3209
                                            next_state   <= indirect_state;
3210
                                          end if;
3211
 
3212
                                        when "0101" =>     -- ACCB,R
3213
                                     case md(6 downto 5) is
3214
                                          when "00" =>
3215
                                  left_ctrl  <= ix_left;
3216
                                          when "01" =>
3217
                                  left_ctrl  <= iy_left;
3218
                                          when "10" =>
3219
                                  left_ctrl  <= up_left;
3220
                                          when others =>
3221
                                          -- when "11" =>
3222
                                  left_ctrl  <= sp_left;
3223
                                          end case;
3224
                                     right_ctrl <= accb_right;
3225
                                     alu_ctrl   <= alu_add16;
3226
                 ea_ctrl    <= load_ea;
3227
                                          if md(4) = '0' then
3228
                                            next_state   <= saved_state;
3229
                                          else
3230
                                            next_state   <= indirect_state;
3231
                                          end if;
3232
 
3233
                                        when "0110" =>     -- ACCA,R
3234
                                     case md(6 downto 5) is
3235
                                          when "00" =>
3236
                                  left_ctrl  <= ix_left;
3237
                                          when "01" =>
3238
                                  left_ctrl  <= iy_left;
3239
                                          when "10" =>
3240
                                  left_ctrl  <= up_left;
3241
                                          when others =>
3242
                                          -- when "11" =>
3243
                                  left_ctrl  <= sp_left;
3244
                                          end case;
3245
                                     right_ctrl <= acca_right;
3246
                                     alu_ctrl   <= alu_add16;
3247
                 ea_ctrl    <= load_ea;
3248
                                          if md(4) = '0' then
3249
                                            next_state   <= saved_state;
3250
                                          else
3251
                                            next_state   <= indirect_state;
3252
                                          end if;
3253
 
3254
                                        when "0111" =>     -- undefined
3255
                                     case md(6 downto 5) is
3256
                                          when "00" =>
3257
                                  left_ctrl  <= ix_left;
3258
                                          when "01" =>
3259
                                  left_ctrl  <= iy_left;
3260
                                          when "10" =>
3261
                                  left_ctrl  <= up_left;
3262
                                          when others =>
3263
                                          -- when "11" =>
3264
                                  left_ctrl  <= sp_left;
3265
                                          end case;
3266
                                     right_ctrl <= zero_right;
3267
                                     alu_ctrl   <= alu_add16;
3268
                 ea_ctrl    <= load_ea;
3269
                                          if md(4) = '0' then
3270
                                            next_state   <= saved_state;
3271
                                          else
3272
                                            next_state   <= indirect_state;
3273
                                          end if;
3274
 
3275
                                        when "1000" =>     -- offset8,R
3276
                 md_ctrl    <= fetch_first_md; -- pick up 8 bit offset
3277
                 addr_ctrl  <= fetch_ad;
3278
                 pc_ctrl    <= incr_pc;
3279
                 next_state <= index8_state;
3280
 
3281
                                        when "1001" =>     -- offset16,R
3282
                 md_ctrl    <= fetch_first_md; -- pick up first byte of 16 bit offset
3283
                 addr_ctrl  <= fetch_ad;
3284
                 pc_ctrl    <= incr_pc;
3285
                 next_state <= index16_state;
3286
 
3287
                                        when "1010" =>     -- undefined
3288
                                     case md(6 downto 5) is
3289
                                          when "00" =>
3290
                                  left_ctrl  <= ix_left;
3291
                                          when "01" =>
3292
                                  left_ctrl  <= iy_left;
3293
                                          when "10" =>
3294
                                  left_ctrl  <= up_left;
3295
                                          when others =>
3296
                                          -- when "11" =>
3297
                                  left_ctrl  <= sp_left;
3298
                                          end case;
3299
                                     right_ctrl <= zero_right;
3300
                                     alu_ctrl   <= alu_add16;
3301
                 ea_ctrl    <= load_ea;
3302
                                          --
3303
                                          if md(4) = '0' then
3304
                                            next_state   <= saved_state;
3305
                                          else
3306
                                            next_state   <= indirect_state;
3307
                                          end if;
3308
 
3309
                                        when "1011" =>     -- ACCD,R
3310
                                     case md(6 downto 5) is
3311
                                          when "00" =>
3312
                                  left_ctrl  <= ix_left;
3313
                                          when "01" =>
3314
                                  left_ctrl  <= iy_left;
3315
                                          when "10" =>
3316
                                  left_ctrl  <= up_left;
3317
                                          when others =>
3318
                                          -- when "11" =>
3319
                                  left_ctrl  <= sp_left;
3320
                                          end case;
3321
                                     right_ctrl <= accd_right;
3322
                                     alu_ctrl   <= alu_add16;
3323
                 ea_ctrl    <= load_ea;
3324
                                          if md(4) = '0' then
3325
                                            next_state   <= saved_state;
3326
                                          else
3327
                                            next_state   <= indirect_state;
3328
                                          end if;
3329
 
3330
                                        when "1100" =>     -- offset8,PC
3331
                                          -- fetch 8 bit offset
3332
                 md_ctrl    <= fetch_first_md;
3333
                 addr_ctrl  <= fetch_ad;
3334
                 pc_ctrl    <= incr_pc;
3335
                 next_state <= pcrel8_state;
3336
 
3337
                                        when "1101" =>     -- offset16,PC
3338
                                          -- fetch offset
3339
                 md_ctrl    <= fetch_first_md;
3340
                 addr_ctrl  <= fetch_ad;
3341
                 pc_ctrl    <= incr_pc;
3342
                 next_state <= pcrel16_state;
3343
 
3344
                                        when "1110" =>     -- undefined
3345
                                     case md(6 downto 5) is
3346
                                          when "00" =>
3347
                                  left_ctrl  <= ix_left;
3348
                                          when "01" =>
3349
                                  left_ctrl  <= iy_left;
3350
                                          when "10" =>
3351
                                  left_ctrl  <= up_left;
3352
                                          when others =>
3353
                                          -- when "11" =>
3354
                                  left_ctrl  <= sp_left;
3355
                                          end case;
3356
                                     right_ctrl <= zero_right;
3357
                                     alu_ctrl   <= alu_add16;
3358
                 ea_ctrl    <= load_ea;
3359
                                          if md(4) = '0' then
3360
                                            next_state   <= saved_state;
3361
                                          else
3362
                                            next_state   <= indirect_state;
3363
                                          end if;
3364
 
3365
               when others =>
3366
--                      when "1111" =>     -- [,address]
3367
                                          -- advance PC to pick up address
3368
                 md_ctrl    <= fetch_first_md;
3369
                 addr_ctrl  <= fetch_ad;
3370
                                          pc_ctrl    <= incr_pc;
3371
                 next_state <= indexaddr_state;
3372
                                        end case;
3373
                                 end if;
3374
 
3375
                          -- load index register with ea plus one
3376
                          when postincr1_state =>
3377
                            left_ctrl  <= ea_left;
3378
                            right_ctrl <= one_right;
3379
                            alu_ctrl   <= alu_add16;
3380
                                 case md(6 downto 5) is
3381
                            when "00" =>
3382
               ix_ctrl    <= load_ix;
3383
                                 when "01" =>
3384
               iy_ctrl    <= load_iy;
3385
                                 when "10" =>
3386
               up_ctrl    <= load_up;
3387
                                 when others =>
3388
                                 -- when "11" =>
3389
               sp_ctrl    <= load_sp;
3390
                            end case;
3391
                                 -- return to previous state
3392
                            if md(4) = '0' then
3393
                                         next_state   <= saved_state;
3394
                                 else
3395
                                         next_state   <= indirect_state;
3396
                                 end if;
3397
 
3398
                          -- load index register with ea plus two
3399
                          when postincr2_state =>
3400
                                 -- increment register by two (address)
3401
                            left_ctrl  <= ea_left;
3402
                            right_ctrl <= two_right;
3403
                            alu_ctrl   <= alu_add16;
3404
                                 case md(6 downto 5) is
3405
                            when "00" =>
3406
               ix_ctrl    <= load_ix;
3407
                                 when "01" =>
3408
               iy_ctrl    <= load_iy;
3409
                                 when "10" =>
3410
               up_ctrl    <= load_up;
3411
                                 when others =>
3412
                                 -- when "11" =>
3413
               sp_ctrl    <= load_sp;
3414
                            end case;
3415
                                 -- return to previous state
3416
                            if md(4) = '0' then
3417
                                         next_state   <= saved_state;
3418
                                 else
3419
                                         next_state   <= indirect_state;
3420
                                 end if;
3421
           --
3422
                          -- ea = index register + md (8 bit signed offset)
3423
                          -- ea holds post byte
3424
                          --
3425
                          when index8_state =>
3426
                                 case ea(6 downto 5) is
3427
                            when "00" =>
3428
                              left_ctrl  <= ix_left;
3429
                            when "01" =>
3430
                              left_ctrl  <= iy_left;
3431
                                 when "10" =>
3432
                              left_ctrl  <= up_left;
3433
                                 when others =>
3434
                                 -- when "11" =>
3435
                              left_ctrl  <= sp_left;
3436
                                 end case;
3437
                                 -- ea = index reg + md
3438
                            right_ctrl <= md_sign8_right;
3439
                            alu_ctrl   <= alu_add16;
3440
             ea_ctrl    <= load_ea;
3441
                                 -- return to previous state
3442
                            if ea(4) = '0' then
3443
                                         next_state   <= saved_state;
3444
                                 else
3445
                                         next_state   <= indirect_state;
3446
                                 end if;
3447
 
3448
                          -- fetch low byte of 16 bit indexed offset
3449
                          when index16_state =>
3450
                                 -- advance pc
3451
             pc_ctrl    <= incr_pc;
3452
                                 -- fetch low byte
3453
             md_ctrl    <= fetch_next_md;
3454
             addr_ctrl  <= fetch_ad;
3455
                                 next_state <= index16_2_state;
3456
 
3457
                          -- ea = index register + md (16 bit offset)
3458
                          -- ea holds post byte
3459
                          when index16_2_state =>
3460
                                 case ea(6 downto 5) is
3461
                            when "00" =>
3462
                              left_ctrl  <= ix_left;
3463
                            when "01" =>
3464
                              left_ctrl  <= iy_left;
3465
                                 when "10" =>
3466
                              left_ctrl  <= up_left;
3467
                                 when others =>
3468
                                 -- when "11" =>
3469
                              left_ctrl  <= sp_left;
3470
                                 end case;
3471
                                 -- ea = index reg + md
3472
                            right_ctrl <= md_right;
3473
                            alu_ctrl   <= alu_add16;
3474
             ea_ctrl    <= load_ea;
3475
                                 -- return to previous state
3476
                            if ea(4) = '0' then
3477
                                         next_state   <= saved_state;
3478
                                 else
3479
                                         next_state   <= indirect_state;
3480
                                 end if;
3481
           --
3482
                          -- pc relative with 8 bit signed offest
3483
                          -- md holds signed offset
3484
                          --
3485
                          when pcrel8_state =>
3486
                                 -- ea = pc + signed md
3487
                            left_ctrl  <= pc_left;
3488
                            right_ctrl <= md_sign8_right;
3489
                            alu_ctrl   <= alu_add16;
3490
             ea_ctrl    <= load_ea;
3491
                                 -- return to previous state
3492
                            if ea(4) = '0' then
3493
                                         next_state   <= saved_state;
3494
                                 else
3495
                                         next_state   <= indirect_state;
3496
                                 end if;
3497
 
3498
                          -- pc relative addressing with 16 bit offset
3499
                          -- pick up the low byte of the offset in md
3500
                          -- advance the pc
3501
                          when pcrel16_state =>
3502
                                 -- advance pc
3503
             pc_ctrl    <= incr_pc;
3504
                                 -- fetch low byte
3505
             md_ctrl    <= fetch_next_md;
3506
             addr_ctrl  <= fetch_ad;
3507
                                 next_state <= pcrel16_2_state;
3508
 
3509
                          -- pc relative with16 bit signed offest
3510
                          -- md holds signed offset
3511
                          when pcrel16_2_state =>
3512
                                 -- ea = pc +  md
3513
                            left_ctrl  <= pc_left;
3514
                            right_ctrl <= md_right;
3515
                            alu_ctrl   <= alu_add16;
3516
             ea_ctrl    <= load_ea;
3517
                                 -- return to previous state
3518
                            if ea(4) = '0' then
3519
                                         next_state   <= saved_state;
3520
                                 else
3521
                                         next_state   <= indirect_state;
3522
                                 end if;
3523
 
3524
                          -- indexed to address
3525
                          -- pick up the low byte of the address
3526
                          -- advance the pc
3527
                          when indexaddr_state =>
3528
                                 -- advance pc
3529
             pc_ctrl    <= incr_pc;
3530
                                 -- fetch low byte
3531
             md_ctrl    <= fetch_next_md;
3532
             addr_ctrl  <= fetch_ad;
3533
                                 next_state <= indexaddr2_state;
3534
 
3535
                          -- indexed to absolute address
3536
                          -- md holds address
3537
                          -- ea hold indexing mode byte
3538
                          when indexaddr2_state =>
3539
                                 -- ea = md
3540
                            left_ctrl  <= pc_left;
3541
                            right_ctrl <= md_right;
3542
                            alu_ctrl   <= alu_ld16;
3543
             ea_ctrl    <= load_ea;
3544
                                 -- return to previous state
3545
                            if ea(4) = '0' then
3546
                                         next_state   <= saved_state;
3547
                                 else
3548
                                         next_state   <= indirect_state;
3549
                                 end if;
3550
 
3551
           --
3552
                          -- load md with high byte of indirect address
3553
                          -- pointed to by ea
3554
                          -- increment ea
3555
                          --
3556
                          when indirect_state =>
3557
                                 -- increment ea
3558
                            left_ctrl  <= ea_left;
3559
                            right_ctrl <= one_right;
3560
                            alu_ctrl   <= alu_add16;
3561
             ea_ctrl    <= load_ea;
3562
                                 -- fetch high byte
3563
             md_ctrl    <= fetch_first_md;
3564
             addr_ctrl  <= read_ad;
3565
                                 next_state <= indirect2_state;
3566
           --
3567
                          -- load md with low byte of indirect address
3568
                          -- pointed to by ea
3569
                          -- ea has previously been incremented
3570
                          --
3571
                          when indirect2_state =>
3572
                                 -- fetch high byte
3573
             md_ctrl    <= fetch_next_md;
3574
             addr_ctrl  <= read_ad;
3575
             dout_ctrl  <= md_lo_dout;
3576
                                 next_state <= indirect3_state;
3577
                          --
3578
                          -- complete idirect addressing
3579
                          -- by loading ea with md
3580
                          --
3581
                          when indirect3_state =>
3582
                                 -- load ea with md
3583
                            left_ctrl  <= ea_left;
3584
                            right_ctrl <= md_right;
3585
                            alu_ctrl   <= alu_ld16;
3586
             ea_ctrl    <= load_ea;
3587
                                 -- return to previous state
3588
                                 next_state   <= saved_state;
3589
 
3590
           --
3591
                          -- ea holds the low byte of the absolute address
3592
                          -- Move ea low byte into ea high byte
3593
                          -- load new ea low byte to for absolute 16 bit address
3594
                          -- advance the program counter
3595
                          --
3596
                          when extended_state => -- fetch ea low byte
3597
                                        -- increment pc
3598
               pc_ctrl      <= incr_pc;
3599
                                        -- fetch next effective address bytes
3600
                                        ea_ctrl      <= fetch_next_ea;
3601
               addr_ctrl    <= fetch_ad;
3602
                                   -- return to previous state
3603
                                   next_state   <= saved_state;
3604
 
3605
                                when lea_state => -- here on load effective address
3606
                                        -- load index register with effective address
3607
               left_ctrl  <= pc_left;
3608
                                        right_ctrl <= ea_right;
3609
                                   alu_ctrl   <= alu_lea;
3610
                                        case op_code(3 downto 0) is
3611
                                        when "0000" => -- leax
3612
                   cc_ctrl    <= load_cc;
3613
                   ix_ctrl    <= load_ix;
3614
                                        when "0001" => -- leay
3615
                   cc_ctrl    <= load_cc;
3616
                   iy_ctrl    <= load_iy;
3617
                                        when "0010" => -- leas
3618
                   sp_ctrl    <= load_sp;
3619
                                        when "0011" => -- leau
3620
                   up_ctrl    <= load_up;
3621
                                        when others =>
3622
                                            null;
3623
                                        end case;
3624
               lic          <= '1';
3625
               next_state   <= fetch_state;
3626
 
3627
                                --
3628
                                -- jump to subroutine
3629
                                -- sp=sp-1
3630
                                -- call push_return_lo_state to save pc
3631
                                -- return to jmp_state
3632
                                --
3633
                                when jsr_state =>
3634
                                        -- decrement sp
3635
               left_ctrl    <= sp_left;
3636
                                        right_ctrl   <= one_right;
3637
                                   alu_ctrl     <= alu_sub16;
3638
               sp_ctrl      <= load_sp;
3639
                                        -- call push_return_state
3640
                                        st_ctrl      <= push_st;
3641
                                        return_state <= jmp_state;
3642
               next_state   <= push_return_lo_state;
3643
 
3644
                                --
3645
                                -- Load pc with ea
3646
                                -- (JMP)
3647
                                --
3648
                                when jmp_state =>
3649
                                        -- load PC with effective address
3650
               left_ctrl  <= pc_left;
3651
                                        right_ctrl <= ea_right;
3652
                                   alu_ctrl   <= alu_ld16;
3653
                                        pc_ctrl    <= load_pc;
3654
               lic        <= '1';
3655
               next_state <= fetch_state;
3656
 
3657
                                --
3658
                                -- long branch or branch to subroutine
3659
                                -- pick up next md byte
3660
                                -- md_hi = md_lo
3661
                                -- md_lo = (pc)
3662
                                -- pc=pc+1
3663
                                -- if a lbsr push return address
3664
                                -- continue to sbranch_state
3665
                                -- to evaluate conditional branches
3666
                                --
3667
                                when lbranch_state =>
3668
                                        pc_ctrl    <= incr_pc;
3669
                                        -- fetch the next byte into md_lo
3670
               md_ctrl    <= fetch_next_md;
3671
               addr_ctrl  <= fetch_ad;
3672
                                        -- if lbsr - push return address
3673
                                        -- then continue on to short branch
3674
                                        if op_code = "00010111" then
3675
                                          st_ctrl      <= push_st;
3676
                                          return_state <= sbranch_state;
3677
                 next_state   <= push_return_lo_state;
3678
                                        else
3679
                 next_state   <= sbranch_state;
3680
                                        end if;
3681
 
3682
                                 --
3683
                                 -- here to execute conditional branch
3684
                                 -- short conditional branch md = signed 8 bit offset
3685
                                 -- long branch md = 16 bit offset
3686
                                 -- 
3687
                  when sbranch_state =>
3688
               left_ctrl  <= pc_left;
3689
                                        right_ctrl <= md_right;
3690
                                   alu_ctrl   <= alu_add16;
3691
                                        -- Test condition for branch
3692
                              if op_code(7 downto 4) = "0010" then -- conditional branch
3693
                 case op_code(3 downto 0) is
3694
                           when "0000" => -- bra
3695
                                            cond_true := (1 = 1);
3696
                           when "0001" => -- brn
3697
                                            cond_true := (1 = 0);
3698
                           when "0010" => -- bhi
3699
                                            cond_true := ((cc(CBIT) or cc(ZBIT)) = '0');
3700
                           when "0011" => -- bls
3701
                                            cond_true := ((cc(CBIT) or cc(ZBIT)) = '1');
3702
                           when "0100" => -- bcc/bhs
3703
                                            cond_true := (cc(CBIT) = '0');
3704
                           when "0101" => -- bcs/blo
3705
                                            cond_true := (cc(CBIT) = '1');
3706
                           when "0110" => -- bne
3707
                             cond_true := (cc(ZBIT) = '0');
3708
                           when "0111" => -- beq
3709
                                            cond_true := (cc(ZBIT) = '1');
3710
                           when "1000" => -- bvc
3711
                                            cond_true := (cc(VBIT) = '0');
3712
                           when "1001" => -- bvs
3713
                                            cond_true := (cc(VBIT) = '1');
3714
                           when "1010" => -- bpl
3715
                                            cond_true := (cc(NBIT) = '0');
3716
                           when "1011" => -- bmi
3717
                                            cond_true := (cc(NBIT) = '1');
3718
                           when "1100" => -- bge
3719
                                            cond_true := ((cc(NBIT) xor cc(VBIT)) = '0');
3720
                           when "1101" => -- blt
3721
                                            cond_true := ((cc(NBIT) xor cc(VBIT)) = '1');
3722
                           when "1110" => -- bgt
3723
                                            cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0');
3724
                           when "1111" => -- ble
3725
                                            cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1');
3726
                           when others =>
3727
                                            null;
3728
                           end case;
3729
                                   end if;
3730 130 dilbert57
                                        if cond_true then
3731 122 dilbert57
                                          pc_ctrl    <= load_pc;
3732
               end if;
3733
               lic          <= '1';
3734
                                        next_state   <= fetch_state;
3735
 
3736
                                 --
3737
                                 -- push return address onto the S stack
3738
                                 --
3739
                                 -- (sp) = pc_lo
3740
                                 -- sp = sp - 1
3741
                                 --
3742
                                 when push_return_lo_state =>
3743
                                          -- decrement the sp
3744
                 left_ctrl  <= sp_left;
3745
                 right_ctrl <= one_right;
3746
                 alu_ctrl   <= alu_sub16;
3747
                 sp_ctrl    <= load_sp;
3748
                 -- write PC low
3749
                 addr_ctrl  <= pushs_ad;
3750
                 dout_ctrl  <= pc_lo_dout;
3751
                 next_state <= push_return_hi_state;
3752
 
3753
                                --
3754
                                -- push program counter hi byte onto the stack
3755
                                -- (sp) = pc_hi
3756
                                -- sp = sp
3757
                                -- return to originating state
3758
                                --
3759
                                when push_return_hi_state =>
3760
                                          -- write pc hi bytes
3761
                 addr_ctrl    <= pushs_ad;
3762
                 dout_ctrl    <= pc_hi_dout;
3763
                 next_state   <= saved_state;
3764
 
3765 130 dilbert57
             --
3766
             -- RTS pull return address from stack
3767
             --
3768 122 dilbert57
                                 when pull_return_hi_state =>
3769
                                          -- increment the sp
3770
                 left_ctrl  <= sp_left;
3771
                 right_ctrl <= one_right;
3772
                 alu_ctrl   <= alu_add16;
3773
                 sp_ctrl    <= load_sp;
3774
                 -- read pc hi
3775
                                          pc_ctrl    <= pull_hi_pc;
3776
                 addr_ctrl  <= pulls_ad;
3777
                 next_state <= pull_return_lo_state;
3778
 
3779
                                when pull_return_lo_state =>
3780
                                          -- increment the SP
3781
                 left_ctrl  <= sp_left;
3782
                 right_ctrl <= one_right;
3783
                 alu_ctrl   <= alu_add16;
3784
                 sp_ctrl    <= load_sp;
3785
                                          -- read pc low
3786
                                          pc_ctrl    <= pull_lo_pc;
3787
                 addr_ctrl  <= pulls_ad;
3788
                 dout_ctrl  <= pc_lo_dout;
3789
                                          --
3790
                 lic          <= '1';
3791 130 dilbert57
                 next_state   <= fetch_state;
3792 122 dilbert57
 
3793
                                 when andcc_state =>
3794
                                          -- AND CC with md
3795
                 left_ctrl  <= md_left;
3796
                 right_ctrl <= zero_right;
3797
                 alu_ctrl   <= alu_andcc;
3798
                 cc_ctrl    <= load_cc;
3799
                                          --
3800
                 lic        <= '1';
3801 130 dilbert57
                                     next_state <= fetch_state;
3802 122 dilbert57
 
3803
                                 when orcc_state =>
3804
                                          -- OR CC with md
3805
                 left_ctrl  <= md_left;
3806
                 right_ctrl <= zero_right;
3807
                 alu_ctrl   <= alu_orcc;
3808
                 cc_ctrl    <= load_cc;
3809
                                          --
3810
                 lic        <= '1';
3811 130 dilbert57
                                     next_state <= fetch_state;
3812 122 dilbert57
 
3813
                                 when tfr_state =>
3814
                                          -- select source register
3815
                                          case md(7 downto 4) is
3816
                                          when "0000" =>
3817
                                            left_ctrl <= accd_left;
3818
                                          when "0001" =>
3819
                                            left_ctrl <= ix_left;
3820
                                          when "0010" =>
3821
                                            left_ctrl <= iy_left;
3822
                                          when "0011" =>
3823
                                            left_ctrl <= up_left;
3824
                                          when "0100" =>
3825
                                            left_ctrl <= sp_left;
3826
                                          when "0101" =>
3827
                                            left_ctrl <= pc_left;
3828
                                          when "1000" =>
3829
                                            left_ctrl <= acca_left;
3830
                                          when "1001" =>
3831
                                            left_ctrl <= accb_left;
3832
                                          when "1010" =>
3833
                                            left_ctrl <= cc_left;
3834
                                          when "1011" =>
3835
                                            left_ctrl <= dp_left;
3836
                                          when others =>
3837
                   left_ctrl  <= md_left;
3838
                                          end case;
3839
                 right_ctrl <= zero_right;
3840
                 alu_ctrl   <= alu_tfr;
3841
                                          -- select destination register
3842
                                          case md(3 downto 0) is
3843
                                          when "0000" => -- accd
3844
                   acca_ctrl  <= load_hi_acca;
3845
                   accb_ctrl  <= load_accb;
3846
                                          when "0001" => -- ix
3847
                   ix_ctrl    <= load_ix;
3848
                                          when "0010" => -- iy
3849
                   iy_ctrl    <= load_iy;
3850
                                          when "0011" => -- up
3851
                   up_ctrl    <= load_up;
3852
                                          when "0100" => -- sp
3853
                   sp_ctrl    <= load_sp;
3854
                                          when "0101" => -- pc
3855
                   pc_ctrl    <= load_pc;
3856
                                          when "1000" => -- acca
3857
                   acca_ctrl  <= load_acca;
3858
                                          when "1001" => -- accb
3859
                   accb_ctrl  <= load_accb;
3860
                                          when "1010" => -- cc
3861
                   cc_ctrl    <= load_cc;
3862
                                          when "1011" => --dp
3863
                   dp_ctrl    <= load_dp;
3864
                                          when others =>
3865
                                            null;
3866
                                          end case;
3867
                                          --
3868
                 lic          <= '1';
3869 130 dilbert57
                                     next_state   <= fetch_state;
3870 122 dilbert57
 
3871
                                 when exg_state =>
3872
                                          -- save destination register
3873
                                          case md(3 downto 0) is
3874
                                          when "0000" =>
3875
                                            left_ctrl <= accd_left;
3876
                                          when "0001" =>
3877
                                            left_ctrl <= ix_left;
3878
                                          when "0010" =>
3879
                                            left_ctrl <= iy_left;
3880
                                          when "0011" =>
3881
                                            left_ctrl <= up_left;
3882
                                          when "0100" =>
3883
                                            left_ctrl <= sp_left;
3884
                                          when "0101" =>
3885
                                            left_ctrl <= pc_left;
3886
                                          when "1000" =>
3887
                                            left_ctrl <= acca_left;
3888
                                          when "1001" =>
3889
                                            left_ctrl <= accb_left;
3890
                                          when "1010" =>
3891
                                            left_ctrl <= cc_left;
3892
                                          when "1011" =>
3893
                                            left_ctrl <= dp_left;
3894
                                          when others =>
3895
                   left_ctrl  <= md_left;
3896
                                          end case;
3897
                 right_ctrl <= zero_right;
3898
                 alu_ctrl   <= alu_tfr;
3899
                 ea_ctrl    <= load_ea;
3900
                                          -- call tranfer microcode
3901 130 dilbert57
                                     next_state   <= exg1_state;
3902 122 dilbert57
 
3903
                                 when exg1_state =>
3904 130 dilbert57
                                          -- select source register
3905
                                          case md(7 downto 4) is
3906
                                          when "0000" =>
3907
                                            left_ctrl <= accd_left;
3908
                                          when "0001" =>
3909
                                            left_ctrl <= ix_left;
3910
                                          when "0010" =>
3911
                                            left_ctrl <= iy_left;
3912
                                          when "0011" =>
3913
                                            left_ctrl <= up_left;
3914
                                          when "0100" =>
3915
                                            left_ctrl <= sp_left;
3916
                                          when "0101" =>
3917
                                            left_ctrl <= pc_left;
3918
                                          when "1000" =>
3919
                                            left_ctrl <= acca_left;
3920
                                          when "1001" =>
3921
                                            left_ctrl <= accb_left;
3922
                                          when "1010" =>
3923
                                            left_ctrl <= cc_left;
3924
                                          when "1011" =>
3925
                                            left_ctrl <= dp_left;
3926
                                          when others =>
3927
                   left_ctrl  <= md_left;
3928
                                          end case;
3929
                 right_ctrl <= zero_right;
3930
                 alu_ctrl   <= alu_tfr;
3931
                                          -- select destination register
3932
                                          case md(3 downto 0) is
3933
                                          when "0000" => -- accd
3934
                   acca_ctrl  <= load_hi_acca;
3935
                   accb_ctrl  <= load_accb;
3936
                                          when "0001" => -- ix
3937
                   ix_ctrl    <= load_ix;
3938
                                          when "0010" => -- iy
3939
                   iy_ctrl    <= load_iy;
3940
                                          when "0011" => -- up
3941
                   up_ctrl    <= load_up;
3942
                                          when "0100" => -- sp
3943
                   sp_ctrl    <= load_sp;
3944
                                          when "0101" => -- pc
3945
                   pc_ctrl    <= load_pc;
3946
                                          when "1000" => -- acca
3947
                   acca_ctrl  <= load_acca;
3948
                                          when "1001" => -- accb
3949
                   accb_ctrl  <= load_accb;
3950
                                          when "1010" => -- cc
3951
                   cc_ctrl    <= load_cc;
3952
                                          when "1011" => --dp
3953
                   dp_ctrl    <= load_dp;
3954
                                          when others =>
3955
                                            null;
3956
                                          end case;
3957
                                     next_state   <= exg2_state;
3958
 
3959
                                 when exg2_state =>
3960 122 dilbert57
                                          -- restore destination
3961
                 left_ctrl  <= ea_left;
3962
                 right_ctrl <= zero_right;
3963
                 alu_ctrl   <= alu_tfr;
3964
                                          -- save as source register
3965
                                          case md(7 downto 4) is
3966
                                          when "0000" => -- accd
3967
                   acca_ctrl  <= load_hi_acca;
3968
                   accb_ctrl  <= load_accb;
3969
                                          when "0001" => -- ix
3970
                   ix_ctrl    <= load_ix;
3971
                                          when "0010" => -- iy
3972
                   iy_ctrl    <= load_iy;
3973
                                          when "0011" => -- up
3974
                   up_ctrl    <= load_up;
3975
                                          when "0100" => -- sp
3976
                   sp_ctrl    <= load_sp;
3977
                                          when "0101" => -- pc
3978
                   pc_ctrl    <= load_pc;
3979
                                          when "1000" => -- acca
3980
                   acca_ctrl  <= load_acca;
3981
                                          when "1001" => -- accb
3982
                   accb_ctrl  <= load_accb;
3983
                                          when "1010" => -- cc
3984
                   cc_ctrl    <= load_cc;
3985
                                          when "1011" => --dp
3986
                   dp_ctrl    <= load_dp;
3987
                                          when others =>
3988
                                            null;
3989
                                          end case;
3990
                 lic          <= '1';
3991
                                     next_state   <= fetch_state;
3992
 
3993
                                 when mul_state =>
3994
                                          -- move acca to md
3995
                 left_ctrl  <= acca_left;
3996
                 right_ctrl <= zero_right;
3997
                 alu_ctrl   <= alu_st16;
3998
                 md_ctrl    <= load_md;
3999
                                     next_state <= mulea_state;
4000
 
4001
                                 when mulea_state =>
4002
                                          -- move accb to ea
4003
                 left_ctrl  <= accb_left;
4004
                 right_ctrl <= zero_right;
4005
                 alu_ctrl   <= alu_st16;
4006
                 ea_ctrl    <= load_ea;
4007
                                     next_state <= muld_state;
4008
 
4009
                                 when muld_state =>
4010
                                          -- clear accd
4011
                 left_ctrl  <= acca_left;
4012
                 right_ctrl <= zero_right;
4013
                 alu_ctrl   <= alu_ld8;
4014
                 acca_ctrl  <= load_hi_acca;
4015
                 accb_ctrl  <= load_accb;
4016
                                     next_state <= mul0_state;
4017
 
4018
                                 when mul0_state =>
4019
                                          -- if bit 0 of ea set, add accd to md
4020
                 left_ctrl  <= accd_left;
4021
                                          if ea(0) = '1' then
4022
                   right_ctrl <= md_right;
4023
                                          else
4024
                   right_ctrl <= zero_right;
4025
                                          end if;
4026
                 alu_ctrl   <= alu_mul;
4027
                 cc_ctrl    <= load_cc;
4028
                 acca_ctrl  <= load_hi_acca;
4029
                 accb_ctrl  <= load_accb;
4030
                 md_ctrl    <= shiftl_md;
4031
                                     next_state <= mul1_state;
4032
 
4033
                                 when mul1_state =>
4034
                                          -- if bit 1 of ea set, add accd to md
4035
                 left_ctrl  <= accd_left;
4036
                                          if ea(1) = '1' then
4037
                   right_ctrl <= md_right;
4038
                                          else
4039
                   right_ctrl <= zero_right;
4040
                                          end if;
4041
                 alu_ctrl   <= alu_mul;
4042
                 cc_ctrl    <= load_cc;
4043
                 acca_ctrl  <= load_hi_acca;
4044
                 accb_ctrl  <= load_accb;
4045
                 md_ctrl    <= shiftl_md;
4046
                                     next_state <= mul2_state;
4047
 
4048
                                 when mul2_state =>
4049
                                          -- if bit 2 of ea set, add accd to md
4050
                 left_ctrl  <= accd_left;
4051
                                          if ea(2) = '1' then
4052
                   right_ctrl <= md_right;
4053
                                          else
4054
                   right_ctrl <= zero_right;
4055
                                          end if;
4056
                 alu_ctrl   <= alu_mul;
4057
                 cc_ctrl    <= load_cc;
4058
                 acca_ctrl  <= load_hi_acca;
4059
                 accb_ctrl  <= load_accb;
4060
                 md_ctrl    <= shiftl_md;
4061
                                     next_state <= mul3_state;
4062
 
4063
                                 when mul3_state =>
4064
                                          -- if bit 3 of ea set, add accd to md
4065
                 left_ctrl  <= accd_left;
4066
                                          if ea(3) = '1' then
4067
                   right_ctrl <= md_right;
4068
                                          else
4069
                   right_ctrl <= zero_right;
4070
                                          end if;
4071
                 alu_ctrl   <= alu_mul;
4072
                 cc_ctrl    <= load_cc;
4073
                 acca_ctrl  <= load_hi_acca;
4074
                 accb_ctrl  <= load_accb;
4075
                 md_ctrl    <= shiftl_md;
4076
                                     next_state <= mul4_state;
4077
 
4078
                                 when mul4_state =>
4079
                                          -- if bit 4 of ea set, add accd to md
4080
                 left_ctrl  <= accd_left;
4081
                                          if ea(4) = '1' then
4082
                   right_ctrl <= md_right;
4083
                                          else
4084
                   right_ctrl <= zero_right;
4085
                                          end if;
4086
                 alu_ctrl   <= alu_mul;
4087
                 cc_ctrl    <= load_cc;
4088
                 acca_ctrl  <= load_hi_acca;
4089
                 accb_ctrl  <= load_accb;
4090
                 md_ctrl    <= shiftl_md;
4091
                                     next_state <= mul5_state;
4092
 
4093
                                 when mul5_state =>
4094
                                          -- if bit 5 of ea set, add accd to md
4095
                 left_ctrl  <= accd_left;
4096
                                          if ea(5) = '1' then
4097
                   right_ctrl <= md_right;
4098
                                          else
4099
                   right_ctrl <= zero_right;
4100
                                          end if;
4101
                 alu_ctrl   <= alu_mul;
4102
                 cc_ctrl    <= load_cc;
4103
                 acca_ctrl  <= load_hi_acca;
4104
                 accb_ctrl  <= load_accb;
4105
                 md_ctrl    <= shiftl_md;
4106
                                     next_state <= mul6_state;
4107
 
4108
                                 when mul6_state =>
4109
                                          -- if bit 6 of ea set, add accd to md
4110
                 left_ctrl  <= accd_left;
4111
                                          if ea(6) = '1' then
4112
                   right_ctrl <= md_right;
4113
                                          else
4114
                   right_ctrl <= zero_right;
4115
                                          end if;
4116
                 alu_ctrl   <= alu_mul;
4117
                 cc_ctrl    <= load_cc;
4118
                 acca_ctrl  <= load_hi_acca;
4119
                 accb_ctrl  <= load_accb;
4120
                 md_ctrl    <= shiftl_md;
4121
                                     next_state <= mul7_state;
4122
 
4123
                                 when mul7_state =>
4124
                                          -- if bit 7 of ea set, add accd to md
4125
                 left_ctrl  <= accd_left;
4126
                                          if ea(7) = '1' then
4127
                   right_ctrl <= md_right;
4128
                                          else
4129
                   right_ctrl <= zero_right;
4130
                                          end if;
4131
                 alu_ctrl   <= alu_mul;
4132
                 cc_ctrl    <= load_cc;
4133
                 acca_ctrl  <= load_hi_acca;
4134
                 accb_ctrl  <= load_accb;
4135
                 md_ctrl    <= shiftl_md;
4136
                 lic          <= '1';
4137
                                     next_state <= fetch_state;
4138
 
4139
                          --
4140
                          -- Enter here on pushs
4141
                          -- ea holds post byte
4142
                          --
4143
                          when pshs_state =>
4144
             -- decrement sp if any registers to be pushed
4145
             left_ctrl  <= sp_left;
4146
             right_ctrl <= one_right;
4147
             alu_ctrl   <= alu_sub16;
4148
                                 -- idle        address
4149
             addr_ctrl  <= idle_ad;
4150
                            dout_ctrl  <= cc_dout;
4151
                                 if ea(7 downto 0) = "00000000" then
4152
               sp_ctrl    <= latch_sp;
4153
                                 else
4154
               sp_ctrl    <= load_sp;
4155
                                 end if;
4156
                                 if ea(7) = '1' then
4157
               next_state <= pshs_pcl_state;
4158
                                 elsif ea(6) = '1' then
4159
               next_state <= pshs_upl_state;
4160
                                 elsif ea(5) = '1' then
4161
                                   next_state <= pshs_iyl_state;
4162
                                 elsif ea(4) = '1' then
4163
                                   next_state <= pshs_ixl_state;
4164
                                 elsif ea(3) = '1' then
4165
                                   next_state <= pshs_dp_state;
4166
                                 elsif ea(2) = '1' then
4167
                                   next_state <= pshs_accb_state;
4168
                                 elsif ea(1) = '1' then
4169
                                   next_state <= pshs_acca_state;
4170
                                 elsif ea(0) = '1' then
4171
                                   next_state <= pshs_cc_state;
4172
                                 else
4173
               lic        <= '1';
4174
                                   next_state <= fetch_state;
4175
                                 end if;
4176
 
4177
                          when pshs_pcl_state =>
4178
             -- decrement sp
4179
             left_ctrl  <= sp_left;
4180
             right_ctrl <= one_right;
4181
             alu_ctrl   <= alu_sub16;
4182
             sp_ctrl    <= load_sp;
4183
                                 -- write pc low
4184
             addr_ctrl  <= pushs_ad;
4185
                            dout_ctrl  <= pc_lo_dout;
4186
             next_state <= pshs_pch_state;
4187
 
4188
                          when pshs_pch_state =>
4189
             -- decrement sp
4190
             left_ctrl  <= sp_left;
4191
             right_ctrl <= one_right;
4192
             alu_ctrl   <= alu_sub16;
4193
                                 if ea(6 downto 0) = "0000000" then
4194
               sp_ctrl    <= latch_sp;
4195
                                 else
4196
               sp_ctrl    <= load_sp;
4197
                                 end if;
4198
                                 -- write pc hi
4199
             addr_ctrl  <= pushs_ad;
4200
                            dout_ctrl  <= pc_hi_dout;
4201
                                 if ea(6) = '1' then
4202
               next_state <= pshs_upl_state;
4203
                                 elsif ea(5) = '1' then
4204
                                   next_state <= pshs_iyl_state;
4205
                                 elsif ea(4) = '1' then
4206
                                   next_state <= pshs_ixl_state;
4207
                                 elsif ea(3) = '1' then
4208
                                   next_state <= pshs_dp_state;
4209
                                 elsif ea(2) = '1' then
4210
                                   next_state <= pshs_accb_state;
4211
                                 elsif ea(1) = '1' then
4212
                                   next_state <= pshs_acca_state;
4213
                                 elsif ea(0) = '1' then
4214
                                   next_state <= pshs_cc_state;
4215
                                 else
4216
               lic        <= '1';
4217
                                   next_state <= fetch_state;
4218
                                 end if;
4219
 
4220
 
4221
                          when pshs_upl_state =>
4222
             -- decrement sp
4223
             left_ctrl  <= sp_left;
4224
             right_ctrl <= one_right;
4225
             alu_ctrl   <= alu_sub16;
4226
             sp_ctrl    <= load_sp;
4227
                                 -- write pc low
4228
             addr_ctrl  <= pushs_ad;
4229
                            dout_ctrl  <= up_lo_dout;
4230
             next_state <= pshs_uph_state;
4231
 
4232
                          when pshs_uph_state =>
4233
             -- decrement sp
4234
             left_ctrl  <= sp_left;
4235
             right_ctrl <= one_right;
4236
             alu_ctrl   <= alu_sub16;
4237
                                 if ea(5 downto 0) = "000000" then
4238
               sp_ctrl    <= latch_sp;
4239
                                 else
4240
               sp_ctrl    <= load_sp;
4241
                                 end if;
4242
                                 -- write pc hi
4243
             addr_ctrl  <= pushs_ad;
4244
                            dout_ctrl  <= up_hi_dout;
4245
                                 if ea(5) = '1' then
4246
                                   next_state   <= pshs_iyl_state;
4247
                                 elsif ea(4) = '1' then
4248
                                   next_state   <= pshs_ixl_state;
4249
                                 elsif ea(3) = '1' then
4250
                                   next_state   <= pshs_dp_state;
4251
                                 elsif ea(2) = '1' then
4252
                                   next_state   <= pshs_accb_state;
4253
                                 elsif ea(1) = '1' then
4254
                                   next_state   <= pshs_acca_state;
4255
                                 elsif ea(0) = '1' then
4256
                                   next_state   <= pshs_cc_state;
4257
                                 else
4258
               lic          <= '1';
4259
                                   next_state   <= fetch_state;
4260
                                 end if;
4261
 
4262
                          when pshs_iyl_state =>
4263
             -- decrement sp
4264
             left_ctrl  <= sp_left;
4265
             right_ctrl <= one_right;
4266
             alu_ctrl   <= alu_sub16;
4267
             sp_ctrl    <= load_sp;
4268
                                 -- write iy low
4269
             addr_ctrl  <= pushs_ad;
4270
                            dout_ctrl  <= iy_lo_dout;
4271
             next_state <= pshs_iyh_state;
4272
 
4273
                          when pshs_iyh_state =>
4274
             -- decrement sp
4275
             left_ctrl  <= sp_left;
4276
             right_ctrl <= one_right;
4277
             alu_ctrl   <= alu_sub16;
4278
                                 if ea(4 downto 0) = "00000" then
4279
               sp_ctrl    <= latch_sp;
4280
                                 else
4281
               sp_ctrl    <= load_sp;
4282
                                 end if;
4283
                                 -- write iy hi
4284
             addr_ctrl  <= pushs_ad;
4285
                            dout_ctrl  <= iy_hi_dout;
4286
                                 if ea(4) = '1' then
4287
                                   next_state   <= pshs_ixl_state;
4288
                                 elsif ea(3) = '1' then
4289
                                   next_state   <= pshs_dp_state;
4290
                                 elsif ea(2) = '1' then
4291
                                   next_state   <= pshs_accb_state;
4292
                                 elsif ea(1) = '1' then
4293
                                   next_state   <= pshs_acca_state;
4294
                                 elsif ea(0) = '1' then
4295
                                   next_state   <= pshs_cc_state;
4296
                                 else
4297
               lic          <= '1';
4298
                                   next_state   <= fetch_state;
4299
                                 end if;
4300
 
4301
                          when pshs_ixl_state =>
4302
             -- decrement sp
4303
             left_ctrl  <= sp_left;
4304
             right_ctrl <= one_right;
4305
             alu_ctrl   <= alu_sub16;
4306
             sp_ctrl    <= load_sp;
4307
                                 -- write ix low
4308
             addr_ctrl  <= pushs_ad;
4309
                            dout_ctrl  <= ix_lo_dout;
4310
             next_state <= pshs_ixh_state;
4311
 
4312
                          when pshs_ixh_state =>
4313
             -- decrement sp
4314
             left_ctrl  <= sp_left;
4315
             right_ctrl <= one_right;
4316
             alu_ctrl   <= alu_sub16;
4317
                                 if ea(3 downto 0) = "0000" then
4318
               sp_ctrl    <= latch_sp;
4319
                                 else
4320
               sp_ctrl    <= load_sp;
4321
                                 end if;
4322
                                 -- write ix hi
4323
             addr_ctrl  <= pushs_ad;
4324
                            dout_ctrl  <= ix_hi_dout;
4325
                                 if ea(3) = '1' then
4326
                                   next_state   <= pshs_dp_state;
4327
                                 elsif ea(2) = '1' then
4328
                                   next_state   <= pshs_accb_state;
4329
                                 elsif ea(1) = '1' then
4330
                                   next_state   <= pshs_acca_state;
4331
                                 elsif ea(0) = '1' then
4332
                                   next_state   <= pshs_cc_state;
4333
                                 else
4334
               lic          <= '1';
4335
                                   next_state   <= fetch_state;
4336
                                 end if;
4337
 
4338
                          when pshs_dp_state =>
4339
             -- decrement sp
4340
             left_ctrl  <= sp_left;
4341
             right_ctrl <= one_right;
4342
             alu_ctrl   <= alu_sub16;
4343
                                 if ea(2 downto 0) = "000" then
4344
               sp_ctrl    <= latch_sp;
4345
                                 else
4346
               sp_ctrl    <= load_sp;
4347
                                 end if;
4348
                                 -- write dp
4349
             addr_ctrl  <= pushs_ad;
4350
                            dout_ctrl  <= dp_dout;
4351
                                 if ea(2) = '1' then
4352
                                   next_state   <= pshs_accb_state;
4353
                                 elsif ea(1) = '1' then
4354
                                   next_state   <= pshs_acca_state;
4355
                                 elsif ea(0) = '1' then
4356
                                   next_state   <= pshs_cc_state;
4357
                                 else
4358
               lic          <= '1';
4359
                                   next_state   <= fetch_state;
4360
                                 end if;
4361
 
4362
                          when pshs_accb_state =>
4363
             -- decrement sp
4364
             left_ctrl  <= sp_left;
4365
             right_ctrl <= one_right;
4366
             alu_ctrl   <= alu_sub16;
4367
                                 if ea(1 downto 0) = "00" then
4368
               sp_ctrl    <= latch_sp;
4369
                                 else
4370
               sp_ctrl    <= load_sp;
4371
                                 end if;
4372
                                 -- write accb
4373
             addr_ctrl  <= pushs_ad;
4374
                            dout_ctrl  <= accb_dout;
4375
                                 if ea(1) = '1' then
4376
                                   next_state   <= pshs_acca_state;
4377
                                 elsif ea(0) = '1' then
4378
                                   next_state   <= pshs_cc_state;
4379
                                 else
4380
               lic          <= '1';
4381
                                   next_state   <= fetch_state;
4382
                                 end if;
4383
 
4384
                          when pshs_acca_state =>
4385
             -- decrement sp
4386
             left_ctrl  <= sp_left;
4387
             right_ctrl <= one_right;
4388
             alu_ctrl   <= alu_sub16;
4389
                                 if ea(0) = '1' then
4390
               sp_ctrl    <= load_sp;
4391
                                 else
4392
               sp_ctrl    <= latch_sp;
4393
                                 end if;
4394
                                 -- write acca
4395
             addr_ctrl  <= pushs_ad;
4396
                            dout_ctrl  <= acca_dout;
4397
                                 if ea(0) = '1' then
4398
                                   next_state   <= pshs_cc_state;
4399
                                 else
4400
               lic          <= '1';
4401
                                   next_state   <= fetch_state;
4402
                                 end if;
4403
 
4404
                          when pshs_cc_state =>
4405
             -- idle sp
4406
                                 -- write cc
4407
             addr_ctrl  <= pushs_ad;
4408
                            dout_ctrl  <= cc_dout;
4409
             lic          <= '1';
4410
             next_state <= fetch_state;
4411
 
4412
                          --
4413
                          -- enter here on PULS
4414
                          -- ea hold register mask
4415
                          --
4416
                          when puls_state =>
4417
                                 if ea(0) = '1' then
4418
                                   next_state <= puls_cc_state;
4419
                                 elsif ea(1) = '1' then
4420
                                   next_state <= puls_acca_state;
4421
                                 elsif ea(2) = '1' then
4422
                                   next_state <= puls_accb_state;
4423
                                 elsif ea(3) = '1' then
4424
                                   next_state <= puls_dp_state;
4425
                                 elsif ea(4) = '1' then
4426
                                   next_state <= puls_ixh_state;
4427
                                 elsif ea(5) = '1' then
4428
                                   next_state <= puls_iyh_state;
4429
                                 elsif ea(6) = '1' then
4430
               next_state <= puls_uph_state;
4431
                                 elsif ea(7) = '1' then
4432
               next_state <= puls_pch_state;
4433
                                 else
4434
               lic        <= '1';
4435
                                   next_state <= fetch_state;
4436
                                 end if;
4437
 
4438
                          when puls_cc_state =>
4439
                                 -- increment sp
4440
             left_ctrl  <= sp_left;
4441
             right_ctrl <= one_right;
4442
             alu_ctrl   <= alu_add16;
4443
             sp_ctrl    <= load_sp;
4444
                                 -- read cc
4445
             cc_ctrl    <= pull_cc;
4446
             addr_ctrl  <= pulls_ad;
4447
                                 if ea(1) = '1' then
4448
                                   next_state <= puls_acca_state;
4449
                                 elsif ea(2) = '1' then
4450
                                   next_state <= puls_accb_state;
4451
                                 elsif ea(3) = '1' then
4452
                                   next_state <= puls_dp_state;
4453
                                 elsif ea(4) = '1' then
4454
                                   next_state <= puls_ixh_state;
4455
                                 elsif ea(5) = '1' then
4456
                                   next_state <= puls_iyh_state;
4457
                                 elsif ea(6) = '1' then
4458
               next_state <= puls_uph_state;
4459
                                 elsif ea(7) = '1' then
4460
               next_state <= puls_pch_state;
4461
                                 else
4462
               lic        <= '1';
4463
                                   next_state <= fetch_state;
4464
                                 end if;
4465
 
4466
                          when puls_acca_state =>
4467
                                 -- increment sp
4468
             left_ctrl  <= sp_left;
4469
             right_ctrl <= one_right;
4470
             alu_ctrl   <= alu_add16;
4471
             sp_ctrl    <= load_sp;
4472
                                 -- read acca
4473
                                 acca_ctrl  <= pull_acca;
4474
             addr_ctrl  <= pulls_ad;
4475
                                 if ea(2) = '1' then
4476
                                   next_state <= puls_accb_state;
4477
                                 elsif ea(3) = '1' then
4478
                                   next_state <= puls_dp_state;
4479
                                 elsif ea(4) = '1' then
4480
                                   next_state <= puls_ixh_state;
4481
                                 elsif ea(5) = '1' then
4482
                                   next_state <= puls_iyh_state;
4483
                                 elsif ea(6) = '1' then
4484
               next_state <= puls_uph_state;
4485
                                 elsif ea(7) = '1' then
4486
               next_state <= puls_pch_state;
4487
                                 else
4488
               lic          <= '1';
4489
                                   next_state <= fetch_state;
4490
                                 end if;
4491
 
4492
                          when puls_accb_state =>
4493
                                 -- increment sp
4494
             left_ctrl  <= sp_left;
4495
             right_ctrl <= one_right;
4496
             alu_ctrl   <= alu_add16;
4497
             sp_ctrl    <= load_sp;
4498
                                 -- read accb
4499
                                 accb_ctrl  <= pull_accb;
4500
             addr_ctrl  <= pulls_ad;
4501
                                 if ea(3) = '1' then
4502
                                   next_state <= puls_dp_state;
4503
                                 elsif ea(4) = '1' then
4504
                                   next_state <= puls_ixh_state;
4505
                                 elsif ea(5) = '1' then
4506
                                   next_state <= puls_iyh_state;
4507
                                 elsif ea(6) = '1' then
4508
               next_state <= puls_uph_state;
4509
                                 elsif ea(7) = '1' then
4510
               next_state <= puls_pch_state;
4511
                                 else
4512
               lic        <= '1';
4513
                                   next_state <= fetch_state;
4514
                                 end if;
4515
 
4516
                          when puls_dp_state =>
4517
                                 -- increment sp
4518
             left_ctrl  <= sp_left;
4519
             right_ctrl <= one_right;
4520
             alu_ctrl   <= alu_add16;
4521
             sp_ctrl    <= load_sp;
4522
                                 -- read dp
4523
                                 dp_ctrl    <= pull_dp;
4524
             addr_ctrl  <= pulls_ad;
4525
                                 if ea(4) = '1' then
4526
                                   next_state <= puls_ixh_state;
4527
                                 elsif ea(5) = '1' then
4528
                                   next_state <= puls_iyh_state;
4529
                                 elsif ea(6) = '1' then
4530
               next_state <= puls_uph_state;
4531
                                 elsif ea(7) = '1' then
4532
               next_state <= puls_pch_state;
4533
                                 else
4534
               lic        <= '1';
4535
                                   next_state <= fetch_state;
4536
                                 end if;
4537
 
4538
                          when puls_ixh_state =>
4539
             -- increment sp
4540
             left_ctrl  <= sp_left;
4541
             right_ctrl <= one_right;
4542
             alu_ctrl   <= alu_add16;
4543
             sp_ctrl    <= load_sp;
4544
                                 -- pull ix hi
4545
                                 ix_ctrl    <= pull_hi_ix;
4546
             addr_ctrl  <= pulls_ad;
4547
             next_state <= puls_ixl_state;
4548
 
4549
                          when puls_ixl_state =>
4550
                                 -- increment sp
4551
             left_ctrl  <= sp_left;
4552
             right_ctrl <= one_right;
4553
             alu_ctrl   <= alu_add16;
4554
             sp_ctrl    <= load_sp;
4555
                                 -- read ix low
4556
                                 ix_ctrl    <= pull_lo_ix;
4557
             addr_ctrl  <= pulls_ad;
4558
                                 if ea(5) = '1' then
4559
                                   next_state <= puls_iyh_state;
4560
                                 elsif ea(6) = '1' then
4561
               next_state <= puls_uph_state;
4562
                                 elsif ea(7) = '1' then
4563
               next_state <= puls_pch_state;
4564
                                 else
4565
               lic        <= '1';
4566
                                   next_state <= fetch_state;
4567
                                 end if;
4568
 
4569
                          when puls_iyh_state =>
4570
             -- increment sp
4571
             left_ctrl  <= sp_left;
4572
             right_ctrl <= one_right;
4573
             alu_ctrl   <= alu_add16;
4574
             sp_ctrl    <= load_sp;
4575
                                 -- pull iy hi
4576
                                 iy_ctrl    <= pull_hi_iy;
4577
             addr_ctrl  <= pulls_ad;
4578
             next_state   <= puls_iyl_state;
4579
 
4580
                          when puls_iyl_state =>
4581
             -- increment sp
4582
             left_ctrl  <= sp_left;
4583
             right_ctrl <= one_right;
4584
             alu_ctrl   <= alu_add16;
4585
             sp_ctrl    <= load_sp;
4586
                                 -- read iy low
4587
                                 iy_ctrl    <= pull_lo_iy;
4588
             addr_ctrl  <= pulls_ad;
4589
                                 if ea(6) = '1' then
4590
               next_state <= puls_uph_state;
4591
                                 elsif ea(7) = '1' then
4592
               next_state <= puls_pch_state;
4593
                                 else
4594
               lic        <= '1';
4595
                                   next_state <= fetch_state;
4596
                                 end if;
4597
 
4598
                          when puls_uph_state =>
4599
             -- increment sp
4600
             left_ctrl  <= sp_left;
4601
             right_ctrl <= one_right;
4602
             alu_ctrl   <= alu_add16;
4603
             sp_ctrl    <= load_sp;
4604
                                 -- pull up hi
4605
                                 up_ctrl    <= pull_hi_up;
4606
             addr_ctrl  <= pulls_ad;
4607
             next_state <= puls_upl_state;
4608
 
4609
                          when puls_upl_state =>
4610
                                 -- increment sp
4611
             left_ctrl  <= sp_left;
4612
             right_ctrl <= one_right;
4613
             alu_ctrl   <= alu_add16;
4614
             sp_ctrl    <= load_sp;
4615
                                 -- read up low
4616
                                 up_ctrl    <= pull_lo_up;
4617
             addr_ctrl  <= pulls_ad;
4618
                                 if ea(7) = '1' then
4619
               next_state <= puls_pch_state;
4620
                                 else
4621
               lic        <= '1';
4622
                                   next_state <= fetch_state;
4623
                                 end if;
4624
 
4625
                          when puls_pch_state =>
4626
             -- increment sp
4627
             left_ctrl  <= sp_left;
4628
             right_ctrl <= one_right;
4629
             alu_ctrl   <= alu_add16;
4630
             sp_ctrl    <= load_sp;
4631
                                 -- pull pc hi
4632
                                 pc_ctrl    <= pull_hi_pc;
4633
             addr_ctrl  <= pulls_ad;
4634
             next_state <= puls_pcl_state;
4635
 
4636
                          when puls_pcl_state =>
4637
                                 -- increment sp
4638
             left_ctrl  <= sp_left;
4639
             right_ctrl <= one_right;
4640
             alu_ctrl   <= alu_add16;
4641
             sp_ctrl    <= load_sp;
4642
                                 -- read pc low
4643
                                 pc_ctrl    <= pull_lo_pc;
4644
             addr_ctrl  <= pulls_ad;
4645
             lic        <= '1';
4646
             next_state <= fetch_state;
4647
 
4648
                          --
4649
                          -- Enter here on pshu
4650
                          -- ea holds post byte
4651
                          --
4652
                          when pshu_state =>
4653
             -- decrement up if any registers to be pushed
4654
             left_ctrl  <= up_left;
4655
             right_ctrl <= one_right;
4656
             alu_ctrl   <= alu_sub16;
4657
                                 if ea(7 downto 0) = "00000000" then
4658
               up_ctrl    <= latch_up;
4659
                                 else
4660
               up_ctrl    <= load_up;
4661
                                 end if;
4662
                                 -- write idle bus
4663
                                 if ea(7) = '1' then
4664
               next_state   <= pshu_pcl_state;
4665
                                 elsif ea(6) = '1' then
4666
               next_state   <= pshu_spl_state;
4667
                                 elsif ea(5) = '1' then
4668
                                   next_state   <= pshu_iyl_state;
4669
                                 elsif ea(4) = '1' then
4670
                                   next_state   <= pshu_ixl_state;
4671
                                 elsif ea(3) = '1' then
4672
                                   next_state   <= pshu_dp_state;
4673
                                 elsif ea(2) = '1' then
4674
                                   next_state   <= pshu_accb_state;
4675
                                 elsif ea(1) = '1' then
4676
                                   next_state   <= pshu_acca_state;
4677
                                 elsif ea(0) = '1' then
4678
                                   next_state   <= pshu_cc_state;
4679
                                 else
4680
               lic          <= '1';
4681
                                   next_state   <= fetch_state;
4682
                                 end if;
4683
                          --
4684
                          -- push PC onto U stack
4685
                          --
4686
                          when pshu_pcl_state =>
4687
             -- decrement up
4688
             left_ctrl  <= up_left;
4689
             right_ctrl <= one_right;
4690
             alu_ctrl   <= alu_sub16;
4691
             up_ctrl    <= load_up;
4692
                                 -- write pc low
4693
             addr_ctrl  <= pushu_ad;
4694
                            dout_ctrl  <= pc_lo_dout;
4695
             next_state <= pshu_pch_state;
4696
 
4697
                          when pshu_pch_state =>
4698
             -- decrement up
4699
             left_ctrl  <= up_left;
4700
             right_ctrl <= one_right;
4701
             alu_ctrl   <= alu_sub16;
4702
                                 if ea(6 downto 0) = "0000000" then
4703
               up_ctrl    <= latch_up;
4704
                                 else
4705
               up_ctrl    <= load_up;
4706
                                 end if;
4707
                                 -- write pc hi
4708
             addr_ctrl  <= pushu_ad;
4709
                            dout_ctrl  <= pc_hi_dout;
4710
                                 if ea(6) = '1' then
4711
               next_state   <= pshu_spl_state;
4712
                                 elsif ea(5) = '1' then
4713
                                   next_state   <= pshu_iyl_state;
4714
                                 elsif ea(4) = '1' then
4715
                                   next_state   <= pshu_ixl_state;
4716
                                 elsif ea(3) = '1' then
4717
                                   next_state   <= pshu_dp_state;
4718
                                 elsif ea(2) = '1' then
4719
                                   next_state   <= pshu_accb_state;
4720
                                 elsif ea(1) = '1' then
4721
                                   next_state   <= pshu_acca_state;
4722
                                 elsif ea(0) = '1' then
4723
                                   next_state   <= pshu_cc_state;
4724
                                 else
4725
               lic          <= '1';
4726
                                   next_state   <= fetch_state;
4727
                                 end if;
4728
 
4729
                          when pshu_spl_state =>
4730
             -- decrement up
4731
             left_ctrl  <= up_left;
4732
             right_ctrl <= one_right;
4733
             alu_ctrl   <= alu_sub16;
4734
             up_ctrl    <= load_up;
4735
                                 -- write sp low
4736
             addr_ctrl  <= pushu_ad;
4737
                            dout_ctrl  <= sp_lo_dout;
4738
             next_state <= pshu_sph_state;
4739
 
4740
                          when pshu_sph_state =>
4741
             -- decrement up
4742
             left_ctrl  <= up_left;
4743
             right_ctrl <= one_right;
4744
             alu_ctrl   <= alu_sub16;
4745
                                 if ea(5 downto 0) = "000000" then
4746
               up_ctrl    <= latch_up;
4747
                                 else
4748
               up_ctrl    <= load_up;
4749
                                 end if;
4750
                                 -- write sp hi
4751
             addr_ctrl  <= pushu_ad;
4752
                            dout_ctrl  <= sp_hi_dout;
4753
                                 if ea(5) = '1' then
4754
                                   next_state   <= pshu_iyl_state;
4755
                                 elsif ea(4) = '1' then
4756
                                   next_state   <= pshu_ixl_state;
4757
                                 elsif ea(3) = '1' then
4758
                                   next_state   <= pshu_dp_state;
4759
                                 elsif ea(2) = '1' then
4760
                                   next_state   <= pshu_accb_state;
4761
                                 elsif ea(1) = '1' then
4762
                                   next_state   <= pshu_acca_state;
4763
                                 elsif ea(0) = '1' then
4764
                                   next_state   <= pshu_cc_state;
4765
                                 else
4766
               lic          <= '1';
4767
                                   next_state   <= fetch_state;
4768
                                 end if;
4769
 
4770
                          when pshu_iyl_state =>
4771
             -- decrement up
4772
             left_ctrl  <= up_left;
4773
             right_ctrl <= one_right;
4774
             alu_ctrl   <= alu_sub16;
4775
             up_ctrl    <= load_up;
4776
                                 -- write iy low
4777
             addr_ctrl  <= pushu_ad;
4778
                            dout_ctrl  <= iy_lo_dout;
4779
             next_state <= pshu_iyh_state;
4780
 
4781
                          when pshu_iyh_state =>
4782
             -- decrement up
4783
             left_ctrl  <= up_left;
4784
             right_ctrl <= one_right;
4785
             alu_ctrl   <= alu_sub16;
4786
                                 if ea(4 downto 0) = "00000" then
4787
               up_ctrl    <= latch_up;
4788
                                 else
4789
               up_ctrl    <= load_up;
4790
                                 end if;
4791
                                 -- write iy hi
4792
             addr_ctrl  <= pushu_ad;
4793
                            dout_ctrl  <= iy_hi_dout;
4794
                                 if ea(4) = '1' then
4795
                                   next_state   <= pshu_ixl_state;
4796
                                 elsif ea(3) = '1' then
4797
                                   next_state   <= pshu_dp_state;
4798
                                 elsif ea(2) = '1' then
4799
                                   next_state   <= pshu_accb_state;
4800
                                 elsif ea(1) = '1' then
4801
                                   next_state   <= pshu_acca_state;
4802
                                 elsif ea(0) = '1' then
4803
                                   next_state   <= pshu_cc_state;
4804
                                 else
4805
               lic          <= '1';
4806
                                   next_state   <= fetch_state;
4807
                                 end if;
4808
 
4809
                          when pshu_ixl_state =>
4810
             -- decrement up
4811
             left_ctrl  <= up_left;
4812
             right_ctrl <= one_right;
4813
             alu_ctrl   <= alu_sub16;
4814
             up_ctrl    <= load_up;
4815
                                 -- write ix low
4816
             addr_ctrl  <= pushu_ad;
4817
                            dout_ctrl  <= ix_lo_dout;
4818
             next_state <= pshu_ixh_state;
4819
 
4820
                          when pshu_ixh_state =>
4821
             -- decrement up
4822
             left_ctrl  <= up_left;
4823
             right_ctrl <= one_right;
4824
             alu_ctrl   <= alu_sub16;
4825
                                 if ea(3 downto 0) = "0000" then
4826
               up_ctrl    <= latch_up;
4827
                                 else
4828
               up_ctrl    <= load_up;
4829
                                 end if;
4830
                                 -- write ix hi
4831
             addr_ctrl  <= pushu_ad;
4832
                            dout_ctrl  <= ix_hi_dout;
4833
                                 if ea(3) = '1' then
4834
                                   next_state   <= pshu_dp_state;
4835
                                 elsif ea(2) = '1' then
4836
                                   next_state   <= pshu_accb_state;
4837
                                 elsif ea(1) = '1' then
4838
                                   next_state   <= pshu_acca_state;
4839
                                 elsif ea(0) = '1' then
4840
                                   next_state   <= pshu_cc_state;
4841
                                 else
4842
               lic          <= '1';
4843
                                   next_state   <= fetch_state;
4844
                                 end if;
4845
 
4846
                          when pshu_dp_state =>
4847
             -- decrement up
4848
             left_ctrl  <= up_left;
4849
             right_ctrl <= one_right;
4850
             alu_ctrl   <= alu_sub16;
4851
                                 if ea(2 downto 0) = "000" then
4852
               up_ctrl    <= latch_up;
4853
                                 else
4854
               up_ctrl    <= load_up;
4855
                                 end if;
4856
                                 -- write dp
4857
             addr_ctrl  <= pushu_ad;
4858
                            dout_ctrl  <= dp_dout;
4859
                                 if ea(2) = '1' then
4860
                                   next_state   <= pshu_accb_state;
4861
                                 elsif ea(1) = '1' then
4862
                                   next_state   <= pshu_acca_state;
4863
                                 elsif ea(0) = '1' then
4864
                                   next_state   <= pshu_cc_state;
4865
                                 else
4866
               lic          <= '1';
4867
                                   next_state   <= fetch_state;
4868
                                 end if;
4869
 
4870
                          when pshu_accb_state =>
4871
             -- decrement up
4872
             left_ctrl  <= up_left;
4873
             right_ctrl <= one_right;
4874
             alu_ctrl   <= alu_sub16;
4875
                                 if ea(1 downto 0) = "00" then
4876
               up_ctrl    <= latch_up;
4877
                                 else
4878
               up_ctrl    <= load_up;
4879
                                 end if;
4880
                                 -- write accb
4881
             addr_ctrl  <= pushu_ad;
4882
                            dout_ctrl  <= accb_dout;
4883
                                 if ea(1) = '1' then
4884
                                   next_state   <= pshu_acca_state;
4885
                                 elsif ea(0) = '1' then
4886
                                   next_state   <= pshu_cc_state;
4887
                                 else
4888
               lic          <= '1';
4889
                                   next_state   <= fetch_state;
4890
                                 end if;
4891
 
4892
                          when pshu_acca_state =>
4893
             -- decrement up
4894
             left_ctrl  <= up_left;
4895
             right_ctrl <= one_right;
4896
             alu_ctrl   <= alu_sub16;
4897
                                 if ea(0) = '0' then
4898
               up_ctrl    <= latch_up;
4899
                                 else
4900
               up_ctrl    <= load_up;
4901
                                 end if;
4902
                                 -- write acca
4903
             addr_ctrl  <= pushu_ad;
4904
                            dout_ctrl  <= acca_dout;
4905
                                 if ea(0) = '1' then
4906
                                   next_state   <= pshu_cc_state;
4907
                                 else
4908
               lic          <= '1';
4909
                                   next_state   <= fetch_state;
4910
                                 end if;
4911
 
4912
                          when pshu_cc_state =>
4913
             -- idle up
4914
                                 -- write cc
4915
             addr_ctrl  <= pushu_ad;
4916
                            dout_ctrl  <= cc_dout;
4917
             lic        <= '1';
4918
             next_state <= fetch_state;
4919
 
4920
                          --
4921
                          -- enter here on PULU
4922
                          -- ea hold register mask
4923
                          --
4924
                          when pulu_state =>
4925
                                 -- idle UP
4926
                                 -- idle bus
4927
                                 if ea(0) = '1' then
4928
                                   next_state <= pulu_cc_state;
4929
                                 elsif ea(1) = '1' then
4930
                                   next_state <= pulu_acca_state;
4931
                                 elsif ea(2) = '1' then
4932
                                   next_state <= pulu_accb_state;
4933
                                 elsif ea(3) = '1' then
4934
                                   next_state <= pulu_dp_state;
4935
                                 elsif ea(4) = '1' then
4936
                                   next_state <= pulu_ixh_state;
4937
                                 elsif ea(5) = '1' then
4938
                                   next_state <= pulu_iyh_state;
4939
                                 elsif ea(6) = '1' then
4940
               next_state <= pulu_sph_state;
4941
                                 elsif ea(7) = '1' then
4942
               next_state <= pulu_pch_state;
4943
                                 else
4944
               lic        <= '1';
4945
                                   next_state <= fetch_state;
4946
                                 end if;
4947
 
4948
                          when pulu_cc_state =>
4949
                                 -- increment up
4950
             left_ctrl  <= up_left;
4951
             right_ctrl <= one_right;
4952
             alu_ctrl   <= alu_add16;
4953
             up_ctrl    <= load_up;
4954
                                 -- read cc
4955
             cc_ctrl    <= pull_cc;
4956
             addr_ctrl  <= pullu_ad;
4957
                                 if ea(1) = '1' then
4958
                                   next_state <= pulu_acca_state;
4959
                                 elsif ea(2) = '1' then
4960
                                   next_state <= pulu_accb_state;
4961
                                 elsif ea(3) = '1' then
4962
                                   next_state <= pulu_dp_state;
4963
                                 elsif ea(4) = '1' then
4964
                                   next_state <= pulu_ixh_state;
4965
                                 elsif ea(5) = '1' then
4966
                                   next_state <= pulu_iyh_state;
4967
                                 elsif ea(6) = '1' then
4968
               next_state <= pulu_sph_state;
4969
                                 elsif ea(7) = '1' then
4970
               next_state <= pulu_pch_state;
4971
                                 else
4972
               lic        <= '1';
4973
                                   next_state <= fetch_state;
4974
                                 end if;
4975
 
4976
                          when pulu_acca_state =>
4977
                                 -- increment up
4978
             left_ctrl  <= up_left;
4979
             right_ctrl <= one_right;
4980
             alu_ctrl   <= alu_add16;
4981
             up_ctrl    <= load_up;
4982
                                 -- read acca
4983
                                 acca_ctrl  <= pull_acca;
4984
             addr_ctrl  <= pullu_ad;
4985
                                 if ea(2) = '1' then
4986
                                   next_state <= pulu_accb_state;
4987
                                 elsif ea(3) = '1' then
4988
                                   next_state <= pulu_dp_state;
4989
                                 elsif ea(4) = '1' then
4990
                                   next_state <= pulu_ixh_state;
4991
                                 elsif ea(5) = '1' then
4992
                                   next_state <= pulu_iyh_state;
4993
                                 elsif ea(6) = '1' then
4994
               next_state <= pulu_sph_state;
4995
                                 elsif ea(7) = '1' then
4996
               next_state <= pulu_pch_state;
4997
                                 else
4998
               lic        <= '1';
4999
                                   next_state <= fetch_state;
5000
                                 end if;
5001
 
5002
                          when pulu_accb_state =>
5003
                                 -- increment up
5004
             left_ctrl  <= up_left;
5005
             right_ctrl <= one_right;
5006
             alu_ctrl   <= alu_add16;
5007
             up_ctrl    <= load_up;
5008
                                 -- read accb
5009
                                 accb_ctrl  <= pull_accb;
5010
             addr_ctrl  <= pullu_ad;
5011
                                 if ea(3) = '1' then
5012
                                   next_state <= pulu_dp_state;
5013
                                 elsif ea(4) = '1' then
5014
                                   next_state <= pulu_ixh_state;
5015
                                 elsif ea(5) = '1' then
5016
                                   next_state <= pulu_iyh_state;
5017
                                 elsif ea(6) = '1' then
5018
               next_state <= pulu_sph_state;
5019
                                 elsif ea(7) = '1' then
5020
               next_state <= pulu_pch_state;
5021
                                 else
5022
               lic        <= '1';
5023
                                   next_state <= fetch_state;
5024
                                 end if;
5025
 
5026
                          when pulu_dp_state =>
5027
                                 -- increment up
5028
             left_ctrl  <= up_left;
5029
             right_ctrl <= one_right;
5030
             alu_ctrl   <= alu_add16;
5031
             up_ctrl    <= load_up;
5032
                                 -- read dp
5033
                                 dp_ctrl    <= pull_dp;
5034
             addr_ctrl  <= pullu_ad;
5035
                                 if ea(4) = '1' then
5036
                                   next_state <= pulu_ixh_state;
5037
                                 elsif ea(5) = '1' then
5038
                                   next_state <= pulu_iyh_state;
5039
                                 elsif ea(6) = '1' then
5040
               next_state <= pulu_sph_state;
5041
                                 elsif ea(7) = '1' then
5042
               next_state <= pulu_pch_state;
5043
                                 else
5044
               lic        <= '1';
5045
                                   next_state <= fetch_state;
5046
                                 end if;
5047
 
5048
                          when pulu_ixh_state =>
5049
             -- increment up
5050
             left_ctrl  <= up_left;
5051
             right_ctrl <= one_right;
5052
             alu_ctrl   <= alu_add16;
5053
             up_ctrl    <= load_up;
5054
                                 -- read ix hi
5055
                                 ix_ctrl    <= pull_hi_ix;
5056
             addr_ctrl  <= pullu_ad;
5057
             next_state <= pulu_ixl_state;
5058
 
5059
                          when pulu_ixl_state =>
5060
                                 -- increment up
5061
             left_ctrl  <= up_left;
5062
             right_ctrl <= one_right;
5063
             alu_ctrl   <= alu_add16;
5064
             up_ctrl    <= load_up;
5065
                                 -- read ix low
5066
                                 ix_ctrl    <= pull_lo_ix;
5067
             addr_ctrl  <= pullu_ad;
5068
                                 if ea(5) = '1' then
5069
                                   next_state <= pulu_iyh_state;
5070
                                 elsif ea(6) = '1' then
5071
               next_state <= pulu_sph_state;
5072
                                 elsif ea(7) = '1' then
5073
               next_state <= pulu_pch_state;
5074
                                 else
5075
               lic        <= '1';
5076
                                   next_state <= fetch_state;
5077
                                 end if;
5078
 
5079
                          when pulu_iyh_state =>
5080
             -- increment up
5081
             left_ctrl  <= up_left;
5082
             right_ctrl <= one_right;
5083
             alu_ctrl   <= alu_add16;
5084
             up_ctrl    <= load_up;
5085
                                 -- read iy hi
5086
                                 iy_ctrl    <= pull_hi_iy;
5087
             addr_ctrl  <= pullu_ad;
5088
             next_state <= pulu_iyl_state;
5089
 
5090
                          when pulu_iyl_state =>
5091
             -- increment up
5092
             left_ctrl  <= up_left;
5093
             right_ctrl <= one_right;
5094
             alu_ctrl   <= alu_add16;
5095
             up_ctrl    <= load_up;
5096
                                 -- read iy low
5097
                                 iy_ctrl    <= pull_lo_iy;
5098
             addr_ctrl  <= pullu_ad;
5099
                                 if ea(6) = '1' then
5100
               next_state <= pulu_sph_state;
5101
                                 elsif ea(7) = '1' then
5102
               next_state <= pulu_pch_state;
5103
                                 else
5104
               lic        <= '1';
5105
                                   next_state <= fetch_state;
5106
                                 end if;
5107
 
5108
                          when pulu_sph_state =>
5109
             -- increment up
5110
             left_ctrl  <= up_left;
5111
             right_ctrl <= one_right;
5112
             alu_ctrl   <= alu_add16;
5113
             up_ctrl    <= load_up;
5114
                                 -- read sp hi
5115
                                 sp_ctrl    <= pull_hi_sp;
5116
             addr_ctrl  <= pullu_ad;
5117
             next_state <= pulu_spl_state;
5118
 
5119
                          when pulu_spl_state =>
5120
                                 -- increment up
5121
             left_ctrl  <= up_left;
5122
             right_ctrl <= one_right;
5123
             alu_ctrl   <= alu_add16;
5124
             up_ctrl    <= load_up;
5125
                                 -- read sp low
5126
                                 sp_ctrl    <= pull_lo_sp;
5127
             addr_ctrl  <= pullu_ad;
5128
                                 if ea(7) = '1' then
5129
               next_state <= pulu_pch_state;
5130
                                 else
5131
               lic        <= '1';
5132
                                   next_state <= fetch_state;
5133
                                 end if;
5134
 
5135
                          when pulu_pch_state =>
5136
             -- increment up
5137
             left_ctrl  <= up_left;
5138
             right_ctrl <= one_right;
5139
             alu_ctrl   <= alu_add16;
5140
             up_ctrl    <= load_up;
5141
                                 -- pull pc hi
5142
                                 pc_ctrl    <= pull_hi_pc;
5143
             addr_ctrl  <= pullu_ad;
5144
             next_state <= pulu_pcl_state;
5145
 
5146
                          when pulu_pcl_state =>
5147
                                 -- increment up
5148
             left_ctrl  <= up_left;
5149
             right_ctrl <= one_right;
5150
             alu_ctrl   <= alu_add16;
5151
             up_ctrl    <= load_up;
5152
                                 -- read pc low
5153
                                 pc_ctrl    <= pull_lo_pc;
5154
             addr_ctrl  <= pullu_ad;
5155
             lic        <= '1';
5156
             next_state <= fetch_state;
5157
 
5158
                          --
5159
                          -- pop the Condition codes
5160
                          --
5161
                          when rti_cc_state =>
5162
                                 -- increment sp
5163
             left_ctrl  <= sp_left;
5164
             right_ctrl <= one_right;
5165
             alu_ctrl   <= alu_add16;
5166
             sp_ctrl    <= load_sp;
5167
                                 -- read cc
5168
             cc_ctrl    <= pull_cc;
5169
             addr_ctrl  <= pulls_ad;
5170
             next_state <= rti_entire_state;
5171
 
5172
                          --
5173
                          -- Added RTI cycle 11th July 2006 John Kent.
5174
                          -- test the "Entire" Flag
5175
                          -- that has just been popped off the stack
5176
                          --
5177
                          when rti_entire_state =>
5178
                                 --
5179
                                 -- The Entire flag must be recovered from the stack
5180
                                 -- before testing.
5181
                                 --
5182
                                 if cc(EBIT) = '1' then
5183
               next_state   <= rti_acca_state;
5184
                                 else
5185
               next_state   <= rti_pch_state;
5186
                                 end if;
5187
 
5188
                          when rti_acca_state =>
5189
                                 -- increment sp
5190
             left_ctrl  <= sp_left;
5191
             right_ctrl <= one_right;
5192
             alu_ctrl   <= alu_add16;
5193
             sp_ctrl    <= load_sp;
5194
                                 -- read acca
5195
                                 acca_ctrl  <= pull_acca;
5196
             addr_ctrl  <= pulls_ad;
5197
             next_state <= rti_accb_state;
5198
 
5199
                          when rti_accb_state =>
5200
                                 -- increment sp
5201
             left_ctrl  <= sp_left;
5202
             right_ctrl <= one_right;
5203
             alu_ctrl   <= alu_add16;
5204
             sp_ctrl    <= load_sp;
5205
                                 -- read accb
5206
                                 accb_ctrl  <= pull_accb;
5207
             addr_ctrl  <= pulls_ad;
5208
             next_state <= rti_dp_state;
5209
 
5210
                          when rti_dp_state =>
5211
                                 -- increment sp
5212
             left_ctrl  <= sp_left;
5213
             right_ctrl <= one_right;
5214
             alu_ctrl   <= alu_add16;
5215
             sp_ctrl    <= load_sp;
5216
                                 -- read dp
5217
                                 dp_ctrl    <= pull_dp;
5218
             addr_ctrl  <= pulls_ad;
5219
             next_state <= rti_ixh_state;
5220
 
5221
                          when rti_ixh_state =>
5222
                                 -- increment sp
5223
             left_ctrl  <= sp_left;
5224
             right_ctrl <= one_right;
5225
             alu_ctrl   <= alu_add16;
5226
             sp_ctrl    <= load_sp;
5227
                                 -- read ix hi
5228
                                 ix_ctrl    <= pull_hi_ix;
5229
             addr_ctrl  <= pulls_ad;
5230
             next_state <= rti_ixl_state;
5231
 
5232
                          when rti_ixl_state =>
5233
                                 -- increment sp
5234
             left_ctrl  <= sp_left;
5235
             right_ctrl <= one_right;
5236
             alu_ctrl   <= alu_add16;
5237
             sp_ctrl    <= load_sp;
5238
                                 -- read ix low
5239
                                 ix_ctrl    <= pull_lo_ix;
5240
             addr_ctrl  <= pulls_ad;
5241
             next_state <= rti_iyh_state;
5242
 
5243
                          when rti_iyh_state =>
5244
                                 -- increment sp
5245
             left_ctrl  <= sp_left;
5246
             right_ctrl <= one_right;
5247
             alu_ctrl   <= alu_add16;
5248
             sp_ctrl    <= load_sp;
5249
                                 -- read iy hi
5250
                                 iy_ctrl    <= pull_hi_iy;
5251
             addr_ctrl  <= pulls_ad;
5252
             next_state <= rti_iyl_state;
5253
 
5254
                          when rti_iyl_state =>
5255
                                 -- increment sp
5256
             left_ctrl  <= sp_left;
5257
             right_ctrl <= one_right;
5258
             alu_ctrl   <= alu_add16;
5259
             sp_ctrl    <= load_sp;
5260
                                 -- read iy low
5261
                                 iy_ctrl    <= pull_lo_iy;
5262
             addr_ctrl  <= pulls_ad;
5263
             next_state <= rti_uph_state;
5264
 
5265
 
5266
                          when rti_uph_state =>
5267
                                 -- increment sp
5268
             left_ctrl  <= sp_left;
5269
             right_ctrl <= one_right;
5270
             alu_ctrl   <= alu_add16;
5271
             sp_ctrl    <= load_sp;
5272
                                 -- read up hi
5273
                                 up_ctrl    <= pull_hi_up;
5274
             addr_ctrl  <= pulls_ad;
5275
             next_state <= rti_upl_state;
5276
 
5277
                          when rti_upl_state =>
5278
                                 -- increment sp
5279
             left_ctrl  <= sp_left;
5280
             right_ctrl <= one_right;
5281
             alu_ctrl   <= alu_add16;
5282
             sp_ctrl    <= load_sp;
5283
                                 -- read up low
5284
             up_ctrl    <= pull_lo_up;
5285
             addr_ctrl  <= pulls_ad;
5286
             next_state <= rti_pch_state;
5287
 
5288
                          when rti_pch_state =>
5289
                  -- increment sp
5290
             left_ctrl  <= sp_left;
5291
             right_ctrl <= one_right;
5292
             alu_ctrl   <= alu_add16;
5293
             sp_ctrl    <= load_sp;
5294
                                 -- pull pc hi
5295
                                 pc_ctrl    <= pull_hi_pc;
5296
             addr_ctrl  <= pulls_ad;
5297
             next_state <= rti_pcl_state;
5298
 
5299
                          when rti_pcl_state =>
5300
                                 -- increment sp
5301
             left_ctrl  <= sp_left;
5302
             right_ctrl <= one_right;
5303
             alu_ctrl   <= alu_add16;
5304
             sp_ctrl    <= load_sp;
5305
                  -- pull pc low
5306
                                 pc_ctrl    <= pull_lo_pc;
5307
             addr_ctrl  <= pulls_ad;
5308
             lic        <= '1';
5309
             next_state <= fetch_state;
5310
 
5311
                          --
5312 130 dilbert57
                          -- here on NMI interrupt
5313
                          -- Complete execute cycle of the last instruction.
5314
           -- If it was a dual operand instruction
5315
           --
5316
                          when int_nmi_state =>
5317
             next_state   <= int_nmi1_state;
5318
 
5319
                          -- Idle bus cycle
5320
           when int_nmi1_state =>
5321
             -- pre decrement sp
5322
             left_ctrl    <= sp_left;
5323
             right_ctrl   <= one_right;
5324
             alu_ctrl     <= alu_sub16;
5325
             sp_ctrl      <= load_sp;
5326
                                 iv_ctrl      <= nmi_iv;
5327
                                 st_ctrl      <= push_st;
5328
                                 return_state <= int_nmimask_state;
5329
             next_state   <= int_entire_state;
5330
 
5331
                          --
5332
                          -- here on IRQ interrupt
5333
                          -- Complete execute cycle of the last instruction.
5334
           -- If it was a dual operand instruction
5335
           --
5336
                          when int_irq_state =>
5337
             next_state   <= int_irq1_state;
5338
 
5339 122 dilbert57
                          -- pre decrement the sp
5340
                          -- Idle bus cycle
5341 130 dilbert57
           when int_irq1_state =>
5342
             -- pre decrement sp
5343
             left_ctrl    <= sp_left;
5344
             right_ctrl   <= one_right;
5345
             alu_ctrl     <= alu_sub16;
5346
             sp_ctrl      <= load_sp;
5347
                                 iv_ctrl      <= irq_iv;
5348
                                 st_ctrl      <= push_st;
5349
                                 return_state <= int_irqmask_state;
5350
             next_state   <= int_entire_state;
5351
 
5352 122 dilbert57
                          --
5353 130 dilbert57
                          -- here on FIRQ interrupt
5354
                          -- Complete execution cycle of the last instruction
5355
           -- if it was a dual operand instruction
5356
           --
5357
                          when int_firq_state =>
5358
             next_state   <= int_firq1_state;
5359 122 dilbert57
 
5360 130 dilbert57
                          -- Idle bus cycle
5361
           when int_firq1_state =>
5362
             -- pre decrement sp
5363
             left_ctrl    <= sp_left;
5364
             right_ctrl   <= one_right;
5365
             alu_ctrl     <= alu_sub16;
5366
             sp_ctrl      <= load_sp;
5367
                                 iv_ctrl      <= firq_iv;
5368
                                 st_ctrl      <= push_st;
5369
                                 return_state <= int_firqmask_state;
5370
             next_state   <= int_fast_state;
5371
 
5372
           --
5373
           -- CWAI entry point
5374
           -- stack pointer already pre-decremented
5375
           -- mask condition codes
5376
           --
5377
           when cwai_state =>
5378
              -- AND CC with md
5379
              left_ctrl    <= md_left;
5380
              right_ctrl   <= zero_right;
5381
              alu_ctrl     <= alu_andcc;
5382
              cc_ctrl      <= load_cc;
5383
                                  st_ctrl      <= push_st;
5384
                                  return_state <= int_cwai_state;
5385
                                  next_state   <= int_entire_state;
5386
 
5387 122 dilbert57
                          --
5388 130 dilbert57
                          -- wait here for an interrupt
5389
                          --
5390
                          when int_cwai_state =>
5391
             if (nmi_req = '1') then
5392
                                   iv_ctrl    <= nmi_iv;
5393
                              next_state <= int_nmimask_state;
5394
                                 --
5395
                                 -- FIRQ & IRQ are level sensitive
5396
                                 --
5397
             elsif (firq = '1') and (cc(FBIT) = '0') then
5398
                                   iv_ctrl     <= firq_iv;
5399
                              next_state  <= int_firqmask_state;
5400
 
5401
                            elsif (irq = '1') and (cc(IBIT) = '0') then
5402
                                   iv_ctrl     <= irq_iv;
5403
                              next_state  <= int_irqmask_state;
5404
                            else
5405
                                   next_state <= int_cwai_state;
5406
             end if;
5407
 
5408
           --
5409
                          -- State to mask I Flag and F Flag (NMI)
5410
                          --
5411
                          when int_nmimask_state =>
5412
                            alu_ctrl   <= alu_seif;
5413
                                 cc_ctrl    <= load_cc;
5414
             next_state <= vect_hi_state;
5415
 
5416
           --
5417
                          -- State to mask I Flag and F Flag (FIRQ)
5418
                          --
5419
                          when int_firqmask_state =>
5420
                            alu_ctrl   <= alu_seif;
5421
                                 cc_ctrl    <= load_cc;
5422
             next_state <= vect_hi_state;
5423
 
5424
 
5425
           --
5426
                          -- State to mask I Flag and F Flag (SWI)
5427
                          --
5428
                          when int_swimask_state =>
5429
                            alu_ctrl   <= alu_seif;
5430
                                 cc_ctrl    <= load_cc;
5431
             next_state <= vect_hi_state;
5432
 
5433
           --
5434
                          -- State to mask I Flag only (IRQ)
5435
                          --
5436
           when int_irqmask_state =>
5437
                                 alu_ctrl   <= alu_sei;
5438
                                 cc_ctrl    <= load_cc;
5439
             next_state <= vect_hi_state;
5440
 
5441
                          --
5442 122 dilbert57
                          -- set Entire Flag on SWI, SWI2, SWI3 and CWAI, IRQ and NMI
5443
                          -- before stacking all registers
5444
                          --
5445
                          when int_entire_state =>
5446
             -- set entire flag
5447
             alu_ctrl   <= alu_see;
5448
             cc_ctrl    <= load_cc;
5449
             next_state <= int_pcl_state;
5450 130 dilbert57
 
5451 122 dilbert57
                          --
5452
                          -- clear Entire Flag on FIRQ
5453
                          -- before stacking all registers
5454
                          --
5455
                          when int_fast_state =>
5456
             -- clear entire flag
5457
             alu_ctrl   <= alu_cle;
5458
             cc_ctrl    <= load_cc;
5459
             next_state <= int_pcl_state;
5460
 
5461
                          when int_pcl_state =>
5462
             -- decrement sp
5463
             left_ctrl  <= sp_left;
5464
             right_ctrl <= one_right;
5465
             alu_ctrl   <= alu_sub16;
5466
             sp_ctrl    <= load_sp;
5467
                                 -- write pc low
5468
             addr_ctrl  <= pushs_ad;
5469
                            dout_ctrl  <= pc_lo_dout;
5470
             next_state <= int_pch_state;
5471
 
5472
                          when int_pch_state =>
5473
             -- decrement sp
5474
             left_ctrl  <= sp_left;
5475
             right_ctrl <= one_right;
5476
             alu_ctrl   <= alu_sub16;
5477
             sp_ctrl    <= load_sp;
5478
                                 -- write pc hi
5479
             addr_ctrl  <= pushs_ad;
5480
                            dout_ctrl  <= pc_hi_dout;
5481
                                 if cc(EBIT) = '1' then
5482
               next_state   <= int_upl_state;
5483
                                 else
5484
               next_state   <= int_cc_state;
5485
                                 end if;
5486
 
5487
                          when int_upl_state =>
5488
             -- decrement sp
5489
             left_ctrl  <= sp_left;
5490
             right_ctrl <= one_right;
5491
             alu_ctrl   <= alu_sub16;
5492
             sp_ctrl    <= load_sp;
5493
                                 -- write up low
5494
             addr_ctrl  <= pushs_ad;
5495
                            dout_ctrl  <= up_lo_dout;
5496
             next_state <= int_uph_state;
5497
 
5498
                          when int_uph_state =>
5499
             -- decrement sp
5500
             left_ctrl  <= sp_left;
5501
             right_ctrl <= one_right;
5502
             alu_ctrl   <= alu_sub16;
5503
             sp_ctrl    <= load_sp;
5504
                                 -- write ix hi
5505
             addr_ctrl  <= pushs_ad;
5506
                            dout_ctrl  <= up_hi_dout;
5507
             next_state <= int_iyl_state;
5508
 
5509
                          when int_iyl_state =>
5510
             -- decrement sp
5511
             left_ctrl  <= sp_left;
5512
             right_ctrl <= one_right;
5513
             alu_ctrl   <= alu_sub16;
5514
             sp_ctrl    <= load_sp;
5515
                                 -- write ix low
5516
             addr_ctrl  <= pushs_ad;
5517
                            dout_ctrl  <= iy_lo_dout;
5518
             next_state <= int_iyh_state;
5519
 
5520
                          when int_iyh_state =>
5521
             -- decrement sp
5522
             left_ctrl  <= sp_left;
5523
             right_ctrl <= one_right;
5524
             alu_ctrl   <= alu_sub16;
5525
             sp_ctrl    <= load_sp;
5526
                                 -- write ix hi
5527
             addr_ctrl  <= pushs_ad;
5528
                            dout_ctrl  <= iy_hi_dout;
5529
             next_state <= int_ixl_state;
5530
 
5531
                          when int_ixl_state =>
5532
             -- decrement sp
5533
             left_ctrl  <= sp_left;
5534
             right_ctrl <= one_right;
5535
             alu_ctrl   <= alu_sub16;
5536
             sp_ctrl    <= load_sp;
5537
                                 -- write ix low
5538
             addr_ctrl  <= pushs_ad;
5539
                            dout_ctrl  <= ix_lo_dout;
5540
             next_state <= int_ixh_state;
5541
 
5542
                          when int_ixh_state =>
5543
             -- decrement sp
5544
             left_ctrl  <= sp_left;
5545
             right_ctrl <= one_right;
5546
             alu_ctrl   <= alu_sub16;
5547
             sp_ctrl    <= load_sp;
5548
                                 -- write ix hi
5549
             addr_ctrl  <= pushs_ad;
5550
                            dout_ctrl  <= ix_hi_dout;
5551
             next_state <= int_dp_state;
5552
 
5553
                          when int_dp_state =>
5554
             -- decrement sp
5555
             left_ctrl  <= sp_left;
5556
             right_ctrl <= one_right;
5557
             alu_ctrl   <= alu_sub16;
5558
             sp_ctrl    <= load_sp;
5559
                                 -- write accb
5560
             addr_ctrl  <= pushs_ad;
5561
                            dout_ctrl  <= dp_dout;
5562
             next_state <= int_accb_state;
5563
 
5564
                          when int_accb_state =>
5565
             -- decrement sp
5566
             left_ctrl  <= sp_left;
5567
             right_ctrl <= one_right;
5568
             alu_ctrl   <= alu_sub16;
5569
             sp_ctrl    <= load_sp;
5570
                                 -- write accb
5571
             addr_ctrl  <= pushs_ad;
5572
                            dout_ctrl  <= accb_dout;
5573
             next_state <= int_acca_state;
5574
 
5575
                          when int_acca_state =>
5576
             -- decrement sp
5577
             left_ctrl  <= sp_left;
5578
             right_ctrl <= one_right;
5579
             alu_ctrl   <= alu_sub16;
5580
             sp_ctrl    <= load_sp;
5581
                                 -- write acca
5582
             addr_ctrl  <= pushs_ad;
5583
                            dout_ctrl  <= acca_dout;
5584
             next_state <= int_cc_state;
5585
 
5586
                          when int_cc_state =>
5587
                                 -- write cc
5588
             addr_ctrl  <= pushs_ad;
5589
                            dout_ctrl  <= cc_dout;
5590 130 dilbert57
                                 next_state <= saved_state;
5591 122 dilbert57
 
5592
                          --
5593
                          -- According to the 6809 programming manual:
5594
                          -- If an interrupt is received and is masked 
5595
                          -- or lasts for less than three cycles, the PC 
5596
                          -- will advance to the next instruction.
5597
                          -- If an interrupt is unmasked and lasts
5598
                          -- for more than three cycles, an interrupt
5599
                          -- will be generated.
5600
                          -- Note that I don't wait 3 clock cycles.
5601
                          -- John Kent 11th July 2006
5602
                          --
5603
                          when sync_state =>
5604 130 dilbert57
             lic        <= '1';
5605
             ba         <= '1';
5606
                         --
5607
                         -- Version 1.28 2015-05-30
5608
                         -- Exit sync_state on interrupt.
5609
                         -- If the interrupts are active
5610
                         -- they will be caught in the state_machine process
5611
                         -- and the interrupt service routine microcode will be executed.
5612
                         -- Masked interrupts will exit the sync_state.
5613
                         -- Moved from the state_machine process to the state_sequencer process
5614
                         --
5615
                                if (firq = '1') or (irq = '1') then
5616
               next_state <= fetch_state;
5617
                                else
5618
                    next_state <= sync_state;
5619
            end if;
5620
 
5621 122 dilbert57
                          when halt_state =>
5622 130 dilbert57
           --
5623
           -- 2011-10-30 John Kent
5624
           -- ba & bs should be high
5625
             ba           <= '1';
5626
             bs           <= '1';
5627 122 dilbert57
                                 if halt = '1' then
5628
               next_state   <= halt_state;
5629
                                 else
5630 130 dilbert57
               next_state   <= fetch_state;
5631 122 dilbert57
                                 end if;
5632
 
5633
                  end case;
5634 130 dilbert57
 
5635
--
5636
-- Ver 1.23 2011-10-30 John Kent
5637
-- First instruction cycle might be
5638
-- fetch_state
5639
-- halt_state
5640
-- int_nmirq_state
5641
-- int_firq_state
5642
--
5643
        if fic = '1' then
5644
                           --
5645
                                        case op_code(7 downto 6) is
5646
                                        when "10" => -- acca
5647
                                     case op_code(3 downto 0) is
5648
                                          when "0000" => -- suba
5649
                                            left_ctrl  <= acca_left;
5650
                                            right_ctrl <= md_right;
5651
                                            alu_ctrl   <= alu_sub8;
5652
                                                 cc_ctrl    <= load_cc;
5653
                                            acca_ctrl  <= load_acca;
5654
                                          when "0001" => -- cmpa
5655
                                            left_ctrl   <= acca_left;
5656
                                            right_ctrl  <= md_right;
5657
                                            alu_ctrl    <= alu_sub8;
5658
                                                 cc_ctrl     <= load_cc;
5659
                                          when "0010" => -- sbca
5660
                                            left_ctrl   <= acca_left;
5661
                                            right_ctrl  <= md_right;
5662
                                            alu_ctrl    <= alu_sbc;
5663
                                                 cc_ctrl     <= load_cc;
5664
                                            acca_ctrl   <= load_acca;
5665
                                          when "0011" =>
5666
                                            case pre_code is
5667
                                                 when "00010000" => -- page 2 -- cmpd
5668
                                              left_ctrl   <= accd_left;
5669
                                              right_ctrl  <= md_right;
5670
                                              alu_ctrl    <= alu_sub16;
5671
                                                   cc_ctrl     <= load_cc;
5672
                                                 when "00010001" => -- page 3 -- cmpu
5673
                                              left_ctrl   <= up_left;
5674
                                              right_ctrl  <= md_right;
5675
                                              alu_ctrl    <= alu_sub16;
5676
                                                   cc_ctrl     <= load_cc;
5677
                                                 when others => -- page 1 -- subd
5678
                                              left_ctrl   <= accd_left;
5679
                                              right_ctrl  <= md_right;
5680
                                              alu_ctrl    <= alu_sub16;
5681
                                                   cc_ctrl     <= load_cc;
5682
                                              acca_ctrl   <= load_hi_acca;
5683
                                                   accb_ctrl   <= load_accb;
5684
                                                 end case;
5685
                                          when "0100" => -- anda
5686
                                            left_ctrl   <= acca_left;
5687
                                            right_ctrl  <= md_right;
5688
                                            alu_ctrl    <= alu_and;
5689
                                                 cc_ctrl     <= load_cc;
5690
                                            acca_ctrl   <= load_acca;
5691
                                          when "0101" => -- bita
5692
                                            left_ctrl   <= acca_left;
5693
                                            right_ctrl  <= md_right;
5694
                                            alu_ctrl    <= alu_and;
5695
                                                 cc_ctrl     <= load_cc;
5696
                                          when "0110" => -- ldaa
5697
                                            left_ctrl   <= acca_left;
5698
                                            right_ctrl  <= md_right;
5699
                                            alu_ctrl    <= alu_ld8;
5700
                                                 cc_ctrl     <= load_cc;
5701
                                            acca_ctrl   <= load_acca;
5702
                                          when "0111" => -- staa
5703
                                            left_ctrl   <= acca_left;
5704
                                            right_ctrl  <= md_right;
5705
                                            alu_ctrl    <= alu_st8;
5706
                                                 cc_ctrl     <= load_cc;
5707
                                          when "1000" => -- eora
5708
                                            left_ctrl   <= acca_left;
5709
                                            right_ctrl  <= md_right;
5710
                                            alu_ctrl    <= alu_eor;
5711
                                                 cc_ctrl     <= load_cc;
5712
                                            acca_ctrl   <= load_acca;
5713
                                          when "1001" => -- adca
5714
                                            left_ctrl   <= acca_left;
5715
                                            right_ctrl  <= md_right;
5716
                                            alu_ctrl    <= alu_adc;
5717
                                                 cc_ctrl     <= load_cc;
5718
                                            acca_ctrl   <= load_acca;
5719
                                          when "1010" => -- oraa
5720
                                            left_ctrl   <= acca_left;
5721
                                            right_ctrl  <= md_right;
5722
                                            alu_ctrl    <= alu_ora;
5723
                                                 cc_ctrl     <= load_cc;
5724
                                            acca_ctrl   <= load_acca;
5725
                                          when "1011" => -- adda
5726
                                            left_ctrl   <= acca_left;
5727
                                            right_ctrl  <= md_right;
5728
                                            alu_ctrl    <= alu_add8;
5729
                                                 cc_ctrl     <= load_cc;
5730
                                            acca_ctrl   <= load_acca;
5731
                                          when "1100" =>
5732
                                            case pre_code is
5733
                                                 when "00010000" => -- page 2 -- cmpy
5734
                                              left_ctrl   <= iy_left;
5735
                                              right_ctrl  <= md_right;
5736
                                              alu_ctrl    <= alu_sub16;
5737
                                                   cc_ctrl     <= load_cc;
5738
                                                 when "00010001" => -- page 3 -- cmps
5739
                                              left_ctrl   <= sp_left;
5740
                                              right_ctrl  <= md_right;
5741
                                              alu_ctrl    <= alu_sub16;
5742
                                                   cc_ctrl     <= load_cc;
5743
                                                 when others => -- page 1 -- cmpx
5744
                                              left_ctrl   <= ix_left;
5745
                                              right_ctrl  <= md_right;
5746
                                              alu_ctrl    <= alu_sub16;
5747
                                                   cc_ctrl     <= load_cc;
5748
                                                 end case;
5749
                                          when "1101" => -- bsr / jsr
5750
                                            null;
5751
                                          when "1110" => -- ldx
5752
                                            case pre_code is
5753
                                                 when "00010000" => -- page 2 -- ldy
5754
                                              left_ctrl   <= iy_left;
5755
                                              right_ctrl  <= md_right;
5756
                                              alu_ctrl    <= alu_ld16;
5757
                                                   cc_ctrl     <= load_cc;
5758
                     iy_ctrl     <= load_iy;
5759
                                                 when others =>   -- page 1 -- ldx
5760
                                              left_ctrl   <= ix_left;
5761
                                              right_ctrl  <= md_right;
5762
                                              alu_ctrl    <= alu_ld16;
5763
                                                   cc_ctrl     <= load_cc;
5764
                     ix_ctrl     <= load_ix;
5765
                                                 end case;
5766
                                          when "1111" => -- stx
5767
                                            case pre_code is
5768
                                                 when "00010000" => -- page 2 -- sty
5769
                                              left_ctrl   <= iy_left;
5770
                                              right_ctrl  <= md_right;
5771
                                              alu_ctrl    <= alu_st16;
5772
                                                   cc_ctrl     <= load_cc;
5773
                                                 when others =>     -- page 1 -- stx
5774
                                              left_ctrl   <= ix_left;
5775
                                              right_ctrl  <= md_right;
5776
                                              alu_ctrl    <= alu_st16;
5777
                                                   cc_ctrl     <= load_cc;
5778
                                                 end case;
5779
                                          when others =>
5780
                                            null;
5781
                                          end case;
5782
                                        when "11" => -- accb dual op
5783
                                     case op_code(3 downto 0) is
5784
                                          when "0000" => -- subb
5785
                                            left_ctrl   <= accb_left;
5786
                                            right_ctrl  <= md_right;
5787
                                            alu_ctrl    <= alu_sub8;
5788
                                                 cc_ctrl     <= load_cc;
5789
                   accb_ctrl   <= load_accb;
5790
                                          when "0001" => -- cmpb
5791
                                            left_ctrl   <= accb_left;
5792
                                            right_ctrl  <= md_right;
5793
                                            alu_ctrl    <= alu_sub8;
5794
                                                 cc_ctrl     <= load_cc;
5795
                                          when "0010" => -- sbcb
5796
                                            left_ctrl   <= accb_left;
5797
                                            right_ctrl  <= md_right;
5798
                                            alu_ctrl    <= alu_sbc;
5799
                                                 cc_ctrl     <= load_cc;
5800
                   accb_ctrl   <= load_accb;
5801
                                          when "0011" => -- addd
5802
                                            left_ctrl   <= accd_left;
5803
                                            right_ctrl  <= md_right;
5804
                                            alu_ctrl    <= alu_add16;
5805
                                                 cc_ctrl     <= load_cc;
5806
                                            acca_ctrl   <= load_hi_acca;
5807
                                                 accb_ctrl   <= load_accb;
5808
                                          when "0100" => -- andb
5809
                                            left_ctrl   <= accb_left;
5810
                                            right_ctrl  <= md_right;
5811
                                            alu_ctrl    <= alu_and;
5812
                                                 cc_ctrl     <= load_cc;
5813
                   accb_ctrl   <= load_accb;
5814
                                          when "0101" => -- bitb
5815
                                            left_ctrl   <= accb_left;
5816
                                            right_ctrl  <= md_right;
5817
                                            alu_ctrl    <= alu_and;
5818
                                                 cc_ctrl     <= load_cc;
5819
                                          when "0110" => -- ldab
5820
                                            left_ctrl   <= accb_left;
5821
                                            right_ctrl  <= md_right;
5822
                                            alu_ctrl    <= alu_ld8;
5823
                                                 cc_ctrl     <= load_cc;
5824
                   accb_ctrl   <= load_accb;
5825
                                          when "0111" => -- stab
5826
                                            left_ctrl   <= accb_left;
5827
                                            right_ctrl  <= md_right;
5828
                                            alu_ctrl    <= alu_st8;
5829
                                                 cc_ctrl     <= load_cc;
5830
                                          when "1000" => -- eorb
5831
                                            left_ctrl   <= accb_left;
5832
                                            right_ctrl  <= md_right;
5833
                                            alu_ctrl    <= alu_eor;
5834
                                                 cc_ctrl     <= load_cc;
5835
                   accb_ctrl   <= load_accb;
5836
                                          when "1001" => -- adcb
5837
                                            left_ctrl   <= accb_left;
5838
                                            right_ctrl  <= md_right;
5839
                                            alu_ctrl    <= alu_adc;
5840
                                                 cc_ctrl     <= load_cc;
5841
                   accb_ctrl   <= load_accb;
5842
                                          when "1010" => -- orab
5843
                                            left_ctrl   <= accb_left;
5844
                                            right_ctrl  <= md_right;
5845
                                            alu_ctrl    <= alu_ora;
5846
                                                 cc_ctrl     <= load_cc;
5847
                   accb_ctrl   <= load_accb;
5848
                                          when "1011" => -- addb
5849
                                            left_ctrl   <= accb_left;
5850
                                            right_ctrl  <= md_right;
5851
                                            alu_ctrl    <= alu_add8;
5852
                                                 cc_ctrl     <= load_cc;
5853
                   accb_ctrl   <= load_accb;
5854
                                          when "1100" => -- ldd
5855
                                            left_ctrl   <= accd_left;
5856
                                            right_ctrl  <= md_right;
5857
                                            alu_ctrl    <= alu_ld16;
5858
                                                 cc_ctrl     <= load_cc;
5859
                                            acca_ctrl   <= load_hi_acca;
5860
                   accb_ctrl   <= load_accb;
5861
                                          when "1101" => -- std
5862
                                            left_ctrl   <= accd_left;
5863
                                            right_ctrl  <= md_right;
5864
                                            alu_ctrl    <= alu_st16;
5865
                                                 cc_ctrl     <= load_cc;
5866
                                          when "1110" => -- ldu
5867
                                            case pre_code is
5868
                                                 when "00010000" => -- page 2 -- lds
5869
                                              left_ctrl   <= sp_left;
5870
                                              right_ctrl  <= md_right;
5871
                                              alu_ctrl    <= alu_ld16;
5872
                                                   cc_ctrl     <= load_cc;
5873
                                                   sp_ctrl     <= load_sp;
5874
                                                 when others => -- page 1 -- ldu
5875
                                              left_ctrl   <= up_left;
5876
                                              right_ctrl  <= md_right;
5877
                                              alu_ctrl    <= alu_ld16;
5878
                                                   cc_ctrl     <= load_cc;
5879
                     up_ctrl     <= load_up;
5880
                                                 end case;
5881
                                          when "1111" =>
5882
                                            case pre_code is
5883
                                                 when "00010000" => -- page 2 -- sts
5884
                                              left_ctrl   <= sp_left;
5885
                                              right_ctrl  <= md_right;
5886
                                              alu_ctrl    <= alu_st16;
5887
                                                   cc_ctrl     <= load_cc;
5888
                                                 when others =>     -- page 1 -- stu
5889
                                              left_ctrl   <= up_left;
5890
                                              right_ctrl  <= md_right;
5891
                                              alu_ctrl    <= alu_st16;
5892
                                                   cc_ctrl     <= load_cc;
5893
                                                 end case;
5894
                                          when others =>
5895
                                            null;
5896
                                          end case;
5897
                                        when others =>
5898
                                          null;
5899
                                        end case;
5900
 
5901
       end if; -- first instruction cycle (fic)
5902
       lic_out <= lic;
5903 122 dilbert57
end process;
5904
 
5905
end rtl;
5906
 

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