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[/] [System09/] [trunk/] [rtl/] [VHDL/] [cpu09n.vhd] - Blame information for rev 211

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1 130 dilbert57
--===========================================================================--
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--                                                                           --
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--        Synthesizable 6809 instruction compatible VHDL CPU core            --
4
--                                                                           --
5
--===========================================================================--
6
--
7
-- File name      : cpu09n.vhd
8
--
9
-- Entity name    : cpu09
10
--
11
-- Purpose        : 6809 instruction compatible CPU core written in VHDL
12
--                  with Last Instruction Cycle, bus available, bus status,
13
--                  and instruction fetch signals.
14
--                  Not cycle compatible with the original 6809 CPU
15
--
16
-- Dependencies   : ieee.std_logic_1164
17
--                  ieee.std_logic_unsigned
18
--
19
-- Author         : John E. Kent
20
--
21
-- Email          : dilbert57@opencores.org      
22
--
23
-- Web            : http://opencores.org/project,system09
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--
25
-- Description    : VMA (valid memory address) is hight whenever a valid memory
26
--                  access is made by an instruction fetch, interrupt vector fetch
27
--                  or a data read or write otherwise it is low indicating an idle
28
--                  bus cycle.
29
--                  IFETCH (instruction fetch output) is high whenever an
30
--                  instruction byte is read i.e. the program counter is applied 
31
--                  to the address bus.
32
--                  LIC (last instruction cycle output) is normally low
33
--                  but goes high on the last cycle of an instruction.
34
--                  BA (bus available output) is normally low but goes high while
35
--                  waiting in a Sync instruction state or the CPU is halted
36
--                  i.e. a DMA grant.
37
--                  BS (bus status output) is normally low but goes high during an
38
--                  interrupt or reset vector fetch or the processor is halted
39
--                  i.e. a DMA grant.
40
-- 
41
--  Copyright (C) 2003 - 2010 John Kent
42
--
43
--  This program is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
52
--
53
--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
55
--
56
--===========================================================================--
57
--                                                                           --
58
--                                Revision History                           --
59
--                                                                           --
60
--===========================================================================--
61
--
62
-- Version 0.1 - 26 June 2003 - John Kent
63
-- Added extra level in state stack
64
-- fixed some calls to the extended addressing state
65
--
66
-- Version 0.2 - 5 Sept 2003 - John Kent
67
-- Fixed 16 bit indexed offset (was doing read rather than fetch)
68
-- Added/Fixed STY and STS instructions.
69
-- ORCC_STATE ANDed CC state rather than ORed it - Now fixed
70
-- CMPX Loaded ACCA and ACCB - Now fixed 
71
--
72
-- Version 1.0 - 6 Sep 2003 - John Kent 
73
-- Initial release to Open Cores
74
-- reversed clock edge
75
--
76
-- Version 1.1 - 29 November 2003 John kent
77
--      ACCA and ACCB indexed offsets are 2's complement.
78
-- ALU Right Mux now sign extends ACCA & ACCB offsets
79
-- Absolute Indirect addressing performed a read on the
80
-- second byte of the address rather than a fetch
81
-- so it formed an incorrect address. Now fixed. 
82
--
83
-- Version 1.2 - 29 November 2003 John Kent
84
-- LEAX and LEAY affect the Z bit only
85
--      LEAS and LEAU do not affect any condition codes
86
-- added an extra ALU control for LEA.
87
--
88
-- Version 1.3 - 12 December 2003 John Kent
89
-- CWAI did not work, was missed a PUSH_ST on calling
90
-- the ANDCC_STATE. Thanks go to Ghassan Kraidy for
91
-- finding this fault.
92
--
93
-- Version 1.4 - 12 December 2003 John Kent
94
-- Missing cc_ctrl assignment in otherwise case of 
95
-- lea_state resulted in cc_ctrl being latched in
96
-- that state.  
97
-- The otherwise statement should never be reached,
98
-- and has been fixed simply to resolve synthesis warnings.
99
--
100
-- Version 1.5 - 17 january 2004 John kent
101
-- The clear instruction used "alu_ld8" to control the ALU
102
-- rather than "alu_clr". This mean the Carry was not being
103
-- cleared correctly.
104
--
105
-- Version 1.6 - 24 January 2004 John Kent
106
-- Fixed problems in PSHU instruction
107
--
108
-- Version 1.7 - 25 January 2004 John Kent
109
-- removed redundant "alu_inx" and "alu_dex'
110
-- Removed "test_alu" and "test_cc"
111
-- STD instruction did not set condition codes
112
-- JMP direct was not decoded properly
113
-- CLR direct performed an unwanted read cycle
114
-- Bogus "latch_md" in Page2 indexed addressing
115
--
116
-- Version 1.8 - 27 January 2004 John Kent
117
-- CWAI in decode1_state should increment the PC.
118
-- ABX is supposed to be an unsigned addition.
119
-- Added extra ALU function
120
-- ASR8 slightly changed in the ALU.
121
--
122
--      Version 1.9 - 20 August 2005
123
-- LSR8 is now handled in ASR8 and ROR8 case in the ALU,
124
-- rather than LSR16. There was a problem with single 
125
-- operand instructions using the MD register which is
126
-- sign extended on the first 8 bit fetch.
127
--
128
-- Version 1.10 - 13 September 2005
129
-- TFR & EXG instructions did not work for the Condition Code Register
130
-- An extra case has been added to the ALU for the alu_tfr control 
131
-- to assign the left ALU input (alu_left) to the condition code
132
-- outputs (cc_out). 
133
--
134
-- Version 1.11 - 16 September 2005
135
-- JSR ,X should not predecrement S before calculating the jump address.
136
-- The reason is that JSR [0,S] needs S to point to the top of the stack
137
-- to fetch a valid vector address. The solution is to have the addressing
138
-- mode microcode called before decrementing S and then decrementing S in
139
-- JSR_STATE. JSR_STATE in turn calls PUSH_RETURN_LO_STATE rather than
140
-- PUSH_RETURN_HI_STATE so that both the High & Low halves of the PC are
141
-- pushed on the stack. This adds one extra bus cycle, but resolves the
142
-- addressing conflict. I've also removed the pre-decement S in 
143
-- JSR EXTENDED as it also calls JSR_STATE.
144
--
145
-- Version 1.12 - 6th June 2006
146
-- 6809 Programming reference manual says V is not affected by ASR, LSR and ROR
147
-- This is different to the 6800. CLR should reset the V bit.
148
--
149
-- Version 1.13 - 7th July 2006
150
-- Disable NMI on reset until S Stack pointer has been loaded.
151
-- Added nmi_enable signal in sp_reg process and nmi_handler process.
152
--
153
-- Version 1.14 - 11th July 2006
154
-- 1. Added new state to RTI called rti_entire_state.
155
-- This state tests the CC register after it has been loaded
156
-- from the stack. Previously the current CC was tested which
157
-- was incorrect. The Entire Flag should be set before the
158
-- interrupt stacks the CC.
159
-- 2. On bogus Interrupts, int_cc_state went to rti_state,
160
-- which was an enumerated state, but not defined anywhere.
161
-- rti_state has been changed to rti_cc_state so that bogus interrupt
162
-- will perform an RTI after entering that state.
163
-- 3. Sync should generate an interrupt if the interrupt masks
164
-- are cleared. If the interrupt masks are set, then an interrupt
165
-- will cause the the PC to advance to the next instruction.
166
-- Note that I don't wait for an interrupt to be asserted for
167
-- three clock cycles.
168
-- 4. Added new ALU control state "alu_mul". "alu_mul" is used in
169
-- the Multiply instruction replacing "alu_add16". This is similar 
170
-- to "alu_add16" except it sets the Carry bit to B7 of the result
171
-- in ACCB, sets the Zero bit if the 16 bit result is zero, but
172
-- does not affect The Half carry (H), Negative (N) or Overflow (V)
173
-- flags. The logic was re-arranged so that it adds md or zero so 
174
-- that the Carry condition code is set on zero multiplicands.
175
-- 5. DAA (Decimal Adjust Accumulator) should set the Negative (N)
176
-- and Zero Flags. It will also affect the Overflow (V) flag although
177
-- the operation is undefined. It's anyones guess what DAA does to V.
178
--
179
-- Version 1.15 - 25th Feb 2007 - John Kent
180
-- line 9672 changed "if Halt <= '1' then" to "if Halt = '1' then"
181
-- Changed sensitivity lists.
182
--
183
-- Version 1.16 - 5th February 2008 - John Kent
184
-- FIRQ interrupts should take priority over IRQ Interrupts.
185
-- This presumably means they should be tested for before IRQ
186
-- when they happen concurrently.
187
--
188
-- Version 1.17 - 18th February 2008 - John Kent
189
-- NMI in CWAI should mask IRQ and FIRQ interrupts
190
--
191
-- Version 1.18 - 21st February 2008 - John Kent
192
-- Removed default register settings in each case statement
193
-- and placed them at the beginning of the state sequencer.
194
-- Modified the SYNC instruction so that the interrupt vector(iv)
195
-- is not set unless an unmasked FIRQ or IRQ is received.
196
--
197
-- Version 1.19 - 25th February 2008 - John Kent
198
-- Enumerated separate states for FIRQ/FAST and NMIIRQ/ENTIRE
199
-- Enumerated separate states for MASKI and MASKIF states
200
-- Removed code on BSR/JSR in fetch cycle
201
--
202
-- Version 1.20 - 8th October 2011 - John Kent
203
-- added fetch output which should go high during the fetch cycle
204
--
205
-- Version 1.21 - 8th October 2011 - John Kent
206
-- added Last Instruction Cycle signal
207
-- replaced fetch with ifetch (instruction fetch) signal
208
-- added ba & bs (bus available & bus status) signals
209
--
210
-- Version 1.22 - 2011-10-29 John Kent
211
-- The halt state isn't correct. 
212
-- The halt state is entered into from the fetch_state
213
-- It returned to the fetch state which may re-run an execute cycle
214
-- on the accumulator and it won't necessarily be the last instruction cycle
215
-- I've changed the halt state to return to the decode1_state
216
--
217
-- Version 1.23 - 2011-10-30 John Kent
218
-- sample halt in the change_state process if lic is high (last instruction cycle)
219
--
220
-- Version 1.24 - 2011-11-01 John Kent
221
-- Handle interrupts in change_state process
222
-- Sample interrupt inputs on last instruction cycle
223
-- Remove iv_ctrl and implement iv (interrupt vector) in change_state process.
224
-- Generate fic (first instruction cycle) from lic (last instruction cycle)
225
-- and use it to complete the dual operand execute cycle before servicing
226
-- halt or interrupts requests.
227
-- rename lic to lic_out on the entity declaration so that lic can be tested internally.
228
-- add int_firq1_state and int_nmirq1_state to allow for the dual operand execute cycle
229
-- integrated nmi_ctrl into change_state process
230
-- Reduces the microcode state stack to one entry (saved_state)
231
-- imm16_state jumps directly to the fetch_state
232
-- pull_return_lo states jumps directly to the fetch_state
233
-- duplicate andcc_state as cwai_state
234
-- rename exg1_state as exg2 state and duplicate tfr_state as exg1_state
235
--
236
-- Version 1.25 - 2011-11-27 John Kent
237
-- Changed the microcode for saving registers on an interrupt into a microcode subroutine.
238
-- Removed SWI servicing from the change state process and made SWI, SWI2 & SWI3
239
-- call the interrupt microcode subroutine.
240
-- Added additional states for nmi, and irq for interrupt servicing.
241
-- Added additional states for nmi/irq, firq, and swi interrupts to mask I & F flags.
242
--
243
-- Version 1.26 - 2013-03-18 John Kent
244
-- pre-initialized cond_true variable to true in state sequencer
245
-- re-arranged change_state process slightly
246
--
247
-- Version 1.27 - 2015-05-30 John Kent
248
-- Added test in state machine for masked IRQ and FIRQ in Sync_state.
249
--
250
-- Version 1.28 - 2015-05-30 John Kent.
251
-- Moved IRQ and FIRQ test from state machine to the state sequencer Sync_state.
252
--
253
-- Version 1.29 - 2017-02-11 John Kent
254
-- Make MUL 11 cycles long rather than 13 cycles.
255
-- 1 fetch_state, 2 decode1_state, 
256
-- 3 mul_state, 4 mulea_state, 5 muld_state
257
-- 6 mul0_state, 7 mul1_state, 8 mul2_state, 9 mul3_state,
258
-- 10 mul4_state, 11 mul5_state, 12 mul6_state, 13 mul7_state,
259
-- move mul_state into decode1_state
260
-- move mul7_state into fetch_state
261
--
262
-- Version 1.29 - 2017-03-08 John Kent.
263
-- Moved LIC in ABX ?
264
--
265
-- Version 1.30 -2018-01-13 John Kent
266
-- cpu09n.vhd
267
-- replace decode1_state, decode2_state and decode3_state
268
-- with the one decode_state.
269
-- $10 $4F = $4F = CLRA on a real MC6809.
270
-- $10 4F = CLRD on a HD6309
271
--
272
library ieee;
273
use ieee.std_logic_1164.all;
274
use ieee.std_logic_unsigned.all;
275
 
276
entity cpu09 is
277
        port (
278
                clk      :      in std_logic;                     -- E clock input (falling edge)
279
                rst      :  in std_logic;                     -- reset input (active high)
280
                vma      : out std_logic;                     -- valid memory address (active high)
281
      lic_out  : out std_logic;                     -- last instruction cycle (active high)
282
      ifetch   : out std_logic;                     -- instruction fetch cycle (active high)
283
      opfetch  : out std_logic;                     -- opcode fetch (active high)
284
      ba       : out std_logic;                     -- bus available (high on sync wait or DMA grant)
285
      bs       : out std_logic;                     -- bus status (high on interrupt or reset vector fetch or DMA grant)
286
                addr     : out std_logic_vector(15 downto 0); -- address bus output
287
                rw       : out std_logic;                     -- read not write output
288
           data_out : out std_logic_vector(7 downto 0);  -- data bus output
289
           data_in  :  in std_logic_vector(7 downto 0);  -- data bus input
290
                irq      :  in std_logic;                     -- interrupt request input (active high)
291
                firq     :  in std_logic;                     -- fast interrupt request input (active high)
292
                nmi      :  in std_logic;                     -- non maskable interrupt request input (active high)
293
                halt     :  in std_logic;                     -- halt input (active high) grants DMA
294
                hold     :  in std_logic                      -- hold input (active high) extend bus cycle
295
                );
296
end cpu09;
297
 
298
architecture rtl of cpu09 is
299
 
300
  constant EBIT : integer := 7;
301
  constant FBIT : integer := 6;
302
  constant HBIT : integer := 5;
303
  constant IBIT : integer := 4;
304
  constant NBIT : integer := 3;
305
  constant ZBIT : integer := 2;
306
  constant VBIT : integer := 1;
307
  constant CBIT : integer := 0;
308
 
309
  --
310
  -- Interrupt vector modifiers
311
  --
312
  constant RST_VEC  : std_logic_vector(2 downto 0) := "111";
313
  constant NMI_VEC  : std_logic_vector(2 downto 0) := "110";
314
  constant SWI_VEC  : std_logic_vector(2 downto 0) := "101";
315
  constant IRQ_VEC  : std_logic_vector(2 downto 0) := "100";
316
  constant FIRQ_VEC : std_logic_vector(2 downto 0) := "011";
317
  constant SWI2_VEC : std_logic_vector(2 downto 0) := "010";
318
  constant SWI3_VEC : std_logic_vector(2 downto 0) := "001";
319
  constant RESV_VEC : std_logic_vector(2 downto 0) := "000";
320
 
321
        type state_type is (-- Start off in Reset
322
                            reset_state,
323
                                                          -- Fetch Interrupt Vectors (including reset)
324
                                                          vect_lo_state, vect_hi_state, vect_idle_state,
325
                       -- Fetch Instruction Cycle
326
                       fetch_state,
327
                                                          -- Decode Instruction Cycles
328
                       decode_state,
329
                                                          -- Calculate Effective Address
330
                                                     imm16_state,
331
                                 indexed_state, index8_state, index16_state, index16_2_state,
332
                                                          pcrel8_state, pcrel16_state, pcrel16_2_state,
333
                                                          indexaddr_state, indexaddr2_state,
334
                                                     postincr1_state, postincr2_state,
335
                                                          indirect_state, indirect2_state, indirect3_state,
336
                       extended_state,
337
                                                          -- single ops
338
                                                          single_op_read_state,
339
                                                     single_op_exec_state,
340
                            single_op_write_state,
341
                                                          -- Dual op states
342
                                                          dual_op_read8_state, dual_op_read16_state, dual_op_read16_2_state,
343
                                                     dual_op_write8_state, dual_op_write16_state,
344
                       -- 
345
                                                     sync_state, halt_state, cwai_state,
346
                                                          --
347
                                                          andcc_state, orcc_state,
348
                                                          tfr_state,
349
                       exg_state, exg1_state, exg2_state,
350
                                                          lea_state,
351
                                                          -- Multiplication
352
                                                     mulea_state, muld_state,
353
                                                     mul0_state, mul1_state, mul2_state, mul3_state,
354
                                                     mul4_state, mul5_state, mul6_state,
355
                                                          --  Branches
356
                                                          lbranch_state, sbranch_state,
357
                                                          -- Jumps, Subroutine Calls and Returns
358
                       jsr_state, jmp_state,
359
                       push_return_hi_state, push_return_lo_state,
360
                       pull_return_hi_state, pull_return_lo_state,
361
                                                          -- Interrupt cycles
362
                                                          int_nmi_state, int_nmi1_state,
363
                                                          int_irq_state, int_irq1_state,
364
                       int_firq_state,  int_firq1_state,
365
                                                          int_entire_state, int_fast_state,
366
                                                          int_pcl_state,  int_pch_state,
367
                                                     int_upl_state,  int_uph_state,
368
                                                     int_iyl_state,  int_iyh_state,
369
                                                     int_ixl_state,  int_ixh_state,
370
                                                     int_dp_state,
371
                                           int_accb_state, int_acca_state,
372
                                                     int_cc_state,
373
                                                     int_cwai_state,
374
                                                          int_nmimask_state, int_firqmask_state, int_swimask_state, int_irqmask_state,
375
                                                          -- Return From Interrupt
376
                                                     rti_cc_state,   rti_entire_state,
377
                                                          rti_acca_state, rti_accb_state,
378
                                                     rti_dp_state,
379
                                                     rti_ixl_state,  rti_ixh_state,
380
                                                     rti_iyl_state,  rti_iyh_state,
381
                                                     rti_upl_state,  rti_uph_state,
382
                                                     rti_pcl_state,  rti_pch_state,
383
                                                          -- Push Registers using SP
384
                                                          pshs_state,
385
                                                     pshs_pcl_state,  pshs_pch_state,
386
                                                     pshs_upl_state,  pshs_uph_state,
387
                                                     pshs_iyl_state,  pshs_iyh_state,
388
                                                     pshs_ixl_state,  pshs_ixh_state,
389
                                                     pshs_dp_state,
390
                                                     pshs_acca_state, pshs_accb_state,
391
                                                     pshs_cc_state,
392
                                                          -- Pull Registers using SP
393
                                                          puls_state,
394
                                                          puls_cc_state,
395
                                                          puls_acca_state, puls_accb_state,
396
                                                          puls_dp_state,
397
                                                     puls_ixl_state,  puls_ixh_state,
398
                                                     puls_iyl_state,  puls_iyh_state,
399
                                                     puls_upl_state,  puls_uph_state,
400
                                                     puls_pcl_state,  puls_pch_state,
401
                                                          -- Push Registers using UP
402
                                                          pshu_state,
403
                                                     pshu_pcl_state,  pshu_pch_state,
404
                                                     pshu_spl_state,  pshu_sph_state,
405
                                                     pshu_iyl_state,  pshu_iyh_state,
406
                                                     pshu_ixl_state,  pshu_ixh_state,
407
                                                     pshu_dp_state,
408
                                                     pshu_acca_state, pshu_accb_state,
409
                                                     pshu_cc_state,
410
                                                          -- Pull Registers using UP
411
                                                          pulu_state,
412
                                                          pulu_cc_state,
413
                                                          pulu_acca_state, pulu_accb_state,
414
                                                          pulu_dp_state,
415
                                                     pulu_ixl_state,  pulu_ixh_state,
416
                                                     pulu_iyl_state,  pulu_iyh_state,
417
                                                     pulu_spl_state,  pulu_sph_state,
418
                                                     pulu_pcl_state,  pulu_pch_state );
419
 
420
        type st_type    is (reset_st, push_st, idle_st );
421
        type iv_type    is (latch_iv, swi3_iv, swi2_iv, firq_iv, irq_iv, swi_iv, nmi_iv, reset_iv);
422
        type addr_type  is (idle_ad, fetch_ad, read_ad, write_ad, pushu_ad, pullu_ad, pushs_ad, pulls_ad, int_hi_ad, int_lo_ad );
423
        type dout_type  is (cc_dout, acca_dout, accb_dout, dp_dout,
424
                       ix_lo_dout, ix_hi_dout, iy_lo_dout, iy_hi_dout,
425
                       up_lo_dout, up_hi_dout, sp_lo_dout, sp_hi_dout,
426
                       pc_lo_dout, pc_hi_dout, md_lo_dout, md_hi_dout );
427
   type op_type    is (reset_op, fetch_op, latch_op );
428
   type pre_type   is (reset_pre, fetch_pre, load_pre, latch_pre );
429
   type cc_type    is (reset_cc, load_cc, pull_cc, latch_cc );
430
   type acca_type  is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca );
431
   type accb_type  is (reset_accb, load_accb, pull_accb, latch_accb );
432
   type dp_type    is (reset_dp, load_dp, pull_dp, latch_dp );
433
        type ix_type    is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix );
434
        type iy_type    is (reset_iy, load_iy, pull_lo_iy, pull_hi_iy, latch_iy );
435
        type sp_type    is (reset_sp, latch_sp, load_sp, pull_hi_sp, pull_lo_sp );
436
        type up_type    is (reset_up, latch_up, load_up, pull_hi_up, pull_lo_up );
437
        type pc_type    is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc, incr_pc );
438
   type md_type    is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md );
439
   type ea_type    is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea );
440
        type left_type  is (cc_left, acca_left, accb_left, dp_left,
441
                                                          ix_left, iy_left, up_left, sp_left,
442
                       accd_left, md_left, pc_left, ea_left );
443
        type right_type is (ea_right, zero_right, one_right, two_right,
444
                       acca_right, accb_right, accd_right,
445
                                                          md_right, md_sign5_right, md_sign8_right );
446
   type alu_type   is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc,
447
                       alu_and, alu_ora, alu_eor,
448
                       alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com,
449
                                                     alu_lsr16, alu_lsl16,
450
                                                     alu_ror8, alu_rol8, alu_mul,
451
                                                     alu_asr8, alu_asl8, alu_lsr8,
452
                                                     alu_andcc, alu_orcc, alu_sex, alu_tfr, alu_abx,
453
                                                          alu_seif, alu_sei, alu_see, alu_cle,
454
                                                     alu_ld8, alu_st8, alu_ld16, alu_st16, alu_lea, alu_nop, alu_daa );
455
 
456
        signal op_code:     std_logic_vector(7 downto 0);
457
        signal pre_code:    std_logic_vector(7 downto 0);
458
        signal acca:        std_logic_vector(7 downto 0);
459
        signal accb:        std_logic_vector(7 downto 0);
460
   signal cc:          std_logic_vector(7 downto 0);
461
        signal cc_out:      std_logic_vector(7 downto 0);
462
        signal dp:          std_logic_vector(7 downto 0);
463
        signal xreg:        std_logic_vector(15 downto 0);
464
        signal yreg:        std_logic_vector(15 downto 0);
465
        signal sp:          std_logic_vector(15 downto 0);
466
        signal up:          std_logic_vector(15 downto 0);
467
        signal ea:          std_logic_vector(15 downto 0);
468
        signal pc:              std_logic_vector(15 downto 0);
469
        signal md:          std_logic_vector(15 downto 0);
470
   signal left:        std_logic_vector(15 downto 0);
471
   signal right:       std_logic_vector(15 downto 0);
472
        signal out_alu:     std_logic_vector(15 downto 0);
473
        signal iv:          std_logic_vector(2 downto 0);
474
        signal nmi_req:     std_logic;
475
        signal nmi_ack:     std_logic;
476
        signal nmi_enable:  std_logic;
477
   signal fic:         std_logic; -- first instruction cycle
478
   signal lic:         std_logic; -- last instruction cycle
479
 
480
        signal state:        state_type;
481
        signal next_state:   state_type;
482
        signal return_state: state_type;
483
        signal saved_state:  state_type;
484
        signal st_ctrl:      st_type;
485
        signal iv_ctrl:      iv_type;
486
   signal pc_ctrl:      pc_type;
487
   signal ea_ctrl:      ea_type;
488
   signal op_ctrl:      op_type;
489
        signal pre_ctrl:     pre_type;
490
        signal md_ctrl:      md_type;
491
        signal acca_ctrl:    acca_type;
492
        signal accb_ctrl:    accb_type;
493
        signal ix_ctrl:      ix_type;
494
        signal iy_ctrl:      iy_type;
495
        signal cc_ctrl:      cc_type;
496
        signal dp_ctrl:      dp_type;
497
        signal sp_ctrl:      sp_type;
498
        signal up_ctrl:      up_type;
499
        signal left_ctrl:    left_type;
500
        signal right_ctrl:   right_type;
501
   signal alu_ctrl:     alu_type;
502
   signal addr_ctrl:    addr_type;
503
   signal dout_ctrl:    dout_type;
504
 
505
 
506
begin
507
 
508
----------------------------------
509
--
510
-- State machine stack
511
--
512
----------------------------------
513
--state_stack_proc: process( clk, hold, state_stack, st_ctrl, 
514
--                           return_state, fetch_state  )
515
state_stack_proc: process( clk, st_ctrl, return_state )
516
begin
517
  if clk'event and clk = '0' then
518
    if hold = '0' then
519
           case st_ctrl is
520
      when reset_st =>
521
        saved_state <= fetch_state;
522
      when push_st =>
523
                  saved_state <= return_state;
524
                when others =>
525
        null;
526
           end case;
527
    end if;
528
  end if;
529
end process;
530
 
531
----------------------------------
532
--
533
-- Interrupt Vector control
534
--
535
----------------------------------
536
--
537
int_vec_proc: process( clk, iv_ctrl )
538
begin
539
  if clk'event and clk = '0' then
540
    if hold = '0' then
541
      case iv_ctrl is
542
      when reset_iv =>
543
        iv <= RST_VEC;
544
      when nmi_iv =>
545
        iv <= NMI_VEC;
546
      when swi_iv =>
547
        iv <= SWI_VEC;
548
      when irq_iv =>
549
        iv <= IRQ_VEC;
550
      when firq_iv =>
551
        iv <= FIRQ_VEC;
552
      when swi2_iv =>
553
        iv <= SWI2_VEC;
554
      when swi3_iv =>
555
        iv <= SWI3_VEC;
556
                when others =>
557
                  null;
558
      end case;
559
    end if; -- hold
560
  end if; -- clk
561
end process;
562
 
563
----------------------------------
564
--
565
-- Program Counter Control
566
--
567
----------------------------------
568
 
569
--pc_reg: process( clk, pc_ctrl, hold, pc, out_alu, data_in )
570
pc_reg: process( clk )
571
begin
572
  if clk'event and clk = '0' then
573
    if hold = '0' then
574
    case pc_ctrl is
575
         when reset_pc =>
576
           pc <= (others=>'0');
577
         when load_pc =>
578
           pc <= out_alu(15 downto 0);
579
         when pull_lo_pc =>
580
           pc(7 downto 0) <= data_in;
581
         when pull_hi_pc =>
582
           pc(15 downto 8) <= data_in;
583
         when incr_pc =>
584
           pc <= pc + 1;
585
         when others =>
586
      null;
587
    end case;
588
         end if;
589
  end if;
590
end process;
591
 
592
----------------------------------
593
--
594
-- Effective Address  Control
595
--
596
----------------------------------
597
 
598
--ea_reg: process( clk, ea_ctrl, hold, ea, out_alu, data_in, dp )
599
ea_reg: process( clk )
600
begin
601
 
602
  if clk'event and clk = '0' then
603
    if hold= '0' then
604
    case ea_ctrl is
605
         when reset_ea =>
606
           ea <= (others=>'0');
607
         when fetch_first_ea =>
608
           ea(7 downto 0) <= data_in;
609
      ea(15 downto 8) <= dp;
610
         when fetch_next_ea =>
611
           ea(15 downto 8) <= ea(7 downto 0);
612
      ea(7 downto 0)  <= data_in;
613
         when load_ea =>
614
           ea <= out_alu(15 downto 0);
615
         when others =>
616
      null;
617
    end case;
618
         end if;
619
  end if;
620
end process;
621
 
622
--------------------------------
623
--
624
-- Accumulator A
625
--
626
--------------------------------
627
--acca_reg : process( clk, acca_ctrl, hold, out_alu, acca, data_in )
628
acca_reg : process( clk )
629
begin
630
  if clk'event and clk = '0' then
631
    if hold = '0' then
632
    case acca_ctrl is
633
    when reset_acca =>
634
           acca <= (others=>'0');
635
         when load_acca =>
636
           acca <= out_alu(7 downto 0);
637
         when load_hi_acca =>
638
           acca <= out_alu(15 downto 8);
639
         when pull_acca =>
640
           acca <= data_in;
641
         when others =>
642
      null;
643
    end case;
644
         end if;
645
  end if;
646
end process;
647
 
648
--------------------------------
649
--
650
-- Accumulator B
651
--
652
--------------------------------
653
--accb_reg : process( clk, accb_ctrl, hold, out_alu, accb, data_in )
654
accb_reg : process( clk )
655
begin
656
  if clk'event and clk = '0' then
657
    if hold = '0' then
658
    case accb_ctrl is
659
    when reset_accb =>
660
           accb <= (others=>'0');
661
         when load_accb =>
662
           accb <= out_alu(7 downto 0);
663
         when pull_accb =>
664
           accb <= data_in;
665
         when others =>
666
      null;
667
    end case;
668
         end if;
669
  end if;
670
end process;
671
 
672
--------------------------------
673
--
674
-- X Index register
675
--
676
--------------------------------
677
--ix_reg : process( clk, ix_ctrl, hold, out_alu, xreg, data_in )
678
ix_reg : process( clk )
679
begin
680
  if clk'event and clk = '0' then
681
    if hold = '0' then
682
    case ix_ctrl is
683
    when reset_ix =>
684
           xreg <= (others=>'0');
685
         when load_ix =>
686
           xreg <= out_alu(15 downto 0);
687
         when pull_hi_ix =>
688
           xreg(15 downto 8) <= data_in;
689
         when pull_lo_ix =>
690
           xreg(7 downto 0) <= data_in;
691
         when others =>
692
      null;
693
    end case;
694
         end if;
695
  end if;
696
end process;
697
 
698
--------------------------------
699
--
700
-- Y Index register
701
--
702
--------------------------------
703
--iy_reg : process( clk, iy_ctrl, hold, out_alu, yreg, data_in )
704
iy_reg : process( clk )
705
begin
706
  if clk'event and clk = '0' then
707
    if hold = '0' then
708
    case iy_ctrl is
709
    when reset_iy =>
710
           yreg <= (others=>'0');
711
         when load_iy =>
712
           yreg <= out_alu(15 downto 0);
713
         when pull_hi_iy =>
714
           yreg(15 downto 8) <= data_in;
715
         when pull_lo_iy =>
716
           yreg(7 downto 0) <= data_in;
717
         when others =>
718
      null;
719
    end case;
720
         end if;
721
  end if;
722
end process;
723
 
724
--------------------------------
725
--
726
-- S stack pointer
727
--
728
--------------------------------
729
--sp_reg : process( clk, sp_ctrl, hold, sp, out_alu, data_in, nmi_enable )
730
sp_reg : process( clk )
731
begin
732
  if clk'event and clk = '0' then
733
    if hold = '0' then
734
    case sp_ctrl is
735
    when reset_sp =>
736
           sp <= (others=>'0');
737
                nmi_enable <= '0';
738
         when load_sp =>
739
           sp <= out_alu(15 downto 0);
740
                nmi_enable <= '1';
741
         when pull_hi_sp =>
742
           sp(15 downto 8) <= data_in;
743
         when pull_lo_sp =>
744
           sp(7 downto 0) <= data_in;
745
                nmi_enable <= '1';
746
         when others =>
747
      null;
748
    end case;
749
         end if;
750
  end if;
751
end process;
752
 
753
--------------------------------
754
--
755
-- U stack pointer
756
--
757
--------------------------------
758
--up_reg : process( clk, up_ctrl, hold, up, out_alu, data_in )
759
up_reg : process( clk )
760
begin
761
  if clk'event and clk = '0' then
762
    if hold = '0' then
763
    case up_ctrl is
764
    when reset_up =>
765
           up <= (others=>'0');
766
         when load_up =>
767
           up <= out_alu(15 downto 0);
768
         when pull_hi_up =>
769
           up(15 downto 8) <= data_in;
770
         when pull_lo_up =>
771
           up(7 downto 0) <= data_in;
772
         when others =>
773
      null;
774
    end case;
775
         end if;
776
  end if;
777
end process;
778
 
779
--------------------------------
780
--
781
-- Memory Data
782
--
783
--------------------------------
784
--md_reg : process( clk, md_ctrl, hold, out_alu, data_in, md )
785
md_reg : process( clk )
786
begin
787
  if clk'event and clk = '0' then
788
    if hold = '0' then
789
    case md_ctrl is
790
    when reset_md =>
791
           md <= (others=>'0');
792
         when load_md =>
793
           md <= out_alu(15 downto 0);
794
         when fetch_first_md => -- sign extend md for branches
795
           md(15 downto 8) <= data_in(7) & data_in(7) & data_in(7) & data_in(7) &
796
                              data_in(7) & data_in(7) & data_in(7) & data_in(7) ;
797
           md(7 downto 0) <= data_in;
798
         when fetch_next_md =>
799
           md(15 downto 8) <= md(7 downto 0);
800
                md(7 downto 0) <= data_in;
801
         when shiftl_md =>
802
           md(15 downto 1) <= md(14 downto 0);
803
                md(0) <= '0';
804
         when others =>
805
      null;
806
    end case;
807
         end if;
808
  end if;
809
end process;
810
 
811
 
812
----------------------------------
813
--
814
-- Condition Codes
815
--
816
----------------------------------
817
 
818
--cc_reg: process( clk, cc_ctrl, hold, cc_out, cc, data_in )
819
cc_reg: process( clk )
820
begin
821
  if clk'event and clk = '0' then
822
    if hold = '0' then
823
    case cc_ctrl is
824
         when reset_cc =>
825
           cc <= "11010000"; -- set EBIT, FBIT & IBIT
826
         when load_cc =>
827
           cc <= cc_out;
828
         when pull_cc =>
829
      cc <= data_in;
830
         when others =>
831
      null;
832
    end case;
833
         end if;
834
  end if;
835
end process;
836
 
837
----------------------------------
838
--
839
-- Direct Page register
840
--
841
----------------------------------
842
 
843
--dp_reg: process( clk, dp_ctrl, hold, out_alu, dp, data_in )
844
dp_reg: process( clk )
845
begin
846
  if clk'event and clk = '0' then
847
    if hold = '0' then
848
    case dp_ctrl is
849
         when reset_dp =>
850
           dp <= (others=>'0');
851
         when load_dp =>
852
           dp <= out_alu(7 downto 0);
853
         when pull_dp =>
854
      dp <= data_in;
855
         when others =>
856
      null;
857
    end case;
858
         end if;
859
  end if;
860
end process;
861
 
862
 
863
----------------------------------
864
--
865
-- op code register
866
--
867
----------------------------------
868
 
869
--op_reg: process( clk, op_ctrl, hold, op_code, data_in )
870
op_reg: process( clk )
871
begin
872
  if clk'event and clk = '0' then
873
    if hold = '0' then
874
    case op_ctrl is
875
         when reset_op =>
876
           op_code <= "00010010";
877
         when fetch_op =>
878
      op_code <= data_in;
879
         when others =>
880
      null;
881
    end case;
882
         end if;
883
  end if;
884
end process;
885
 
886
 
887
----------------------------------
888
--
889
-- pre byte op code register
890
--
891
----------------------------------
892
 
893
--pre_reg: process( clk, pre_ctrl, hold, pre_code, data_in )
894
pre_reg: process( clk )
895
begin
896
  if clk'event and clk = '0' then
897
    if hold = '0' then
898
    case pre_ctrl is
899
         when reset_pre =>
900
           pre_code <= (others=>'0');
901
         when fetch_pre =>
902
      pre_code <= data_in;
903
    when load_pre =>
904
                pre_code <= op_code;
905
         when others =>
906
      null;
907
    end case;
908
         end if;
909
  end if;
910
end process;
911
 
912
--------------------------------
913
--
914
-- state machine
915
--
916
--------------------------------
917
 
918
--change_state: process( clk, rst, state, hold, next_state )
919
change_state: process( clk )
920
begin
921
  if clk'event and clk = '0' then
922
    if rst = '1' then
923
      fic     <= '0';
924
           nmi_ack <= '0';
925
           state   <= reset_state;
926
    elsif hold = '0' then
927
                  fic <= lic;
928
                  --
929
                  -- nmi request is not cleared until nmi input goes low
930
                  --
931
                  if (nmi_req = '0') and (nmi_ack='1') then
932
          nmi_ack <= '0';
933
                  end if;
934
 
935
                  if (nmi_req = '1') and (nmi_ack = '0')  and (state = int_nmimask_state) then
936
          nmi_ack <= '1';
937
                  end if;
938
 
939
        if lic = '1'  then
940
          if halt = '1' then
941
                           state <= halt_state;
942
 
943
          -- service non maskable interrupts
944
          elsif (nmi_req = '1') and (nmi_ack = '0') then
945
                           state <= int_nmi_state;
946
                                 --
947
                                 -- FIRQ & IRQ are level sensitive
948
                                 --
949
          elsif (firq = '1') and (cc(FBIT) = '0') then
950
                           state  <= int_firq_state;
951
 
952
                         elsif (irq = '1') and (cc(IBIT) = '0') then
953
                           state <= int_irq_state;
954
                         --
955
                         -- Version 1.27 2015-05-30
956
                         -- Exit sync_state on masked interrupt.
957
                         --
958
                         -- Version 1.28 2015-05-30
959
                         -- Move this code to the state sequencer
960
                         -- near line 5566.
961
                         --
962
                         -- elsif  (state = sync_state) and ((firq = '1') or (irq = '1'))then
963
                         --   state <= fetch_state;
964
          --
965
                         else
966
                           state <= next_state;
967
          end if; -- halt, nmi, firq, irq
968
                  else
969
                    state <= next_state;
970
        end if; -- lic
971
         end if; -- reset/hold
972
  end if; -- clk
973
end process;
974
 
975
------------------------------------
976
--
977
-- Detect Edge of NMI interrupt
978
--
979
------------------------------------
980
 
981
--nmi_handler : process( clk, rst, nmi, nmi_ack, nmi_req, nmi_enable )
982
nmi_handler : process( rst, clk )
983
begin
984
  if rst='1' then
985
         nmi_req <= '0';
986
  elsif clk'event and clk='0' then
987
           if (nmi='1') and (nmi_ack='0') and (nmi_enable='1') then
988
             nmi_req <= '1';
989
           else
990
                  if (nmi='0') and (nmi_ack='1') then
991
               nmi_req <= '0';
992
                  end if;
993
                end if;
994
  end if;
995
end process;
996
 
997
 
998
----------------------------------
999
--
1000
-- Address output multiplexer
1001
--
1002
----------------------------------
1003
 
1004
addr_mux: process( addr_ctrl, pc, ea, up, sp, iv )
1005
begin
1006
  ifetch <= '0';
1007
  vma    <= '1';
1008
  case addr_ctrl is
1009
    when fetch_ad =>
1010
           addr   <= pc;
1011
      rw     <= '1';
1012
      ifetch <= '1';
1013
         when read_ad =>
1014
           addr   <= ea;
1015
      rw     <= '1';
1016
    when write_ad =>
1017
           addr   <= ea;
1018
                rw     <= '0';
1019
         when pushs_ad =>
1020
           addr   <= sp;
1021
                rw     <= '0';
1022
    when pulls_ad =>
1023
           addr   <= sp;
1024
      rw     <= '1';
1025
         when pushu_ad =>
1026
           addr   <= up;
1027
                rw     <= '0';
1028
    when pullu_ad =>
1029
           addr   <= up;
1030
      rw     <= '1';
1031
         when int_hi_ad =>
1032
           addr   <= "111111111111" & iv & "0";
1033
      rw     <= '1';
1034
    when int_lo_ad =>
1035
           addr   <= "111111111111" & iv & "1";
1036
      rw     <= '1';
1037
         when others =>
1038
      addr   <= "1111111111111111";
1039
      rw     <= '1';
1040
      vma    <= '0';
1041
  end case;
1042
end process;
1043
 
1044
--------------------------------
1045
--
1046
-- Data Bus output
1047
--
1048
--------------------------------
1049
dout_mux : process( dout_ctrl, md, acca, accb, dp, xreg, yreg, sp, up, pc, cc )
1050
begin
1051
    case dout_ctrl is
1052
         when cc_dout => -- condition code register
1053
           data_out <= cc;
1054
         when acca_dout => -- accumulator a
1055
           data_out <= acca;
1056
         when accb_dout => -- accumulator b
1057
           data_out <= accb;
1058
         when dp_dout => -- direct page register
1059
           data_out <= dp;
1060
         when ix_lo_dout => -- X index reg
1061
           data_out <= xreg(7 downto 0);
1062
         when ix_hi_dout => -- X index reg
1063
           data_out <= xreg(15 downto 8);
1064
         when iy_lo_dout => -- Y index reg
1065
           data_out <= yreg(7 downto 0);
1066
         when iy_hi_dout => -- Y index reg
1067
           data_out <= yreg(15 downto 8);
1068
         when up_lo_dout => -- U stack pointer
1069
           data_out <= up(7 downto 0);
1070
         when up_hi_dout => -- U stack pointer
1071
           data_out <= up(15 downto 8);
1072
         when sp_lo_dout => -- S stack pointer
1073
           data_out <= sp(7 downto 0);
1074
         when sp_hi_dout => -- S stack pointer
1075
           data_out <= sp(15 downto 8);
1076
         when md_lo_dout => -- alu output
1077
           data_out <= md(7 downto 0);
1078
         when md_hi_dout => -- alu output
1079
           data_out <= md(15 downto 8);
1080
         when pc_lo_dout => -- low order pc
1081
           data_out <= pc(7 downto 0);
1082
         when pc_hi_dout => -- high order pc
1083
           data_out <= pc(15 downto 8);
1084
    end case;
1085
end process;
1086
 
1087
----------------------------------
1088
--
1089
-- Left Mux
1090
--
1091
----------------------------------
1092
 
1093
left_mux: process( left_ctrl, acca, accb, cc, dp, xreg, yreg, up, sp, pc, ea, md )
1094
begin
1095
  case left_ctrl is
1096
         when cc_left =>
1097
           left(15 downto 8) <= "00000000";
1098
                left(7 downto 0)  <= cc;
1099
         when acca_left =>
1100
           left(15 downto 8) <= "00000000";
1101
                left(7 downto 0)  <= acca;
1102
         when accb_left =>
1103
           left(15 downto 8) <= "00000000";
1104
                left(7 downto 0)  <= accb;
1105
         when dp_left =>
1106
           left(15 downto 8) <= "00000000";
1107
                left(7 downto 0)  <= dp;
1108
         when accd_left =>
1109
           left(15 downto 8) <= acca;
1110
                left(7 downto 0)  <= accb;
1111
         when md_left =>
1112
           left <= md;
1113
         when ix_left =>
1114
           left <= xreg;
1115
         when iy_left =>
1116
           left <= yreg;
1117
         when sp_left =>
1118
           left <= sp;
1119
         when up_left =>
1120
           left <= up;
1121
         when pc_left =>
1122
           left <= pc;
1123
         when others =>
1124
--       when ea_left =>
1125
           left <= ea;
1126
    end case;
1127
end process;
1128
 
1129
----------------------------------
1130
--
1131
-- Right Mux
1132
--
1133
----------------------------------
1134
 
1135
right_mux: process( right_ctrl, md, acca, accb, ea )
1136
begin
1137
  case right_ctrl is
1138
         when ea_right =>
1139
           right <= ea;
1140
         when zero_right =>
1141
           right <= "0000000000000000";
1142
         when one_right =>
1143
           right <= "0000000000000001";
1144
         when two_right =>
1145
           right <= "0000000000000010";
1146
         when acca_right =>
1147
           if acca(7) = '0' then
1148
             right <= "00000000" & acca(7 downto 0);
1149
                else
1150
                  right <= "11111111" & acca(7 downto 0);
1151
                end if;
1152
         when accb_right =>
1153
           if accb(7) = '0' then
1154
             right <= "00000000" & accb(7 downto 0);
1155
                else
1156
                  right <= "11111111" & accb(7 downto 0);
1157
                end if;
1158
         when accd_right =>
1159
           right <= acca & accb;
1160
         when md_sign5_right =>
1161
           if md(4) = '0' then
1162
             right <= "00000000000" & md(4 downto 0);
1163
                else
1164
                  right <= "11111111111" & md(4 downto 0);
1165
                end if;
1166
         when md_sign8_right =>
1167
           if md(7) = '0' then
1168
             right <= "00000000" & md(7 downto 0);
1169
                else
1170
                  right <= "11111111" & md(7 downto 0);
1171
                end if;
1172
         when others =>
1173
--       when md_right =>
1174
           right <= md;
1175
    end case;
1176
end process;
1177
 
1178
----------------------------------
1179
--
1180
-- Arithmetic Logic Unit
1181
--
1182
----------------------------------
1183
 
1184
alu: process( alu_ctrl, cc, left, right, out_alu, cc_out )
1185
variable valid_lo, valid_hi : boolean;
1186
variable carry_in : std_logic;
1187
variable daa_reg : std_logic_vector(7 downto 0);
1188
begin
1189
 
1190
  case alu_ctrl is
1191
         when alu_adc | alu_sbc |
1192
              alu_rol8 | alu_ror8 =>
1193
           carry_in := cc(CBIT);
1194
    when alu_asr8 =>
1195
           carry_in := left(7);
1196
         when others =>
1197
           carry_in := '0';
1198
  end case;
1199
 
1200
  valid_lo := left(3 downto 0) <= 9;
1201
  valid_hi := left(7 downto 4) <= 9;
1202
 
1203
  --
1204
  -- CBIT HBIT VHI VLO DAA
1205
  --    0    0   0   0 66 (!VHI : hi_nybble>8)
1206
  --    0    0   0   1 60
1207
  --    0    0   1   1 00
1208
  --    0    0   1   0 06 ( VHI : hi_nybble<=8)
1209
  --
1210
  --    0    1   1   0 06
1211
  --    0    1   1   1 06
1212
  --    0    1   0   1 66
1213
  --    0    1   0   0 66
1214
  --
1215
  --    1    1   0   0 66
1216
  --    1    1   0   1 66
1217
  --    1    1   1   1 66
1218
  --    1    1   1   0 66
1219
  --
1220
  --    1    0   1   0 66
1221
  --    1    0   1   1 60
1222
  --    1    0   0   1 60
1223
  --    1    0   0   0 66
1224
  --
1225
  -- 66 = (!VHI & !VLO) + (CBIT & HBIT) + (HBIT & !VHI) + (CBIT & !VLO) 
1226
  --    = (CBIT & (HBIT + !VLO)) + (!VHI & (HBIT + !VLO))
1227
  --    = (!VLO & (CBIT + !VHI)) + (HBIT & (CBIT + !VHI))
1228
  -- 60 = (CBIT & !HBIT & VLO) + (!HBIT & !VHI & VLO) 
1229
  --    = (!HBIT & VLO & (CBIT + !VHI))
1230
  -- 06 = (!CBIT & VHI & (!VLO + VHI)
1231
  -- 00 = (!CBIT & !HBIT & VHI & VLO)
1232
  --
1233
  if (cc(CBIT) = '0') then
1234
    -- CBIT=0
1235
    if( cc(HBIT) = '0' ) then
1236
           -- HBIT=0
1237
                if valid_lo then
1238
                  -- lo <= 9 (no overflow in low nybble)
1239
                  if valid_hi then
1240
                    -- hi <= 9 (no overflow in either low or high nybble)
1241
                    daa_reg := "00000000";
1242
                  else
1243
                    -- hi > 9 (overflow in high nybble only)
1244
                    daa_reg := "01100000";
1245
                  end if;
1246
                else
1247
                  -- lo > 9 (overflow in low nybble)
1248
                  --
1249
                  -- since there is already an overflow in the low nybble
1250
                  -- you need to make room in the high nybble for the low nybble carry
1251
                  -- so compare the high nybble with 8 rather than 9
1252
                  -- if the high nybble is 9 there will be an overflow on the high nybble
1253
                  -- after the decimal adjust which means it will roll over to an invalid BCD digit
1254
                  --
1255
             if( left(7 downto 4) <= 8 ) then
1256
                    -- hi <= 8 (overflow in low nybble only)
1257
                    daa_reg := "00000110";
1258
                  else
1259
                    -- hi > 8 (overflow in low and high nybble)
1260
                         daa_reg := "01100110";
1261
                  end if;
1262
                end if;
1263
    else
1264
           -- HBIT=1 (overflow in low nybble)
1265
                if valid_hi then
1266
                  -- hi <= 9 (overflow in low nybble only)
1267
                  daa_reg := "00000110";
1268
                else
1269
                  -- hi > 9 (overflow in low and high nybble)
1270
                  daa_reg := "01100110";
1271
           end if;
1272
         end if;
1273
  else
1274
    -- CBIT=1 (carry => overflow in high nybble)
1275
    if ( cc(HBIT) = '0' )then
1276
           -- HBIT=0 (half carry clear => may or may not be an overflow in the low nybble)
1277
                if valid_lo then
1278
                  -- lo <=9  (overflow in high nybble only)
1279
                  daa_reg := "01100000";
1280
           else
1281
                  -- lo >9  (overflow in low and high nybble)
1282
                  daa_reg := "01100110";
1283
                end if;
1284
         else
1285
           -- HBIT=1 (overflow in low and high nybble)
1286
                daa_reg := "01100110";
1287
         end if;
1288
  end if;
1289
 
1290
  case alu_ctrl is
1291
         when alu_add8 | alu_inc |
1292
              alu_add16 | alu_adc | alu_mul =>
1293
                out_alu <= left + right + ("000000000000000" & carry_in);
1294
         when alu_sub8 | alu_dec |
1295
              alu_sub16 | alu_sbc =>
1296
           out_alu <= left - right - ("000000000000000" & carry_in);
1297
    when alu_abx =>
1298
           out_alu <= left + ("00000000" & right(7 downto 0)) ;
1299
         when alu_and =>
1300
           out_alu   <= left and right;         -- and/bit
1301
         when alu_ora =>
1302
           out_alu   <= left or right;  -- or
1303
         when alu_eor =>
1304
           out_alu   <= left xor right;         -- eor/xor
1305
         when alu_lsl16 | alu_asl8 | alu_rol8 =>
1306
           out_alu   <= left(14 downto 0) & carry_in;    -- rol8/asl8/lsl16
1307
         when alu_lsr16 =>
1308
           out_alu   <= carry_in & left(15 downto 1);   -- lsr16
1309
         when alu_lsr8 | alu_asr8 | alu_ror8 =>
1310
           out_alu   <= "00000000" & carry_in & left(7 downto 1);       -- ror8/asr8/lsr8
1311
         when alu_neg =>
1312
           out_alu   <= right - left;   -- neg (right=0)
1313
         when alu_com =>
1314
           out_alu   <= not left;
1315
         when alu_clr | alu_ld8 | alu_ld16 | alu_lea =>
1316
           out_alu   <= right;           -- clr, ld
1317
         when alu_st8 | alu_st16 | alu_andcc | alu_orcc | alu_tfr =>
1318
           out_alu   <= left;
1319
         when alu_daa =>
1320
           out_alu   <= left + ("00000000" & daa_reg);
1321
         when alu_sex =>
1322
           if left(7) = '0' then
1323
              out_alu <= "00000000" & left(7 downto 0);
1324
                else
1325
                   out_alu <= "11111111" & left(7 downto 0);
1326
                end if;
1327
         when others =>
1328
           out_alu   <= left; -- nop
1329
    end case;
1330
 
1331
         --
1332
         -- carry bit
1333
         --
1334
    case alu_ctrl is
1335
         when alu_add8 | alu_adc  =>
1336
      cc_out(CBIT) <= (left(7) and right(7)) or
1337
                                (left(7) and not out_alu(7)) or
1338
                                                   (right(7) and not out_alu(7));
1339
         when alu_sub8 | alu_sbc =>
1340
      cc_out(CBIT) <= ((not left(7)) and right(7)) or
1341
                                ((not left(7)) and out_alu(7)) or
1342
                                                         (right(7) and out_alu(7));
1343
         when alu_add16  =>
1344
      cc_out(CBIT) <= (left(15) and right(15)) or
1345
                                (left(15) and not out_alu(15)) or
1346
                                                   (right(15) and not out_alu(15));
1347
         when alu_sub16 =>
1348
      cc_out(CBIT) <= ((not left(15)) and right(15)) or
1349
                                ((not left(15)) and out_alu(15)) or
1350
                                                         (right(15) and out_alu(15));
1351
         when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 =>
1352
           cc_out(CBIT) <= left(0);
1353
         when alu_rol8 | alu_asl8 =>
1354
           cc_out(CBIT) <= left(7);
1355
         when alu_lsl16 =>
1356
           cc_out(CBIT) <= left(15);
1357
         when alu_com =>
1358
           cc_out(CBIT) <= '1';
1359
         when alu_neg | alu_clr =>
1360
           cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
1361
                                out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0);
1362
    when alu_mul =>
1363
                cc_out(CBIT) <= out_alu(7);
1364
    when alu_daa =>
1365
           if ( daa_reg(7 downto 4) = "0110" ) then
1366
                  cc_out(CBIT) <= '1';
1367
                else
1368
                  cc_out(CBIT) <= '0';
1369
           end if;
1370
         when alu_andcc =>
1371
      cc_out(CBIT) <= left(CBIT) and cc(CBIT);
1372
         when alu_orcc =>
1373
      cc_out(CBIT) <= left(CBIT) or cc(CBIT);
1374
         when alu_tfr =>
1375
      cc_out(CBIT) <= left(CBIT);
1376
         when others =>
1377
      cc_out(CBIT) <= cc(CBIT);
1378
    end case;
1379
         --
1380
         -- Zero flag
1381
         --
1382
    case alu_ctrl is
1383
         when alu_add8 | alu_sub8 |
1384
              alu_adc | alu_sbc |
1385
              alu_and | alu_ora | alu_eor |
1386
              alu_inc | alu_dec |
1387
                        alu_neg | alu_com | alu_clr |
1388
                        alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
1389
                   alu_ld8  | alu_st8 | alu_sex | alu_daa =>
1390
      cc_out(ZBIT) <= not( out_alu(7)  or out_alu(6)  or out_alu(5)  or out_alu(4)  or
1391
                                out_alu(3)  or out_alu(2)  or out_alu(1)  or out_alu(0) );
1392
         when alu_add16 | alu_sub16 | alu_mul |
1393
              alu_lsl16 | alu_lsr16 |
1394
                   alu_ld16  | alu_st16 | alu_lea =>
1395
      cc_out(ZBIT) <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or
1396
                                out_alu(11) or out_alu(10) or out_alu(9)  or out_alu(8)  or
1397
                                out_alu(7)  or out_alu(6)  or out_alu(5)  or out_alu(4)  or
1398
                                out_alu(3)  or out_alu(2)  or out_alu(1)  or out_alu(0) );
1399
         when alu_andcc =>
1400
      cc_out(ZBIT) <= left(ZBIT) and cc(ZBIT);
1401
         when alu_orcc =>
1402
      cc_out(ZBIT) <= left(ZBIT) or cc(ZBIT);
1403
         when alu_tfr =>
1404
      cc_out(ZBIT) <= left(ZBIT);
1405
         when others =>
1406
      cc_out(ZBIT) <= cc(ZBIT);
1407
    end case;
1408
 
1409
    --
1410
         -- negative flag
1411
         --
1412
    case alu_ctrl is
1413
         when alu_add8 | alu_sub8 |
1414
              alu_adc | alu_sbc |
1415
              alu_and | alu_ora | alu_eor |
1416
              alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
1417
              alu_inc | alu_dec | alu_neg | alu_com | alu_clr |
1418
                        alu_ld8  | alu_st8 | alu_sex | alu_daa =>
1419
      cc_out(NBIT) <= out_alu(7);
1420
         when alu_add16 | alu_sub16 |
1421
              alu_lsl16 | alu_lsr16 |
1422
                        alu_ld16 | alu_st16 =>
1423
                cc_out(NBIT) <= out_alu(15);
1424
         when alu_andcc =>
1425
      cc_out(NBIT) <= left(NBIT) and cc(NBIT);
1426
         when alu_orcc =>
1427
      cc_out(NBIT) <= left(NBIT) or cc(NBIT);
1428
         when alu_tfr =>
1429
      cc_out(NBIT) <= left(NBIT);
1430
         when others =>
1431
      cc_out(NBIT) <= cc(NBIT);
1432
    end case;
1433
 
1434
    --
1435
         -- Interrupt mask flag
1436
    --
1437
    case alu_ctrl is
1438
         when alu_andcc =>
1439
      cc_out(IBIT) <= left(IBIT) and cc(IBIT);
1440
         when alu_orcc =>
1441
      cc_out(IBIT) <= left(IBIT) or cc(IBIT);
1442
         when alu_tfr =>
1443
      cc_out(IBIT) <= left(IBIT);
1444
    when alu_seif | alu_sei =>
1445
           cc_out(IBIT) <= '1';
1446
         when others =>
1447
                cc_out(IBIT) <= cc(IBIT);             -- interrupt mask
1448
    end case;
1449
 
1450
    --
1451
    -- Half Carry flag
1452
         --
1453
    case alu_ctrl is
1454
         when alu_add8 | alu_adc =>
1455
      cc_out(HBIT) <= (left(3) and right(3)) or
1456
                     (right(3) and not out_alu(3)) or
1457
                      (left(3) and not out_alu(3));
1458
         when alu_andcc =>
1459
      cc_out(HBIT) <= left(HBIT) and cc(HBIT);
1460
         when alu_orcc =>
1461
      cc_out(HBIT) <= left(HBIT) or cc(HBIT);
1462
         when alu_tfr =>
1463
      cc_out(HBIT) <= left(HBIT);
1464
         when others =>
1465
                cc_out(HBIT) <= cc(HBIT);
1466
    end case;
1467
 
1468
    --
1469
    -- Overflow flag
1470
         --
1471
    case alu_ctrl is
1472
         when alu_add8 | alu_adc =>
1473
      cc_out(VBIT) <= (left(7)  and      right(7)  and (not out_alu(7))) or
1474
                 ((not left(7)) and (not right(7)) and      out_alu(7));
1475
         when alu_sub8 | alu_sbc =>
1476
      cc_out(VBIT) <= (left(7)  and (not right(7)) and (not out_alu(7))) or
1477
                 ((not left(7)) and      right(7)  and      out_alu(7));
1478
         when alu_add16 =>
1479
      cc_out(VBIT) <= (left(15)  and      right(15)  and (not out_alu(15))) or
1480
                 ((not left(15)) and (not right(15)) and      out_alu(15));
1481
         when alu_sub16 =>
1482
      cc_out(VBIT) <= (left(15)  and (not right(15)) and (not out_alu(15))) or
1483
                 ((not left(15)) and      right(15) and       out_alu(15));
1484
         when alu_inc =>
1485
           cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and
1486
                                      left(3)  and left(2) and left(1) and left(0));
1487
         when alu_dec | alu_neg =>
1488
           cc_out(VBIT) <= (left(7)  and (not left(6)) and (not left(5)) and (not left(4)) and
1489
                            (not left(3)) and (not left(2)) and (not left(1)) and (not left(0)));
1490
-- 6809 Programming reference manual says
1491
-- V not affected by ASR, LSR and ROR
1492
-- This is different to the 6800
1493
-- John Kent 6th June 2006
1494
--       when alu_asr8 =>
1495
--         cc_out(VBIT) <= left(0) xor left(7);
1496
--       when alu_lsr8 | alu_lsr16 =>
1497
--         cc_out(VBIT) <= left(0);
1498
--       when alu_ror8 =>
1499
--      cc_out(VBIT) <= left(0) xor cc(CBIT);
1500
    when alu_lsl16 =>
1501
      cc_out(VBIT) <= left(15) xor left(14);
1502
         when alu_rol8 | alu_asl8 =>
1503
      cc_out(VBIT) <= left(7) xor left(6);
1504
--
1505
-- 11th July 2006 - John Kent
1506
-- What DAA does with V is anyones guess
1507
-- It is undefined in the 6809 programming manual
1508
--
1509
         when alu_daa =>
1510
      cc_out(VBIT) <= left(7) xor out_alu(7) xor cc(CBIT);
1511
-- CLR resets V Bit
1512
-- John Kent 6th June 2006
1513
         when alu_and | alu_ora | alu_eor | alu_com | alu_clr |
1514
              alu_st8 | alu_st16 | alu_ld8 | alu_ld16 | alu_sex =>
1515
      cc_out(VBIT) <= '0';
1516
         when alu_andcc =>
1517
      cc_out(VBIT) <= left(VBIT) and cc(VBIT);
1518
         when alu_orcc =>
1519
      cc_out(VBIT) <= left(VBIT) or cc(VBIT);
1520
         when alu_tfr =>
1521
      cc_out(VBIT) <= left(VBIT);
1522
         when others =>
1523
                cc_out(VBIT) <= cc(VBIT);
1524
    end case;
1525
 
1526
         case alu_ctrl is
1527
         when alu_andcc =>
1528
      cc_out(FBIT) <= left(FBIT) and cc(FBIT);
1529
         when alu_orcc =>
1530
      cc_out(FBIT) <= left(FBIT) or cc(FBIT);
1531
         when alu_tfr =>
1532
      cc_out(FBIT) <= left(FBIT);
1533
    when alu_seif =>
1534
           cc_out(FBIT) <= '1';
1535
         when others =>
1536
      cc_out(FBIT) <= cc(FBIT);
1537
         end case;
1538
 
1539
         case alu_ctrl is
1540
         when alu_andcc =>
1541
      cc_out(EBIT) <= left(EBIT) and cc(EBIT);
1542
         when alu_orcc =>
1543
      cc_out(EBIT) <= left(EBIT) or cc(EBIT);
1544
         when alu_tfr =>
1545
      cc_out(EBIT) <= left(EBIT);
1546
    when alu_see =>
1547
           cc_out(EBIT) <= '1';
1548
    when alu_cle =>
1549
           cc_out(EBIT) <= '0';
1550
         when others =>
1551
           cc_out(EBIT) <= cc(EBIT);
1552
         end case;
1553
end process;
1554
 
1555
------------------------------------
1556
--
1557
-- state sequencer
1558
--
1559
------------------------------------
1560
process( state, saved_state,
1561
         op_code, pre_code,
1562
                        cc, ea, md, iv, fic, halt,
1563
         nmi_req, firq, irq, lic )
1564
variable cond_true : boolean;  -- variable used to evaluate coditional branches
1565
begin
1566
  cond_true  := (1=1);
1567
  ba         <= '0';
1568
  bs         <= '0';
1569
  lic        <= '0';
1570
  opfetch    <= '0';
1571
  iv_ctrl    <= latch_iv;
1572
  -- Registers preserved
1573
  cc_ctrl    <= latch_cc;
1574
  acca_ctrl  <= latch_acca;
1575
  accb_ctrl  <= latch_accb;
1576
  dp_ctrl    <= latch_dp;
1577
  ix_ctrl    <= latch_ix;
1578
  iy_ctrl    <= latch_iy;
1579
  up_ctrl    <= latch_up;
1580
  sp_ctrl    <= latch_sp;
1581
  pc_ctrl    <= latch_pc;
1582
  md_ctrl    <= latch_md;
1583
  ea_ctrl    <= latch_ea;
1584
  op_ctrl    <= latch_op;
1585
  pre_ctrl   <= latch_pre;
1586
  -- ALU Idle
1587
  left_ctrl  <= pc_left;
1588
  right_ctrl <= zero_right;
1589
  alu_ctrl   <= alu_nop;
1590
  -- Bus idle
1591
  addr_ctrl  <= idle_ad;
1592
  dout_ctrl  <= cc_dout;
1593
  -- Next State Fetch
1594
  st_ctrl      <= idle_st;
1595
  return_state <= fetch_state;
1596
  next_state   <= fetch_state;
1597
 
1598
  case state is
1599
  when reset_state =>        --  released from reset
1600
    -- reset the registers
1601
    iv_ctrl    <= reset_iv;
1602
    op_ctrl    <= reset_op;
1603
    pre_ctrl   <= reset_pre;
1604
    cc_ctrl    <= reset_cc;
1605
    acca_ctrl  <= reset_acca;
1606
    accb_ctrl  <= reset_accb;
1607
    dp_ctrl    <= reset_dp;
1608
    ix_ctrl    <= reset_ix;
1609
    iy_ctrl    <= reset_iy;
1610
    up_ctrl    <= reset_up;
1611
    sp_ctrl    <= reset_sp;
1612
    pc_ctrl    <= reset_pc;
1613
    ea_ctrl    <= reset_ea;
1614
    md_ctrl    <= reset_md;
1615
    st_ctrl    <= reset_st;
1616
    next_state <= vect_hi_state;
1617
 
1618
  --
1619
  -- Jump via interrupt vector
1620
  -- iv holds interrupt type
1621
  -- fetch PC hi from vector location
1622
  --
1623
  when vect_hi_state =>
1624
    -- fetch pc low interrupt vector
1625
    pc_ctrl    <= pull_hi_pc;
1626
    addr_ctrl  <= int_hi_ad;
1627
    bs         <= '1';
1628
    next_state <= vect_lo_state;
1629
 
1630
  --
1631
  -- jump via interrupt vector
1632
  -- iv holds vector type
1633
  -- fetch PC lo from vector location
1634
  --
1635
  when vect_lo_state =>
1636
    -- fetch the vector low byte
1637
    pc_ctrl    <= pull_lo_pc;
1638
    addr_ctrl  <= int_lo_ad;
1639
    bs         <= '1';
1640
    next_state <= fetch_state;
1641
 
1642
  when vect_idle_state =>
1643
    --
1644
    -- Last Instruction Cycle for SWI, SWI2 & SWI3
1645
    --
1646
    if op_code = "00111111" then
1647
      lic      <= '1';
1648
    end if;
1649
    next_state <= fetch_state;
1650
 
1651
  --
1652
  -- Here to fetch an instruction
1653
  -- PC points to opcode
1654
  --
1655
  when fetch_state =>
1656
    -- fetch the op code
1657
    opfetch    <= '1';
1658
    op_ctrl    <= fetch_op;
1659
    pre_ctrl   <= fetch_pre;
1660
    ea_ctrl    <= reset_ea;
1661
    -- Fetch op code
1662
    addr_ctrl  <= fetch_ad;
1663
    -- Advance the PC to fetch next instruction byte
1664
    pc_ctrl    <= incr_pc;
1665
    next_state <= decode_state;
1666
 
1667
  --
1668
  -- Here to decode instruction
1669
  -- and fetch next byte of intruction
1670
  -- whether it be necessary or not
1671
  --
1672
  when decode_state =>
1673
        -- fetch first byte of address or immediate data
1674
    ea_ctrl    <= fetch_first_ea;
1675
    md_ctrl    <= fetch_first_md;
1676
    addr_ctrl  <= fetch_ad;
1677
    case op_code(7 downto 4) is
1678
    --
1679
    -- direct single op (2 bytes)
1680
    -- 6809 => 6 cycles
1681
    -- cpu09 => 5 cycles
1682
    -- 1 op=(pc) / pc=pc+1
1683
    -- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
1684
    -- 3 md_lo=(ea) / pc=pc
1685
    -- 4 alu_left=md / md=alu_out / pc=pc
1686
    -- 5 (ea)=md_lo / pc=pc
1687
    --
1688
    -- Exception is JMP
1689
    -- 6809 => 3 cycles
1690
    -- cpu09 => 3 cycles
1691
    -- 1 op=(pc) / pc=pc+1
1692
    -- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
1693
    -- 3 pc=ea
1694
               --
1695
        when "0000" =>
1696
      -- advance the PC
1697
      pc_ctrl    <= incr_pc;
1698
 
1699
      case op_code(3 downto 0) is
1700
      when "1110" => -- jmp
1701
        next_state <= jmp_state;
1702
 
1703
      when "1111" => -- clr
1704
        next_state <= single_op_exec_state;
1705
 
1706
      when others =>
1707
        next_state <= single_op_read_state;
1708
 
1709
      end case;
1710
 
1711
    -- acca / accb inherent instructions
1712
        when "0001" =>
1713
      case op_code(3 downto 0) is
1714
      --
1715
      -- Page2 pre byte
1716
      -- pre=(pc) / pc=pc+1
1717
      -- op=(pc) / pc=pc+1
1718
      --
1719
      when "0000" => -- page2
1720
        opfetch    <= '1';
1721
        op_ctrl    <= fetch_op;
1722
                  pre_ctrl   <= load_pre;
1723
        -- advance pc
1724
        pc_ctrl    <= incr_pc;
1725
        next_state <= decode_state;
1726
 
1727
      --
1728
      -- Page3 pre byte
1729
      -- pre=(pc) / pc=pc+1
1730
      -- op=(pc) / pc=pc+1
1731
      --
1732
      when "0001" => -- page3
1733
        opfetch    <= '1';
1734
        op_ctrl    <= fetch_op;
1735
                  pre_ctrl   <= load_pre;
1736
        -- advance pc
1737
        pc_ctrl    <= incr_pc;
1738
        next_state <= decode_state;
1739
 
1740
      --
1741
      -- nop - No operation ( 1 byte )
1742
      -- 6809 => 2 cycles
1743
      -- cpu09 => 2 cycles
1744
      -- 1 op=(pc) / pc=pc+1
1745
      -- 2 decode
1746
      -- 
1747
      when "0010" => -- nop
1748
        lic          <= '1';
1749
        next_state   <= fetch_state;
1750
 
1751
      --
1752
      -- sync - halt execution until an interrupt is received
1753
      -- interrupt may be NMI, IRQ or FIRQ
1754
      -- program execution continues if the 
1755
      -- interrupt is asserted for 3 clock cycles
1756
      -- note that registers are not pushed onto the stack
1757
      -- CPU09 => Interrupts need only be asserted for one clock cycle
1758
      --
1759
      when "0011" => -- sync
1760
        next_state   <= sync_state;
1761
 
1762
      --
1763
      -- lbra -- long branch (3 bytes)
1764
      -- 6809 => 5 cycles
1765
      -- cpu09 => 4 cycles
1766
      -- 1 op=(pc) / pc=pc+1
1767
      -- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
1768
      -- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
1769
      -- 4 pc=pc+md
1770
      --
1771
      when "0110" =>
1772
        -- increment the pc
1773
        pc_ctrl    <= incr_pc;
1774
        next_state <= lbranch_state;
1775
 
1776
      --
1777
      -- lbsr - long branch to subroutine (3 bytes)
1778
      -- 6809 => 9 cycles
1779
      -- cpu09 => 6 cycles
1780
      -- 1 op=(pc) /pc=pc+1
1781
      -- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / sp=sp-1
1782
      -- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
1783
      -- 4 (sp)= pc_lo / sp=sp-1 / pc=pc
1784
      -- 5 (sp)=pc_hi / pc=pc
1785
      -- 6 pc=pc+md
1786
      --
1787
      when "0111" =>
1788
        -- pre decrement sp
1789
        left_ctrl  <= sp_left;
1790
        right_ctrl <= one_right;
1791
        alu_ctrl   <= alu_sub16;
1792
        sp_ctrl    <= load_sp;
1793
        -- increment the pc
1794
        pc_ctrl    <= incr_pc;
1795
        next_state <= lbranch_state;
1796
 
1797
      --
1798
      -- Decimal Adjust Accumulator
1799
      --
1800
      when "1001" => -- daa
1801
        left_ctrl  <= acca_left;
1802
        right_ctrl <= accb_right;
1803
        alu_ctrl   <= alu_daa;
1804
        cc_ctrl    <= load_cc;
1805
        acca_ctrl  <= load_acca;
1806
        lic        <= '1';
1807
        next_state <= fetch_state;
1808
 
1809
      --
1810
      -- OR Condition Codes
1811
      --
1812
      when "1010" => -- orcc
1813
        -- increment the pc
1814
        pc_ctrl      <= incr_pc;
1815
        next_state   <= orcc_state;
1816
 
1817
      --
1818
      -- AND Condition Codes
1819
      --
1820
      when "1100" => -- andcc
1821
        -- increment the pc
1822
        pc_ctrl      <= incr_pc;
1823
        next_state   <= andcc_state;
1824
 
1825
      --
1826
      -- Sign Extend
1827
      --
1828
      when "1101" => -- sex
1829
        left_ctrl  <= accb_left;
1830
        right_ctrl <= zero_right;
1831
        alu_ctrl   <= alu_sex;
1832
        cc_ctrl    <= load_cc;
1833
        acca_ctrl  <= load_hi_acca;
1834
        lic        <= '1';
1835
        next_state <= fetch_state;
1836
 
1837
      --
1838
      -- Exchange Registers
1839
      --
1840
      when "1110" => -- exg
1841
        -- increment the pc
1842
        pc_ctrl    <= incr_pc;
1843
        next_state <= exg_state;
1844
 
1845
      --
1846
      -- Transfer Registers
1847
      --
1848
      when "1111" => -- tfr
1849
        -- increment the pc
1850
        pc_ctrl      <= incr_pc;
1851
        next_state   <= tfr_state;
1852
 
1853
      when others =>
1854
        -- increment the pc
1855
        pc_ctrl    <= incr_pc;
1856
        lic        <= '1';
1857
        next_state <= fetch_state;
1858
      end case;
1859
 
1860
         --
1861
         -- conditional branch
1862
         --
1863
    when "0010" => -- branch conditional
1864
      -- increment the pc
1865
      pc_ctrl    <= incr_pc;
1866
                case pre_code is
1867
                when "00010000" => -- page 2
1868
                        --
1869
                        -- lbcc -- long branch conditional
1870
                        -- 6809 => branch 6 cycles, no branch 5 cycles
1871
                        -- cpu09 => always 5 cycles
1872
                        -- 1 pre=(pc) / pc=pc+1
1873
                        -- 2 op=(pc) / pc=pc+1
1874
                        -- 3 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
1875
         -- 4 md_hi=md_lo / md_lo=(pc) / pc=pc+1
1876
                        -- 5 if cond pc=pc+md else pc=pc
1877
                        --
1878
                        next_state <= lbranch_state;
1879
 
1880
                when others => -- page 1
1881
                        --
1882
                        -- Short branch conditional
1883
                        -- 6809 => always 3 cycles
1884
                        -- cpu09 => always = 3 cycles
1885
                        -- 1 op=(pc) / pc=pc+1
1886
                        -- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / test cc
1887
                        -- 3 if cc tru pc=pc+md else pc=pc
1888
                        --
1889
                        next_state <= sbranch_state;
1890
                end case;
1891
 
1892
    --
1893
    -- Single byte stack operators
1894
    -- Do not advance PC
1895
    --
1896
    when "0011" =>
1897
      --
1898
      -- lea - load effective address (2+ bytes)
1899
      -- 6809 => 4 cycles + addressing mode
1900
      -- cpu09 => 4 cycles + addressing mode
1901
      -- 1 op=(pc) / pc=pc+1
1902
      -- 2 md_lo=(pc) / pc=pc+1
1903
      -- 3 calculate ea
1904
      -- 4 ix/iy/sp/up = ea
1905
      --
1906
      case op_code(3 downto 0) is
1907
           when "0000" |  -- leax
1908
           "0001" |  -- leay
1909
           "0010" |  -- leas
1910
           "0011" => -- leau
1911
        -- advance PC
1912
        pc_ctrl      <= incr_pc;
1913
        st_ctrl      <= push_st;
1914
        return_state <= lea_state;
1915
        next_state   <= indexed_state;
1916
 
1917
      --
1918
      -- pshs - push registers onto sp stack
1919
      -- 6809 => 5 cycles + registers
1920
      -- cpu09 => 3 cycles + registers
1921
      --  1 op=(pc) / pc=pc+1
1922
      --  2 ea_lo=(pc) / pc=pc+1 
1923
      --  3 if ea(7 downto 0) != "00000000" then sp=sp-1
1924
      --  4 if ea(7) = 1 (sp)=pcl, sp=sp-1
1925
      --  5 if ea(7) = 1 (sp)=pch
1926
      --    if ea(6 downto 0) != "0000000" then sp=sp-1
1927
      --  6 if ea(6) = 1 (sp)=upl, sp=sp-1
1928
      --  7 if ea(6) = 1 (sp)=uph
1929
      --    if ea(5 downto 0) != "000000" then sp=sp-1
1930
      --  8 if ea(5) = 1 (sp)=iyl, sp=sp-1
1931
      --  9 if ea(5) = 1 (sp)=iyh
1932
      --    if ea(4 downto 0) != "00000" then sp=sp-1
1933
      -- 10 if ea(4) = 1 (sp)=ixl, sp=sp-1
1934
      -- 11 if ea(4) = 1 (sp)=ixh
1935
      --    if ea(3 downto 0) != "0000" then sp=sp-1
1936
      -- 12 if ea(3) = 1 (sp)=dp
1937
      --    if ea(2 downto 0) != "000" then sp=sp-1
1938
      -- 13 if ea(2) = 1 (sp)=accb
1939
      --    if ea(1 downto 0) != "00" then sp=sp-1
1940
      -- 14 if ea(1) = 1 (sp)=acca
1941
      --    if ea(0 downto 0) != "0" then sp=sp-1
1942
      -- 15 if ea(0) = 1 (sp)=cc
1943
      --
1944
      when "0100" => -- pshs
1945
        -- advance PC
1946
        pc_ctrl    <= incr_pc;
1947
        next_state <= pshs_state;
1948
 
1949
      --
1950
      -- puls - pull registers of sp stack
1951
      -- 6809 => 5 cycles + registers
1952
      -- cpu09 => 3 cycles + registers
1953
      --
1954
      when "0101" => -- puls
1955
        -- advance PC
1956
        pc_ctrl    <= incr_pc;
1957
        next_state <= puls_state;
1958
 
1959
      --
1960
      -- pshu - push registers onto up stack
1961
      -- 6809 => 5 cycles + registers
1962
      -- cpu09 => 3 cycles + registers
1963
      --
1964
      when "0110" => -- pshu
1965
        -- advance PC
1966
        pc_ctrl    <= incr_pc;
1967
        next_state <= pshu_state;
1968
 
1969
      --
1970
      -- pulu - pull registers of up stack
1971
      -- 6809 => 5 cycles + registers
1972
      -- cpu09 => 3 cycles + registers
1973
      --
1974
      when "0111" => -- pulu
1975
        -- advance PC
1976
        pc_ctrl    <= incr_pc;
1977
        next_state <= pulu_state;
1978
 
1979
      --
1980
      -- rts - return from subroutine
1981
      -- 6809 => 5 cycles
1982
      -- cpu09 => 4 cycles 
1983
      -- 1 op=(pc) / pc=pc+1
1984
      -- 2 decode op
1985
      -- 3 pc_hi = (sp) / sp=sp+1
1986
      -- 4 pc_lo = (sp) / sp=sp+1
1987
      --
1988
      when "1001" =>
1989
                  next_state   <= pull_return_hi_state;
1990
 
1991
      --
1992
      -- ADD accb to index register
1993
      -- *** Note: this is an unsigned addition.
1994
      --           does not affect any condition codes
1995
      -- 6809 => 3 cycles
1996
      -- cpu09 => 2 cycles
1997
      -- 1 op=(pc) / pc=pc+1
1998
      -- 2 alu_left=ix / alu_right=accb / ix=alu_out / pc=pc
1999
      --
2000
      when "1010" => -- abx
2001
        left_ctrl    <= ix_left;
2002
        right_ctrl   <= accb_right;
2003
        alu_ctrl     <= alu_abx;
2004
        ix_ctrl      <= load_ix;
2005
        lic          <= '1';
2006
        next_state   <= fetch_state;
2007
 
2008
      --
2009
      -- Return From Interrupt
2010
      --
2011
      when "1011" => -- rti
2012
        next_state   <= rti_cc_state;
2013
 
2014
      --
2015
      -- CWAI
2016
      --
2017
      when "1100" => -- cwai #$<cc_mask>
2018
        -- pre decrement sp
2019
        left_ctrl    <= sp_left;
2020
        right_ctrl   <= one_right;
2021
        alu_ctrl     <= alu_sub16;
2022
        sp_ctrl      <= load_sp;
2023
        -- increment pc
2024
        pc_ctrl      <= incr_pc;
2025
        next_state   <= cwai_state;
2026
 
2027
      --
2028
      -- MUL Multiply
2029
      --
2030
      when "1101" => -- mul
2031
                        -- move acca to md
2032
         left_ctrl  <= acca_left;
2033
         right_ctrl <= zero_right;
2034
         alu_ctrl   <= alu_st16;
2035
         md_ctrl    <= load_md; -- over ride md_ctrl <= second byte fetch 
2036
                        next_state <= mulea_state;
2037
 
2038
      --
2039
      -- SWI Software Interrupt
2040
                -- Do not advance PC
2041
      --
2042
      when "1111" => -- swi
2043
        -- predecrement SP
2044
        left_ctrl    <= sp_left;
2045
        right_ctrl   <= one_right;
2046
        alu_ctrl     <= alu_sub16;
2047
        sp_ctrl      <= load_sp;
2048
        st_ctrl      <= push_st;
2049
                  case pre_code is
2050
                  when "00010000" => -- page 2
2051
                                iv_ctrl      <= swi2_iv;
2052
                                return_state <= vect_hi_state;
2053
 
2054
                  when "00010001" => -- page 3
2055
                           iv_ctrl      <= swi3_iv;
2056
                                return_state <= vect_hi_state;
2057
 
2058
                  when others => -- page 1
2059
                                iv_ctrl  <= swi_iv;
2060
                                return_state <= int_swimask_state;
2061
 
2062
                  end case;
2063
        next_state   <= int_entire_state;
2064
 
2065
      when others =>
2066
        lic          <= '1';
2067
        next_state   <= fetch_state;
2068
 
2069
      end case;
2070
                                 --
2071
    -- Accumulator A Single operand
2072
    -- source = acca, dest = acca
2073
    -- Do not advance PC
2074
    -- Typically 2 cycles 1 bytes
2075
    -- 1 opcode fetch
2076
    -- 2 post byte fetch / instruction decode
2077
    -- Note that there is no post byte
2078
    -- so do not advance PC in decode cycle
2079
    -- Re-run opcode fetch cycle after decode
2080
    -- 
2081
    when "0100" => -- acca single op
2082
      left_ctrl  <= acca_left;
2083
      case op_code(3 downto 0) is
2084
 
2085
      when "0000" => -- neg
2086
        right_ctrl <= zero_right;
2087
        alu_ctrl   <= alu_neg;
2088
        acca_ctrl  <= load_acca;
2089
        cc_ctrl    <= load_cc;
2090
 
2091
      when "0011" => -- com
2092
        right_ctrl <= zero_right;
2093
        alu_ctrl   <= alu_com;
2094
        acca_ctrl  <= load_acca;
2095
        cc_ctrl    <= load_cc;
2096
 
2097
      when "0100" => -- lsr
2098
        right_ctrl <= zero_right;
2099
        alu_ctrl   <= alu_lsr8;
2100
        acca_ctrl  <= load_acca;
2101
        cc_ctrl    <= load_cc;
2102
 
2103
           when "0110" => -- ror
2104
        right_ctrl <= zero_right;
2105
        alu_ctrl   <= alu_ror8;
2106
        acca_ctrl  <= load_acca;
2107
        cc_ctrl    <= load_cc;
2108
 
2109
      when "0111" => -- asr
2110
        right_ctrl <= zero_right;
2111
        alu_ctrl   <= alu_asr8;
2112
        acca_ctrl  <= load_acca;
2113
        cc_ctrl    <= load_cc;
2114
 
2115
      when "1000" => -- asl
2116
        right_ctrl <= zero_right;
2117
        alu_ctrl   <= alu_asl8;
2118
        acca_ctrl  <= load_acca;
2119
        cc_ctrl    <= load_cc;
2120
 
2121
      when "1001" => -- rol
2122
        right_ctrl <= zero_right;
2123
        alu_ctrl   <= alu_rol8;
2124
        acca_ctrl  <= load_acca;
2125
        cc_ctrl    <= load_cc;
2126
 
2127
      when "1010" => -- dec
2128
        right_ctrl <= one_right;
2129
        alu_ctrl   <= alu_dec;
2130
        acca_ctrl  <= load_acca;
2131
        cc_ctrl    <= load_cc;
2132
 
2133
      when "1011" => -- undefined
2134
        right_ctrl <= zero_right;
2135
        alu_ctrl   <= alu_nop;
2136
        acca_ctrl  <= latch_acca;
2137
        cc_ctrl    <= latch_cc;
2138
 
2139
      when "1100" => -- inc
2140
        right_ctrl <= one_right;
2141
        alu_ctrl   <= alu_inc;
2142
        acca_ctrl  <= load_acca;
2143
        cc_ctrl    <= load_cc;
2144
 
2145
      when "1101" => -- tst
2146
        right_ctrl <= zero_right;
2147
        alu_ctrl   <= alu_st8;
2148
        acca_ctrl  <= latch_acca;
2149
        cc_ctrl    <= load_cc;
2150
 
2151
      when "1110" => -- jmp (not defined)
2152
        right_ctrl <= zero_right;
2153
        alu_ctrl   <= alu_nop;
2154
        acca_ctrl  <= latch_acca;
2155
        cc_ctrl    <= latch_cc;
2156
 
2157
      when "1111" => -- clr
2158
        right_ctrl <= zero_right;
2159
        alu_ctrl   <= alu_clr;
2160
        acca_ctrl  <= load_acca;
2161
        cc_ctrl    <= load_cc;
2162
 
2163
      when others =>
2164
        right_ctrl <= zero_right;
2165
        alu_ctrl   <= alu_nop;
2166
        acca_ctrl  <= latch_acca;
2167
        cc_ctrl    <= latch_cc;
2168
 
2169
      end case;
2170
      lic        <= '1';
2171
      next_state <= fetch_state;
2172
 
2173
      --
2174
      -- Single Operand accb
2175
      -- source = accb, dest = accb
2176
      -- Typically 2 cycles 1 bytes
2177
      -- 1 opcode fetch
2178
      -- 2 post byte fetch / instruction decode
2179
      -- Note that there is no post byte
2180
      -- so do not advance PC in decode cycle
2181
      -- Re-run opcode fetch cycle after decode
2182
      --
2183
    when "0101" =>
2184
      left_ctrl  <= accb_left;
2185
      case op_code(3 downto 0) is
2186
      when "0000" => -- neg
2187
        right_ctrl <= zero_right;
2188
        alu_ctrl   <= alu_neg;
2189
        accb_ctrl  <= load_accb;
2190
        cc_ctrl    <= load_cc;
2191
 
2192
      when "0011" => -- com
2193
        right_ctrl <= zero_right;
2194
        alu_ctrl   <= alu_com;
2195
        accb_ctrl  <= load_accb;
2196
        cc_ctrl    <= load_cc;
2197
 
2198
      when "0100" => -- lsr
2199
        right_ctrl <= zero_right;
2200
        alu_ctrl   <= alu_lsr8;
2201
        accb_ctrl  <= load_accb;
2202
        cc_ctrl    <= load_cc;
2203
 
2204
      when "0110" => -- ror
2205
        right_ctrl <= zero_right;
2206
        alu_ctrl   <= alu_ror8;
2207
        accb_ctrl  <= load_accb;
2208
        cc_ctrl    <= load_cc;
2209
 
2210
      when "0111" => -- asr
2211
        right_ctrl <= zero_right;
2212
        alu_ctrl   <= alu_asr8;
2213
        accb_ctrl  <= load_accb;
2214
        cc_ctrl    <= load_cc;
2215
 
2216
      when "1000" => -- asl
2217
        right_ctrl <= zero_right;
2218
        alu_ctrl   <= alu_asl8;
2219
        accb_ctrl  <= load_accb;
2220
        cc_ctrl    <= load_cc;
2221
 
2222
      when "1001" => -- rol
2223
        right_ctrl <= zero_right;
2224
        alu_ctrl   <= alu_rol8;
2225
        accb_ctrl  <= load_accb;
2226
        cc_ctrl    <= load_cc;
2227
 
2228
      when "1010" => -- dec
2229
        right_ctrl <= one_right;
2230
        alu_ctrl   <= alu_dec;
2231
        accb_ctrl  <= load_accb;
2232
        cc_ctrl    <= load_cc;
2233
 
2234
      when "1011" => -- undefined
2235
        right_ctrl <= zero_right;
2236
        alu_ctrl   <= alu_nop;
2237
        accb_ctrl  <= latch_accb;
2238
        cc_ctrl    <= latch_cc;
2239
 
2240
      when "1100" => -- inc
2241
        right_ctrl <= one_right;
2242
        alu_ctrl   <= alu_inc;
2243
        accb_ctrl  <= load_accb;
2244
        cc_ctrl    <= load_cc;
2245
 
2246
      when "1101" => -- tst
2247
        right_ctrl <= zero_right;
2248
        alu_ctrl   <= alu_st8;
2249
        accb_ctrl  <= latch_accb;
2250
        cc_ctrl    <= load_cc;
2251
 
2252
      when "1110" => -- jmp (undefined)
2253
        right_ctrl <= zero_right;
2254
        alu_ctrl   <= alu_nop;
2255
        accb_ctrl  <= latch_accb;
2256
        cc_ctrl    <= latch_cc;
2257
 
2258
      when "1111" => -- clr
2259
        right_ctrl <= zero_right;
2260
        alu_ctrl   <= alu_clr;
2261
        accb_ctrl  <= load_accb;
2262
        cc_ctrl    <= load_cc;
2263
 
2264
      when others =>
2265
        right_ctrl <= zero_right;
2266
        alu_ctrl   <= alu_nop;
2267
        accb_ctrl  <= latch_accb;
2268
        cc_ctrl    <= latch_cc;
2269
      end case;
2270
      lic          <= '1';
2271
      next_state   <= fetch_state;
2272
 
2273
    --
2274
    -- Single operand indexed
2275
    -- Two byte instruction so advance PC
2276
    -- EA should hold index offset
2277
    --
2278
    when "0110" => -- indexed single op
2279
      -- increment the pc 
2280
      pc_ctrl    <= incr_pc;
2281
      st_ctrl    <= push_st;
2282
 
2283
      case op_code(3 downto 0) is
2284
      when "1110" => -- jmp
2285
        return_state <= jmp_state;
2286
 
2287
      when "1111" => -- clr
2288
        return_state <= single_op_exec_state;
2289
 
2290
      when others =>
2291
        return_state <= single_op_read_state;
2292
 
2293
      end case;
2294
      next_state <= indexed_state;
2295
 
2296
    --
2297
    -- Single operand extended addressing
2298
    -- three byte instruction so advance the PC
2299
    -- Low order EA holds high order address
2300
    --
2301
    when "0111" => -- extended single op
2302
      -- increment PC
2303
      pc_ctrl    <= incr_pc;
2304
      st_ctrl    <= push_st;
2305
 
2306
      case op_code(3 downto 0) is
2307
      when "1110" => -- jmp
2308
        return_state <= jmp_state;
2309
 
2310
      when "1111" => -- clr
2311
        return_state <= single_op_exec_state;
2312
 
2313
      when others =>
2314
        return_state <= single_op_read_state;
2315
 
2316
      end case;
2317
      next_state <= extended_state;
2318
 
2319
    when "1000" => -- acca immediate
2320
      -- increment the pc
2321
      pc_ctrl    <= incr_pc;
2322
 
2323
      case op_code(3 downto 0) is
2324
      when "0011" | -- subd #, cmpd #, cmpu #
2325
           "1100" | -- cmpx #, cmpy #, cmps #
2326
           "1110" => -- ldx #,  ldy #, undef #
2327
                          next_state   <= imm16_state;
2328
 
2329
      --
2330
      -- bsr offset - Branch to subroutine (2 bytes)
2331
      -- 6809 => 7 cycles
2332
      -- cpu09 => 5 cycles
2333
      -- 1 op=(pc) / pc=pc+1
2334
      -- 2 md_hi=sign(pc) / md_lo=(pc) / sp=sp-1 / pc=pc+1
2335
      -- 3 (sp)=pc_lo / sp=sp-1
2336
      -- 4 (sp)=pc_hi
2337
      -- 5 pc=pc+md
2338
      --
2339
      when "1101" => -- bsr
2340
        -- pre decrement SP
2341
        left_ctrl  <= sp_left;
2342
        right_ctrl <= one_right;
2343
        alu_ctrl   <= alu_sub16;
2344
        sp_ctrl    <= load_sp;
2345
             --
2346
             st_ctrl      <= push_st;
2347
        return_state <= sbranch_state;
2348
        next_state   <= push_return_lo_state;
2349
 
2350
      when others =>
2351
        lic          <= '1';
2352
        next_state   <= fetch_state;
2353
 
2354
      end case;
2355
 
2356
    when "1001" => -- acca direct
2357
      -- increment the pc
2358
      pc_ctrl    <= incr_pc;
2359
      case op_code(3 downto 0) is
2360
      when "0011" | -- subd <,  cmpd <, cmpu <
2361
           "1100" | -- cmpx <,  cmpy <, cmps <
2362
           "1110" => -- ldx <,   ldy <, undef <
2363
        next_state   <= dual_op_read16_state;
2364
 
2365
      when "0111" =>  -- sta direct
2366
        next_state <= dual_op_write8_state;
2367
 
2368
           --
2369
      -- jsr direct - Jump to subroutine in direct page (2 bytes)
2370
      -- 6809 => 7 cycles
2371
      -- cpu09 => 5 cycles
2372
      -- 1 op=(pc) / pc=pc+1
2373
      -- 2 ea_hi=0 / ea_lo=(pc) / sp=sp-1 / pc=pc+1
2374
      -- 3 (sp)=pc_lo / sp=sp-1
2375
      -- 4 (sp)=pc_hi
2376
      -- 5 pc=ea
2377
      --
2378
      when "1101" => -- jsr direct
2379
        -- pre decrement sp
2380
        left_ctrl  <= sp_left;
2381
        right_ctrl <= one_right;
2382
        alu_ctrl   <= alu_sub16;
2383
        sp_ctrl    <= load_sp;
2384
        --
2385
        st_ctrl      <= push_st;
2386
        return_state <= jmp_state;
2387
        next_state   <= push_return_lo_state;
2388
 
2389
 
2390
      when "1111" => -- stx <, sty <, undef <
2391
        -- idle ALU
2392
        left_ctrl  <= ix_left;
2393
        right_ctrl <= zero_right;
2394
        alu_ctrl   <= alu_nop;
2395
        cc_ctrl    <= latch_cc;
2396
        sp_ctrl    <= latch_sp;
2397
        next_state <= dual_op_write16_state;
2398
 
2399
      when others =>
2400
        next_state   <= dual_op_read8_state;
2401
 
2402
      end case;
2403
 
2404
    when "1010" => -- acca indexed
2405
      -- increment the pc
2406
      pc_ctrl    <= incr_pc;
2407
      case op_code(3 downto 0) is
2408
      when "0011" | -- subd x, cmpd x, cmpu x
2409
           "1100" | -- cmpx x, cmpy x. cmps ,x
2410
           "1110" => -- ldx x,  ldy x, undef x
2411
        st_ctrl      <= push_st;
2412
        return_state <= dual_op_read16_state;
2413
        next_state   <= indexed_state;
2414
 
2415
      when "0111" =>  -- staa ,x
2416
        st_ctrl      <= push_st;
2417
        return_state <= dual_op_write8_state;
2418
        next_state   <= indexed_state;
2419
 
2420
      when "1101" => -- jsr ,x
2421
        -- DO NOT pre decrement SP
2422
        st_ctrl      <= push_st;
2423
        return_state <= jsr_state;
2424
        next_state   <= indexed_state;
2425
 
2426
      when "1111" => -- stx ind, sty ind
2427
        st_ctrl      <= push_st;
2428
        return_state <= dual_op_write16_state;
2429
        next_state   <= indexed_state;
2430
 
2431
      when others =>
2432
        st_ctrl      <= push_st;
2433
        return_state <= dual_op_read8_state;
2434
        next_state   <= indexed_state;
2435
 
2436
      end case;
2437
 
2438
   when "1011" => -- acca extended
2439
     -- increment the pc
2440
     pc_ctrl    <= incr_pc;
2441
     case op_code(3 downto 0) is
2442
     when "0011" | -- subd >, cmpd >, cmpu >
2443
          "1100" | -- cmpx >, cmpy >, cmps >
2444
          "1110" => -- ldx >   ldy >, undef >
2445
       st_ctrl      <= push_st;
2446
       return_state <= dual_op_read16_state;
2447
       next_state   <= extended_state;
2448
 
2449
     when "0111" =>  -- staa >
2450
       st_ctrl      <= push_st;
2451
       return_state <= dual_op_write8_state;
2452
       next_state   <= extended_state;
2453
 
2454
     when "1101" => -- jsr >extended
2455
     -- DO NOT pre decrement sp
2456
       st_ctrl      <= push_st;
2457
       return_state <= jsr_state;
2458
       next_state   <= extended_state;
2459
 
2460
     when "1111" => -- stx >, sty >
2461
       st_ctrl      <= push_st;
2462
       return_state <= dual_op_write16_state;
2463
       next_state   <= extended_state;
2464
 
2465
     when others =>
2466
       st_ctrl      <= push_st;
2467
       return_state <= dual_op_read8_state;
2468
       next_state   <= extended_state;
2469
 
2470
     end case;
2471
 
2472
   when "1100" => -- accb immediate
2473
     -- increment the pc
2474
     pc_ctrl    <= incr_pc;
2475
     case op_code(3 downto 0) is
2476
     when "0011" | -- addd #, undef #, undef #
2477
          "1100" | -- ldd #, undef #, undef #
2478
          "1110" => -- ldu #, lds #, undef #
2479
       next_state   <= imm16_state;
2480
 
2481
     when others =>
2482
       lic          <= '1';
2483
       next_state   <= fetch_state;
2484
 
2485
     end case;
2486
 
2487
   when "1101" => -- accb direct
2488
     -- increment the pc
2489
     pc_ctrl    <= incr_pc;
2490
     case op_code(3 downto 0) is
2491
     when "0011" | -- addd <, undef <, undef <
2492
          "1100" | -- ldd <, undef <, undef <
2493
          "1110" => -- ldu, lds <, undef <
2494
       next_state   <= dual_op_read16_state;
2495
 
2496
     when "0111" =>  -- stab <
2497
       next_state   <= dual_op_write8_state;
2498
 
2499
     when "1101" =>  -- std <,
2500
       next_state   <= dual_op_write16_state;
2501
 
2502
     when "1111" => -- stu <, sts <
2503
       next_state   <= dual_op_write16_state;
2504
 
2505
     when others =>
2506
       next_state   <= dual_op_read8_state;
2507
 
2508
     end case;
2509
 
2510
   when "1110" => -- accb indexed
2511
     -- increment the pc
2512
     pc_ctrl    <= incr_pc;
2513
     case op_code(3 downto 0) is
2514
     when "0011" | -- addd x, undef x, undef x
2515
          "1100" | -- ldd x, undef x, undef x
2516
          "1110" => -- ldu x, lds x, undef x
2517
       st_ctrl      <= push_st;
2518
       return_state <= dual_op_read16_state;
2519
       next_state   <= indexed_state;
2520
 
2521
     when "0111" =>  -- stab x
2522
       st_ctrl      <= push_st;
2523
       return_state <= dual_op_write8_state;
2524
       next_state   <= indexed_state;
2525
 
2526
     when "1101" =>  -- std x
2527
       st_ctrl      <= push_st;
2528
       return_state <= dual_op_write16_state;
2529
       next_state   <= indexed_state;
2530
 
2531
     when "1111" => -- stu x, sts x, undef x
2532
       st_ctrl      <= push_st;
2533
       return_state <= dual_op_write16_state;
2534
       next_state   <= indexed_state;
2535
 
2536
     when others =>
2537
       st_ctrl      <= push_st;
2538
       return_state <= dual_op_read8_state;
2539
       next_state   <= indexed_state;
2540
 
2541
     end case;
2542
 
2543
   when "1111" => -- accb extended
2544
     -- increment the pc
2545
     pc_ctrl    <= incr_pc;
2546
     case op_code(3 downto 0) is
2547
     when "0011" | -- addd >, undef >, undef >
2548
                    "1100" | -- ldd >, undef >, undef >
2549
               "1110" => -- ldu >, lds >, undef >
2550
            st_ctrl      <= push_st;
2551
            return_state <= dual_op_read16_state;
2552
       next_state   <= extended_state;
2553
 
2554
     when "0111" =>  -- stab extended
2555
            st_ctrl      <= push_st;
2556
            return_state <= dual_op_write8_state;
2557
       next_state   <= extended_state;
2558
 
2559
     when "1101" =>  -- std extended
2560
       st_ctrl      <= push_st;
2561
            return_state <= dual_op_write16_state;
2562
            next_state   <= extended_state;
2563
 
2564
          when "1111" => -- stu  extended
2565
            st_ctrl      <= push_st;
2566
            return_state <= dual_op_write16_state;
2567
            next_state   <= extended_state;
2568
 
2569
          when others =>
2570
            st_ctrl      <= push_st;
2571
            return_state <= dual_op_read8_state;
2572
            next_state   <= extended_state;
2573
     end case;
2574
        --
2575
   -- not sure why I need this
2576
   --   
2577
   when others =>
2578
          lic <= '1';
2579
          next_state <= fetch_state;
2580
        end case;
2581
 
2582
 
2583
           --
2584
                          -- here if ea holds low byte
2585
                          -- Direct
2586
                          -- Extended
2587
                          -- Indexed
2588
                          -- read memory location
2589
                          --
2590
                          when single_op_read_state =>
2591
                                        -- read memory into md
2592
                                   md_ctrl    <= fetch_first_md;
2593
               addr_ctrl  <= read_ad;
2594
                                        dout_ctrl  <= md_lo_dout;
2595
                                        next_state <= single_op_exec_state;
2596
 
2597
                when single_op_exec_state =>
2598
                    case op_code(3 downto 0) is
2599
                         when "0000" => -- neg
2600
                   left_ctrl  <= md_left;
2601
                                            right_ctrl <= zero_right;
2602
                                            alu_ctrl   <= alu_neg;
2603
                                            cc_ctrl    <= load_cc;
2604
                                       md_ctrl    <= load_md;
2605
                                       next_state <= single_op_write_state;
2606
                    when "0011" => -- com
2607
                   left_ctrl  <= md_left;
2608
                             right_ctrl <= zero_right;
2609
                                            alu_ctrl   <= alu_com;
2610
                                            cc_ctrl    <= load_cc;
2611
                                       md_ctrl    <= load_md;
2612
                                       next_state <= single_op_write_state;
2613
                         when "0100" => -- lsr
2614
                   left_ctrl  <= md_left;
2615
                                                 right_ctrl <= zero_right;
2616
                                            alu_ctrl   <= alu_lsr8;
2617
                                            cc_ctrl    <= load_cc;
2618
                                       md_ctrl    <= load_md;
2619
                                       next_state <= single_op_write_state;
2620
                         when "0110" => -- ror
2621
                   left_ctrl  <= md_left;
2622
                                                 right_ctrl <= zero_right;
2623
                                            alu_ctrl   <= alu_ror8;
2624
                                            cc_ctrl    <= load_cc;
2625
                                       md_ctrl    <= load_md;
2626
                                       next_state <= single_op_write_state;
2627
                         when "0111" => -- asr
2628
                   left_ctrl  <= md_left;
2629
                                                 right_ctrl <= zero_right;
2630
                                            alu_ctrl   <= alu_asr8;
2631
                                            cc_ctrl    <= load_cc;
2632
                                       md_ctrl    <= load_md;
2633
                                       next_state <= single_op_write_state;
2634
                         when "1000" => -- asl
2635
                   left_ctrl  <= md_left;
2636
                                                 right_ctrl <= zero_right;
2637
                                            alu_ctrl   <= alu_asl8;
2638
                                            cc_ctrl    <= load_cc;
2639
                                       md_ctrl    <= load_md;
2640
                                       next_state <= single_op_write_state;
2641
                         when "1001" => -- rol
2642
                   left_ctrl  <= md_left;
2643
                                                 right_ctrl <= zero_right;
2644
                                            alu_ctrl   <= alu_rol8;
2645
                                            cc_ctrl    <= load_cc;
2646
                                       md_ctrl    <= load_md;
2647
                                       next_state <= single_op_write_state;
2648
                         when "1010" => -- dec
2649
                   left_ctrl  <= md_left;
2650
                             right_ctrl <= one_right;
2651
                                            alu_ctrl   <= alu_dec;
2652
                                            cc_ctrl    <= load_cc;
2653
                                       md_ctrl    <= load_md;
2654
                                       next_state <= single_op_write_state;
2655
                         when "1011" => -- undefined
2656
                   lic        <= '1';
2657
                                       next_state <= fetch_state;
2658
                         when "1100" => -- inc
2659
                   left_ctrl  <= md_left;
2660
                             right_ctrl <= one_right;
2661
                                            alu_ctrl   <= alu_inc;
2662
                                            cc_ctrl    <= load_cc;
2663
                                       md_ctrl    <= load_md;
2664
                                       next_state <= single_op_write_state;
2665
                         when "1101" => -- tst
2666
                   left_ctrl  <= md_left;
2667
                             right_ctrl <= zero_right;
2668
                                            alu_ctrl   <= alu_st8;
2669
                                            cc_ctrl    <= load_cc;
2670
                   lic        <= '1';
2671
                                       next_state <= fetch_state;
2672
                         when "1110" => -- jmp
2673
                   left_ctrl  <= md_left;
2674
                                                 right_ctrl <= zero_right;
2675
                                            alu_ctrl   <= alu_ld16;
2676
                   pc_ctrl    <= load_pc;
2677
                   lic          <= '1';
2678
                                       next_state <= fetch_state;
2679
                         when "1111" => -- clr
2680
                   left_ctrl  <= md_left;
2681
                                                 right_ctrl <= zero_right;
2682
                                            alu_ctrl   <= alu_clr;
2683
                                            cc_ctrl    <= load_cc;
2684
                                       md_ctrl    <= load_md;
2685
                                       next_state <= single_op_write_state;
2686
                         when others =>
2687
                 lic        <= '1';
2688
                                     next_state <= fetch_state;
2689
                         end case;
2690
           --
2691
                          -- single operand 8 bit write
2692
                          -- Write low 8 bits of ALU output
2693
                          -- EA holds address
2694
                          -- MD holds data
2695
                          --
2696
                          when single_op_write_state =>
2697
                                 -- write ALU low byte output
2698
             addr_ctrl  <= write_ad;
2699
             dout_ctrl  <= md_lo_dout;
2700
             lic        <= '1';
2701
                                 next_state <= fetch_state;
2702
 
2703
           --
2704
                          -- here if ea holds address of low byte
2705
                          -- read memory location
2706
                          --
2707
                          when dual_op_read8_state =>
2708
                                   -- read first data byte from ea
2709
                                   md_ctrl    <= fetch_first_md;
2710
               addr_ctrl  <= read_ad;
2711
               lic        <= '1';
2712
                                        next_state <= fetch_state;
2713
 
2714
                                --
2715
                                -- Here to read a 16 bit value into MD
2716
                                -- pointed to by the EA register
2717
                                -- The first byte is read
2718
                                -- and the EA is incremented
2719
                                --
2720
                           when dual_op_read16_state =>
2721
                                        -- increment the effective address
2722
               left_ctrl  <= ea_left;
2723
               right_ctrl <= one_right;
2724
               alu_ctrl   <= alu_add16;
2725
               ea_ctrl    <= load_ea;
2726
                                        -- read the high byte of the 16 bit data
2727
                                   md_ctrl    <= fetch_first_md;
2728
               addr_ctrl  <= read_ad;
2729
                                        next_state <= dual_op_read16_2_state;
2730
 
2731
                                --
2732
                                -- here to read the second byte
2733
                           -- pointed to by EA into MD
2734
                                --
2735
                           when dual_op_read16_2_state =>
2736
                                        -- read the low byte of the 16 bit data
2737
                                   md_ctrl    <= fetch_next_md;
2738
               addr_ctrl  <= read_ad;
2739
               lic        <= '1';
2740
                                        next_state <= fetch_state;
2741
 
2742
           --
2743
                          -- 16 bit Write state
2744
                          -- EA hold address of memory to write to
2745
                          -- Advance the effective address in ALU
2746
                          -- decode op_code to determine which
2747
                          -- register to write
2748
                          --
2749
                          when dual_op_write16_state =>
2750
                                 -- increment the effective address
2751
                                 left_ctrl  <= ea_left;
2752
                                 right_ctrl <= one_right;
2753
                                 alu_ctrl   <= alu_add16;
2754
                            ea_ctrl    <= load_ea;
2755
                                 -- write the ALU hi byte at ea
2756
             addr_ctrl  <= write_ad;
2757
                                 if op_code(6) = '0' then
2758
                                   case op_code(3 downto 0) is
2759
                              when "1111" => -- stx / sty
2760
                                          case pre_code is
2761
                                          when "00010000" => -- page 2 -- sty
2762
                        dout_ctrl  <= iy_hi_dout;
2763
                                     when others =>     -- page 1 -- stx
2764
                   dout_ctrl  <= ix_hi_dout;
2765
                                          end case;
2766
                                   when others =>
2767
                 dout_ctrl  <= md_hi_dout;
2768
                                   end case;
2769
             else
2770
                                   case op_code(3 downto 0) is
2771
                              when "1101" => -- std
2772
                 dout_ctrl  <= acca_dout; -- acca is high byte of ACCD
2773
                              when "1111" => -- stu / sts
2774
                                          case pre_code is
2775
                                          when "00010000" => -- page 2 -- sts
2776
                        dout_ctrl  <= sp_hi_dout;
2777
                                          when others =>     -- page 1 -- stu
2778
                        dout_ctrl  <= up_hi_dout;
2779
                                          end case;
2780
                                   when others =>
2781
                 dout_ctrl  <= md_hi_dout;
2782
                                   end case;
2783
             end if;
2784
                                 next_state   <= dual_op_write8_state;
2785
 
2786
           --
2787
                          -- Dual operand 8 bit write
2788
           -- Write 8 bit accumulator
2789
                          -- or low byte of 16 bit register
2790
                          -- EA holds address
2791
                          -- decode opcode to determine
2792
                          -- which register to apply to the bus
2793
                          -- Also set the condition codes here
2794
                          --
2795
                          when dual_op_write8_state =>
2796
                            if op_code(6) = '0' then
2797
                                   case op_code(3 downto 0) is
2798
                                        when "0111" => -- sta
2799
                 dout_ctrl  <= acca_dout;
2800
                                        when "1111" => -- stx / sty
2801
                                          case pre_code is
2802
                                          when "00010000" => -- page 2 -- sty
2803
                        dout_ctrl  <= iy_lo_dout;
2804
                                     when others =>     -- page 1 -- stx
2805
                   dout_ctrl  <= ix_lo_dout;
2806
                                          end case;
2807
                                        when others =>
2808
                 dout_ctrl  <= md_lo_dout;
2809
                                        end case;
2810
             else
2811
                                   case op_code(3 downto 0) is
2812
                                        when "0111" => -- stb
2813
                 dout_ctrl  <= accb_dout;
2814
                                        when "1101" => -- std
2815
                 dout_ctrl  <= accb_dout; -- accb is low byte of accd
2816
                                        when "1111" => -- stu / sts
2817
                                          case pre_code is
2818
                                          when "00010000" => -- page 2 -- sts
2819
                        dout_ctrl  <= sp_lo_dout;
2820
                                          when others =>     -- page 1 -- stu
2821
                        dout_ctrl  <= up_lo_dout;
2822
                                          end case;
2823
                                        when others =>
2824
                 dout_ctrl  <= md_lo_dout;
2825
                                        end case;
2826
             end if;
2827
                                 -- write ALU low byte output
2828
             addr_ctrl    <= write_ad;
2829
             lic          <= '1';
2830
                                 next_state   <= fetch_state;
2831
 
2832
                          --
2833
                          -- 16 bit immediate addressing mode
2834
                          --
2835
                          when imm16_state =>
2836
                                   -- increment pc
2837
               pc_ctrl    <= incr_pc;
2838
                                   -- fetch next immediate byte
2839
                              md_ctrl    <= fetch_next_md;
2840
               addr_ctrl  <= fetch_ad;
2841
               lic        <= '1';
2842
                                        next_state <= fetch_state;
2843
 
2844
           --
2845
                          -- md & ea holds 8 bit index offset
2846
                          -- calculate the effective memory address
2847
                          -- using the alu
2848
                          --
2849
           when indexed_state =>
2850
                                 --
2851
                                 -- decode indexing mode
2852
                                 --
2853
                                 if md(7) = '0' then
2854
                                   case md(6 downto 5) is
2855
                                        when "00" =>
2856
                                left_ctrl  <= ix_left;
2857
                                        when "01" =>
2858
                                left_ctrl  <= iy_left;
2859
                                        when "10" =>
2860
                                left_ctrl  <= up_left;
2861
                                        when others =>
2862
                                        -- when "11" =>
2863
                                left_ctrl  <= sp_left;
2864
                                        end case;
2865
                                   right_ctrl   <= md_sign5_right;
2866
                                   alu_ctrl     <= alu_add16;
2867
               ea_ctrl      <= load_ea;
2868
                                        next_state   <= saved_state;
2869
 
2870
                                 else
2871
                                   case md(3 downto 0) is
2872
                                        when "0000" =>     -- ,R+
2873
                                     case md(6 downto 5) is
2874
                                          when "00" =>
2875
                                  left_ctrl  <= ix_left;
2876
                                          when "01" =>
2877
                                  left_ctrl  <= iy_left;
2878
                                          when "10" =>
2879
                                  left_ctrl  <= up_left;
2880
                                          when others =>
2881
                                  left_ctrl  <= sp_left;
2882
                                          end case;
2883
                                          --
2884
                                     right_ctrl <= zero_right;
2885
                                     alu_ctrl   <= alu_add16;
2886
                 ea_ctrl    <= load_ea;
2887
                 next_state <= postincr1_state;
2888
 
2889
                                        when "0001" =>     -- ,R++
2890
                                     case md(6 downto 5) is
2891
                                          when "00" =>
2892
                                  left_ctrl  <= ix_left;
2893
                                          when "01" =>
2894
                                  left_ctrl  <= iy_left;
2895
                                          when "10" =>
2896
                                  left_ctrl  <= up_left;
2897
                                          when others =>
2898
                                          -- when "11" =>
2899
                                  left_ctrl  <= sp_left;
2900
                                          end case;
2901
                                     right_ctrl <= zero_right;
2902
                                     alu_ctrl   <= alu_add16;
2903
                 ea_ctrl    <= load_ea;
2904
                 next_state <= postincr2_state;
2905
 
2906
                                        when "0010" =>     -- ,-R
2907
                                     case md(6 downto 5) is
2908
                                          when "00" =>
2909
                                  left_ctrl  <= ix_left;
2910
                   ix_ctrl    <= load_ix;
2911
                                          when "01" =>
2912
                                  left_ctrl  <= iy_left;
2913
                   iy_ctrl    <= load_iy;
2914
                                          when "10" =>
2915
                                  left_ctrl  <= up_left;
2916
                   up_ctrl    <= load_up;
2917
                                          when others =>
2918
                                          -- when "11" =>
2919
                                  left_ctrl  <= sp_left;
2920
                   sp_ctrl    <= load_sp;
2921
                                          end case;
2922
                                     right_ctrl   <= one_right;
2923
                                     alu_ctrl     <= alu_sub16;
2924
                 ea_ctrl      <= load_ea;
2925
                                          next_state   <= saved_state;
2926
 
2927
                                        when "0011" =>     -- ,--R
2928
                                     case md(6 downto 5) is
2929
                                          when "00" =>
2930
                                  left_ctrl  <= ix_left;
2931
                   ix_ctrl    <= load_ix;
2932
                                          when "01" =>
2933
                                  left_ctrl  <= iy_left;
2934
                   iy_ctrl    <= load_iy;
2935
                                          when "10" =>
2936
                                  left_ctrl  <= up_left;
2937
                   up_ctrl    <= load_up;
2938
                                          when others =>
2939
                                          -- when "11" =>
2940
                                  left_ctrl  <= sp_left;
2941
                   sp_ctrl    <= load_sp;
2942
                                          end case;
2943
                                     right_ctrl <= two_right;
2944
                                     alu_ctrl   <= alu_sub16;
2945
                 ea_ctrl    <= load_ea;
2946
                                          if md(4) = '0' then
2947
                                            next_state   <= saved_state;
2948
                                          else
2949
                                            next_state   <= indirect_state;
2950
                                          end if;
2951
 
2952
                                        when "0100" =>     -- ,R (zero offset)
2953
                                     case md(6 downto 5) is
2954
                                          when "00" =>
2955
                                  left_ctrl  <= ix_left;
2956
                                          when "01" =>
2957
                                  left_ctrl  <= iy_left;
2958
                                          when "10" =>
2959
                                  left_ctrl  <= up_left;
2960
                                          when others =>
2961
                                          -- when "11" =>
2962
                                  left_ctrl  <= sp_left;
2963
                                          end case;
2964
                                     right_ctrl <= zero_right;
2965
                                     alu_ctrl   <= alu_add16;
2966
                 ea_ctrl    <= load_ea;
2967
                                          if md(4) = '0' then
2968
                                            next_state   <= saved_state;
2969
                                          else
2970
                                            next_state   <= indirect_state;
2971
                                          end if;
2972
 
2973
                                        when "0101" =>     -- ACCB,R
2974
                                     case md(6 downto 5) is
2975
                                          when "00" =>
2976
                                  left_ctrl  <= ix_left;
2977
                                          when "01" =>
2978
                                  left_ctrl  <= iy_left;
2979
                                          when "10" =>
2980
                                  left_ctrl  <= up_left;
2981
                                          when others =>
2982
                                          -- when "11" =>
2983
                                  left_ctrl  <= sp_left;
2984
                                          end case;
2985
                                     right_ctrl <= accb_right;
2986
                                     alu_ctrl   <= alu_add16;
2987
                 ea_ctrl    <= load_ea;
2988
                                          if md(4) = '0' then
2989
                                            next_state   <= saved_state;
2990
                                          else
2991
                                            next_state   <= indirect_state;
2992
                                          end if;
2993
 
2994
                                        when "0110" =>     -- ACCA,R
2995
                                     case md(6 downto 5) is
2996
                                          when "00" =>
2997
                                  left_ctrl  <= ix_left;
2998
                                          when "01" =>
2999
                                  left_ctrl  <= iy_left;
3000
                                          when "10" =>
3001
                                  left_ctrl  <= up_left;
3002
                                          when others =>
3003
                                          -- when "11" =>
3004
                                  left_ctrl  <= sp_left;
3005
                                          end case;
3006
                                     right_ctrl <= acca_right;
3007
                                     alu_ctrl   <= alu_add16;
3008
                 ea_ctrl    <= load_ea;
3009
                                          if md(4) = '0' then
3010
                                            next_state   <= saved_state;
3011
                                          else
3012
                                            next_state   <= indirect_state;
3013
                                          end if;
3014
 
3015
                                        when "0111" =>     -- undefined
3016
                                     case md(6 downto 5) is
3017
                                          when "00" =>
3018
                                  left_ctrl  <= ix_left;
3019
                                          when "01" =>
3020
                                  left_ctrl  <= iy_left;
3021
                                          when "10" =>
3022
                                  left_ctrl  <= up_left;
3023
                                          when others =>
3024
                                          -- when "11" =>
3025
                                  left_ctrl  <= sp_left;
3026
                                          end case;
3027
                                     right_ctrl <= zero_right;
3028
                                     alu_ctrl   <= alu_add16;
3029
                 ea_ctrl    <= load_ea;
3030
                                          if md(4) = '0' then
3031
                                            next_state   <= saved_state;
3032
                                          else
3033
                                            next_state   <= indirect_state;
3034
                                          end if;
3035
 
3036
                                        when "1000" =>     -- offset8,R
3037
                 md_ctrl    <= fetch_first_md; -- pick up 8 bit offset
3038
                 addr_ctrl  <= fetch_ad;
3039
                 pc_ctrl    <= incr_pc;
3040
                 next_state <= index8_state;
3041
 
3042
                                        when "1001" =>     -- offset16,R
3043
                 md_ctrl    <= fetch_first_md; -- pick up first byte of 16 bit offset
3044
                 addr_ctrl  <= fetch_ad;
3045
                 pc_ctrl    <= incr_pc;
3046
                 next_state <= index16_state;
3047
 
3048
                                        when "1010" =>     -- undefined
3049
                                     case md(6 downto 5) is
3050
                                          when "00" =>
3051
                                  left_ctrl  <= ix_left;
3052
                                          when "01" =>
3053
                                  left_ctrl  <= iy_left;
3054
                                          when "10" =>
3055
                                  left_ctrl  <= up_left;
3056
                                          when others =>
3057
                                          -- when "11" =>
3058
                                  left_ctrl  <= sp_left;
3059
                                          end case;
3060
                                     right_ctrl <= zero_right;
3061
                                     alu_ctrl   <= alu_add16;
3062
                 ea_ctrl    <= load_ea;
3063
                                          --
3064
                                          if md(4) = '0' then
3065
                                            next_state   <= saved_state;
3066
                                          else
3067
                                            next_state   <= indirect_state;
3068
                                          end if;
3069
 
3070
                                        when "1011" =>     -- ACCD,R
3071
                                     case md(6 downto 5) is
3072
                                          when "00" =>
3073
                                  left_ctrl  <= ix_left;
3074
                                          when "01" =>
3075
                                  left_ctrl  <= iy_left;
3076
                                          when "10" =>
3077
                                  left_ctrl  <= up_left;
3078
                                          when others =>
3079
                                          -- when "11" =>
3080
                                  left_ctrl  <= sp_left;
3081
                                          end case;
3082
                                     right_ctrl <= accd_right;
3083
                                     alu_ctrl   <= alu_add16;
3084
                 ea_ctrl    <= load_ea;
3085
                                          if md(4) = '0' then
3086
                                            next_state   <= saved_state;
3087
                                          else
3088
                                            next_state   <= indirect_state;
3089
                                          end if;
3090
 
3091
                                        when "1100" =>     -- offset8,PC
3092
                                          -- fetch 8 bit offset
3093
                 md_ctrl    <= fetch_first_md;
3094
                 addr_ctrl  <= fetch_ad;
3095
                 pc_ctrl    <= incr_pc;
3096
                 next_state <= pcrel8_state;
3097
 
3098
                                        when "1101" =>     -- offset16,PC
3099
                                          -- fetch offset
3100
                 md_ctrl    <= fetch_first_md;
3101
                 addr_ctrl  <= fetch_ad;
3102
                 pc_ctrl    <= incr_pc;
3103
                 next_state <= pcrel16_state;
3104
 
3105
                                        when "1110" =>     -- undefined
3106
                                     case md(6 downto 5) is
3107
                                          when "00" =>
3108
                                  left_ctrl  <= ix_left;
3109
                                          when "01" =>
3110
                                  left_ctrl  <= iy_left;
3111
                                          when "10" =>
3112
                                  left_ctrl  <= up_left;
3113
                                          when others =>
3114
                                          -- when "11" =>
3115
                                  left_ctrl  <= sp_left;
3116
                                          end case;
3117
                                     right_ctrl <= zero_right;
3118
                                     alu_ctrl   <= alu_add16;
3119
                 ea_ctrl    <= load_ea;
3120
                                          if md(4) = '0' then
3121
                                            next_state   <= saved_state;
3122
                                          else
3123
                                            next_state   <= indirect_state;
3124
                                          end if;
3125
 
3126
               when others =>
3127
--                      when "1111" =>     -- [,address]
3128
                                          -- advance PC to pick up address
3129
                 md_ctrl    <= fetch_first_md;
3130
                 addr_ctrl  <= fetch_ad;
3131
                                          pc_ctrl    <= incr_pc;
3132
                 next_state <= indexaddr_state;
3133
                                        end case;
3134
                                 end if;
3135
 
3136
                          -- load index register with ea plus one
3137
                          when postincr1_state =>
3138
                            left_ctrl  <= ea_left;
3139
                            right_ctrl <= one_right;
3140
                            alu_ctrl   <= alu_add16;
3141
                                 case md(6 downto 5) is
3142
                            when "00" =>
3143
               ix_ctrl    <= load_ix;
3144
                                 when "01" =>
3145
               iy_ctrl    <= load_iy;
3146
                                 when "10" =>
3147
               up_ctrl    <= load_up;
3148
                                 when others =>
3149
                                 -- when "11" =>
3150
               sp_ctrl    <= load_sp;
3151
                            end case;
3152
                                 -- return to previous state
3153
                            if md(4) = '0' then
3154
                                         next_state   <= saved_state;
3155
                                 else
3156
                                         next_state   <= indirect_state;
3157
                                 end if;
3158
 
3159
                          -- load index register with ea plus two
3160
                          when postincr2_state =>
3161
                                 -- increment register by two (address)
3162
                            left_ctrl  <= ea_left;
3163
                            right_ctrl <= two_right;
3164
                            alu_ctrl   <= alu_add16;
3165
                                 case md(6 downto 5) is
3166
                            when "00" =>
3167
               ix_ctrl    <= load_ix;
3168
                                 when "01" =>
3169
               iy_ctrl    <= load_iy;
3170
                                 when "10" =>
3171
               up_ctrl    <= load_up;
3172
                                 when others =>
3173
                                 -- when "11" =>
3174
               sp_ctrl    <= load_sp;
3175
                            end case;
3176
                                 -- return to previous state
3177
                            if md(4) = '0' then
3178
                                         next_state   <= saved_state;
3179
                                 else
3180
                                         next_state   <= indirect_state;
3181
                                 end if;
3182
           --
3183
                          -- ea = index register + md (8 bit signed offset)
3184
                          -- ea holds post byte
3185
                          --
3186
                          when index8_state =>
3187
                                 case ea(6 downto 5) is
3188
                            when "00" =>
3189
                              left_ctrl  <= ix_left;
3190
                            when "01" =>
3191
                              left_ctrl  <= iy_left;
3192
                                 when "10" =>
3193
                              left_ctrl  <= up_left;
3194
                                 when others =>
3195
                                 -- when "11" =>
3196
                              left_ctrl  <= sp_left;
3197
                                 end case;
3198
                                 -- ea = index reg + md
3199
                            right_ctrl <= md_sign8_right;
3200
                            alu_ctrl   <= alu_add16;
3201
             ea_ctrl    <= load_ea;
3202
                                 -- return to previous state
3203
                            if ea(4) = '0' then
3204
                                         next_state   <= saved_state;
3205
                                 else
3206
                                         next_state   <= indirect_state;
3207
                                 end if;
3208
 
3209
                          -- fetch low byte of 16 bit indexed offset
3210
                          when index16_state =>
3211
                                 -- advance pc
3212
             pc_ctrl    <= incr_pc;
3213
                                 -- fetch low byte
3214
             md_ctrl    <= fetch_next_md;
3215
             addr_ctrl  <= fetch_ad;
3216
                                 next_state <= index16_2_state;
3217
 
3218
                          -- ea = index register + md (16 bit offset)
3219
                          -- ea holds post byte
3220
                          when index16_2_state =>
3221
                                 case ea(6 downto 5) is
3222
                            when "00" =>
3223
                              left_ctrl  <= ix_left;
3224
                            when "01" =>
3225
                              left_ctrl  <= iy_left;
3226
                                 when "10" =>
3227
                              left_ctrl  <= up_left;
3228
                                 when others =>
3229
                                 -- when "11" =>
3230
                              left_ctrl  <= sp_left;
3231
                                 end case;
3232
                                 -- ea = index reg + md
3233
                            right_ctrl <= md_right;
3234
                            alu_ctrl   <= alu_add16;
3235
             ea_ctrl    <= load_ea;
3236
                                 -- return to previous state
3237
                            if ea(4) = '0' then
3238
                                         next_state   <= saved_state;
3239
                                 else
3240
                                         next_state   <= indirect_state;
3241
                                 end if;
3242
           --
3243
                          -- pc relative with 8 bit signed offest
3244
                          -- md holds signed offset
3245
                          --
3246
                          when pcrel8_state =>
3247
                                 -- ea = pc + signed md
3248
                            left_ctrl  <= pc_left;
3249
                            right_ctrl <= md_sign8_right;
3250
                            alu_ctrl   <= alu_add16;
3251
             ea_ctrl    <= load_ea;
3252
                                 -- return to previous state
3253
                            if ea(4) = '0' then
3254
                                         next_state   <= saved_state;
3255
                                 else
3256
                                         next_state   <= indirect_state;
3257
                                 end if;
3258
 
3259
                          -- pc relative addressing with 16 bit offset
3260
                          -- pick up the low byte of the offset in md
3261
                          -- advance the pc
3262
                          when pcrel16_state =>
3263
                                 -- advance pc
3264
             pc_ctrl    <= incr_pc;
3265
                                 -- fetch low byte
3266
             md_ctrl    <= fetch_next_md;
3267
             addr_ctrl  <= fetch_ad;
3268
                                 next_state <= pcrel16_2_state;
3269
 
3270
                          -- pc relative with16 bit signed offest
3271
                          -- md holds signed offset
3272
                          when pcrel16_2_state =>
3273
                                 -- ea = pc +  md
3274
                            left_ctrl  <= pc_left;
3275
                            right_ctrl <= md_right;
3276
                            alu_ctrl   <= alu_add16;
3277
             ea_ctrl    <= load_ea;
3278
                                 -- return to previous state
3279
                            if ea(4) = '0' then
3280
                                         next_state   <= saved_state;
3281
                                 else
3282
                                         next_state   <= indirect_state;
3283
                                 end if;
3284
 
3285
                          -- indexed to address
3286
                          -- pick up the low byte of the address
3287
                          -- advance the pc
3288
                          when indexaddr_state =>
3289
                                 -- advance pc
3290
             pc_ctrl    <= incr_pc;
3291
                                 -- fetch low byte
3292
             md_ctrl    <= fetch_next_md;
3293
             addr_ctrl  <= fetch_ad;
3294
                                 next_state <= indexaddr2_state;
3295
 
3296
                          -- indexed to absolute address
3297
                          -- md holds address
3298
                          -- ea hold indexing mode byte
3299
                          when indexaddr2_state =>
3300
                                 -- ea = md
3301
                            left_ctrl  <= pc_left;
3302
                            right_ctrl <= md_right;
3303
                            alu_ctrl   <= alu_ld16;
3304
             ea_ctrl    <= load_ea;
3305
                                 -- return to previous state
3306
                            if ea(4) = '0' then
3307
                                         next_state   <= saved_state;
3308
                                 else
3309
                                         next_state   <= indirect_state;
3310
                                 end if;
3311
 
3312
           --
3313
                          -- load md with high byte of indirect address
3314
                          -- pointed to by ea
3315
                          -- increment ea
3316
                          --
3317
                          when indirect_state =>
3318
                                 -- increment ea
3319
                            left_ctrl  <= ea_left;
3320
                            right_ctrl <= one_right;
3321
                            alu_ctrl   <= alu_add16;
3322
             ea_ctrl    <= load_ea;
3323
                                 -- fetch high byte
3324
             md_ctrl    <= fetch_first_md;
3325
             addr_ctrl  <= read_ad;
3326
                                 next_state <= indirect2_state;
3327
           --
3328
                          -- load md with low byte of indirect address
3329
                          -- pointed to by ea
3330
                          -- ea has previously been incremented
3331
                          --
3332
                          when indirect2_state =>
3333
                                 -- fetch high byte
3334
             md_ctrl    <= fetch_next_md;
3335
             addr_ctrl  <= read_ad;
3336
             dout_ctrl  <= md_lo_dout;
3337
                                 next_state <= indirect3_state;
3338
                          --
3339
                          -- complete idirect addressing
3340
                          -- by loading ea with md
3341
                          --
3342
                          when indirect3_state =>
3343
                                 -- load ea with md
3344
                            left_ctrl  <= ea_left;
3345
                            right_ctrl <= md_right;
3346
                            alu_ctrl   <= alu_ld16;
3347
             ea_ctrl    <= load_ea;
3348
                                 -- return to previous state
3349
                                 next_state   <= saved_state;
3350
 
3351
           --
3352
                          -- ea holds the low byte of the absolute address
3353
                          -- Move ea low byte into ea high byte
3354
                          -- load new ea low byte to for absolute 16 bit address
3355
                          -- advance the program counter
3356
                          --
3357
                          when extended_state => -- fetch ea low byte
3358
                                        -- increment pc
3359
               pc_ctrl      <= incr_pc;
3360
                                        -- fetch next effective address bytes
3361
                                        ea_ctrl      <= fetch_next_ea;
3362
               addr_ctrl    <= fetch_ad;
3363
                                   -- return to previous state
3364
                                   next_state   <= saved_state;
3365
 
3366
                                when lea_state => -- here on load effective address
3367
                                        -- load index register with effective address
3368
               left_ctrl  <= pc_left;
3369
                                        right_ctrl <= ea_right;
3370
                                   alu_ctrl   <= alu_lea;
3371
                                        case op_code(3 downto 0) is
3372
                                        when "0000" => -- leax
3373
                   cc_ctrl    <= load_cc;
3374
                   ix_ctrl    <= load_ix;
3375
                                        when "0001" => -- leay
3376
                   cc_ctrl    <= load_cc;
3377
                   iy_ctrl    <= load_iy;
3378
                                        when "0010" => -- leas
3379
                   sp_ctrl    <= load_sp;
3380
                                        when "0011" => -- leau
3381
                   up_ctrl    <= load_up;
3382
                                        when others =>
3383
                                            null;
3384
                                        end case;
3385
               lic          <= '1';
3386
               next_state   <= fetch_state;
3387
 
3388
                                --
3389
                                -- jump to subroutine
3390
                                -- sp=sp-1
3391
                                -- call push_return_lo_state to save pc
3392
                                -- return to jmp_state
3393
                                --
3394
                                when jsr_state =>
3395
                                        -- decrement sp
3396
               left_ctrl    <= sp_left;
3397
                                        right_ctrl   <= one_right;
3398
                                   alu_ctrl     <= alu_sub16;
3399
               sp_ctrl      <= load_sp;
3400
                                        -- call push_return_state
3401
                                        st_ctrl      <= push_st;
3402
                                        return_state <= jmp_state;
3403
               next_state   <= push_return_lo_state;
3404
 
3405
                                --
3406
                                -- Load pc with ea
3407
                                -- (JMP)
3408
                                --
3409
                                when jmp_state =>
3410
                                        -- load PC with effective address
3411
               left_ctrl  <= pc_left;
3412
                                        right_ctrl <= ea_right;
3413
                                   alu_ctrl   <= alu_ld16;
3414
                                        pc_ctrl    <= load_pc;
3415
               lic        <= '1';
3416
               next_state <= fetch_state;
3417
 
3418
                                --
3419
                                -- long branch or branch to subroutine
3420
                                -- pick up next md byte
3421
                                -- md_hi = md_lo
3422
                                -- md_lo = (pc)
3423
                                -- pc=pc+1
3424
                                -- if a lbsr push return address
3425
                                -- continue to sbranch_state
3426
                                -- to evaluate conditional branches
3427
                                --
3428
                                when lbranch_state =>
3429
                                        pc_ctrl    <= incr_pc;
3430
                                        -- fetch the next byte into md_lo
3431
               md_ctrl    <= fetch_next_md;
3432
               addr_ctrl  <= fetch_ad;
3433
                                        -- if lbsr - push return address
3434
                                        -- then continue on to short branch
3435
                                        if op_code = "00010111" then
3436
                                          st_ctrl      <= push_st;
3437
                                          return_state <= sbranch_state;
3438
                 next_state   <= push_return_lo_state;
3439
                                        else
3440
                 next_state   <= sbranch_state;
3441
                                        end if;
3442
 
3443
                                 --
3444
                                 -- here to execute conditional branch
3445
                                 -- short conditional branch md = signed 8 bit offset
3446
                                 -- long branch md = 16 bit offset
3447
                                 -- 
3448
                  when sbranch_state =>
3449
               left_ctrl  <= pc_left;
3450
                                        right_ctrl <= md_right;
3451
                                   alu_ctrl   <= alu_add16;
3452
                                        -- Test condition for branch
3453
                              if op_code(7 downto 4) = "0010" then -- conditional branch
3454
                 case op_code(3 downto 0) is
3455
                           when "0000" => -- bra
3456
                                            cond_true := (1 = 1);
3457
                           when "0001" => -- brn
3458
                                            cond_true := (1 = 0);
3459
                           when "0010" => -- bhi
3460
                                            cond_true := ((cc(CBIT) or cc(ZBIT)) = '0');
3461
                           when "0011" => -- bls
3462
                                            cond_true := ((cc(CBIT) or cc(ZBIT)) = '1');
3463
                           when "0100" => -- bcc/bhs
3464
                                            cond_true := (cc(CBIT) = '0');
3465
                           when "0101" => -- bcs/blo
3466
                                            cond_true := (cc(CBIT) = '1');
3467
                           when "0110" => -- bne
3468
                             cond_true := (cc(ZBIT) = '0');
3469
                           when "0111" => -- beq
3470
                                            cond_true := (cc(ZBIT) = '1');
3471
                           when "1000" => -- bvc
3472
                                            cond_true := (cc(VBIT) = '0');
3473
                           when "1001" => -- bvs
3474
                                            cond_true := (cc(VBIT) = '1');
3475
                           when "1010" => -- bpl
3476
                                            cond_true := (cc(NBIT) = '0');
3477
                           when "1011" => -- bmi
3478
                                            cond_true := (cc(NBIT) = '1');
3479
                           when "1100" => -- bge
3480
                                            cond_true := ((cc(NBIT) xor cc(VBIT)) = '0');
3481
                           when "1101" => -- blt
3482
                                            cond_true := ((cc(NBIT) xor cc(VBIT)) = '1');
3483
                           when "1110" => -- bgt
3484
                                            cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0');
3485
                           when "1111" => -- ble
3486
                                            cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1');
3487
                           when others =>
3488
                                            null;
3489
                           end case;
3490
                                   end if;
3491
                                        if cond_true then
3492
                                          pc_ctrl    <= load_pc;
3493
               end if;
3494
               lic          <= '1';
3495
                                        next_state   <= fetch_state;
3496
 
3497
                                 --
3498
                                 -- push return address onto the S stack
3499
                                 --
3500
                                 -- (sp) = pc_lo
3501
                                 -- sp = sp - 1
3502
                                 --
3503
                                 when push_return_lo_state =>
3504
                                          -- decrement the sp
3505
                 left_ctrl  <= sp_left;
3506
                 right_ctrl <= one_right;
3507
                 alu_ctrl   <= alu_sub16;
3508
                 sp_ctrl    <= load_sp;
3509
                 -- write PC low
3510
                 addr_ctrl  <= pushs_ad;
3511
                 dout_ctrl  <= pc_lo_dout;
3512
                 next_state <= push_return_hi_state;
3513
 
3514
                                --
3515
                                -- push program counter hi byte onto the stack
3516
                                -- (sp) = pc_hi
3517
                                -- sp = sp
3518
                                -- return to originating state
3519
                                --
3520
                                when push_return_hi_state =>
3521
                                          -- write pc hi bytes
3522
                 addr_ctrl    <= pushs_ad;
3523
                 dout_ctrl    <= pc_hi_dout;
3524
                 next_state   <= saved_state;
3525
 
3526
             --
3527
             -- RTS pull return address from stack
3528
             --
3529
                                 when pull_return_hi_state =>
3530
                                          -- increment the sp
3531
                 left_ctrl  <= sp_left;
3532
                 right_ctrl <= one_right;
3533
                 alu_ctrl   <= alu_add16;
3534
                 sp_ctrl    <= load_sp;
3535
                 -- read pc hi
3536
                                          pc_ctrl    <= pull_hi_pc;
3537
                 addr_ctrl  <= pulls_ad;
3538
                 next_state <= pull_return_lo_state;
3539
 
3540
                                when pull_return_lo_state =>
3541
                                          -- increment the SP
3542
                 left_ctrl  <= sp_left;
3543
                 right_ctrl <= one_right;
3544
                 alu_ctrl   <= alu_add16;
3545
                 sp_ctrl    <= load_sp;
3546
                                          -- read pc low
3547
                                          pc_ctrl    <= pull_lo_pc;
3548
                 addr_ctrl  <= pulls_ad;
3549
                 dout_ctrl  <= pc_lo_dout;
3550
                                          --
3551
                 lic          <= '1';
3552
                 next_state   <= fetch_state;
3553
 
3554
                                 when andcc_state =>
3555
                                          -- AND CC with md
3556
                 left_ctrl  <= md_left;
3557
                 right_ctrl <= zero_right;
3558
                 alu_ctrl   <= alu_andcc;
3559
                 cc_ctrl    <= load_cc;
3560
                                          --
3561
                 lic        <= '1';
3562
                                     next_state <= fetch_state;
3563
 
3564
                                 when orcc_state =>
3565
                                          -- OR CC with md
3566
                 left_ctrl  <= md_left;
3567
                 right_ctrl <= zero_right;
3568
                 alu_ctrl   <= alu_orcc;
3569
                 cc_ctrl    <= load_cc;
3570
                                          --
3571
                 lic        <= '1';
3572
                                     next_state <= fetch_state;
3573
 
3574
                                 when tfr_state =>
3575
                                          -- select source register
3576
                                          case md(7 downto 4) is
3577
                                          when "0000" =>
3578
                                            left_ctrl <= accd_left;
3579
                                          when "0001" =>
3580
                                            left_ctrl <= ix_left;
3581
                                          when "0010" =>
3582
                                            left_ctrl <= iy_left;
3583
                                          when "0011" =>
3584
                                            left_ctrl <= up_left;
3585
                                          when "0100" =>
3586
                                            left_ctrl <= sp_left;
3587
                                          when "0101" =>
3588
                                            left_ctrl <= pc_left;
3589
                                          when "1000" =>
3590
                                            left_ctrl <= acca_left;
3591
                                          when "1001" =>
3592
                                            left_ctrl <= accb_left;
3593
                                          when "1010" =>
3594
                                            left_ctrl <= cc_left;
3595
                                          when "1011" =>
3596
                                            left_ctrl <= dp_left;
3597
                                          when others =>
3598
                   left_ctrl  <= md_left;
3599
                                          end case;
3600
                 right_ctrl <= zero_right;
3601
                 alu_ctrl   <= alu_tfr;
3602
                                          -- select destination register
3603
                                          case md(3 downto 0) is
3604
                                          when "0000" => -- accd
3605
                   acca_ctrl  <= load_hi_acca;
3606
                   accb_ctrl  <= load_accb;
3607
                                          when "0001" => -- ix
3608
                   ix_ctrl    <= load_ix;
3609
                                          when "0010" => -- iy
3610
                   iy_ctrl    <= load_iy;
3611
                                          when "0011" => -- up
3612
                   up_ctrl    <= load_up;
3613
                                          when "0100" => -- sp
3614
                   sp_ctrl    <= load_sp;
3615
                                          when "0101" => -- pc
3616
                   pc_ctrl    <= load_pc;
3617
                                          when "1000" => -- acca
3618
                   acca_ctrl  <= load_acca;
3619
                                          when "1001" => -- accb
3620
                   accb_ctrl  <= load_accb;
3621
                                          when "1010" => -- cc
3622
                   cc_ctrl    <= load_cc;
3623
                                          when "1011" => --dp
3624
                   dp_ctrl    <= load_dp;
3625
                                          when others =>
3626
                                            null;
3627
                                          end case;
3628
                                          --
3629
                 lic          <= '1';
3630
                                     next_state   <= fetch_state;
3631
 
3632
                                 when exg_state =>
3633
                                          -- save destination register
3634
                                          case md(3 downto 0) is
3635
                                          when "0000" =>
3636
                                            left_ctrl <= accd_left;
3637
                                          when "0001" =>
3638
                                            left_ctrl <= ix_left;
3639
                                          when "0010" =>
3640
                                            left_ctrl <= iy_left;
3641
                                          when "0011" =>
3642
                                            left_ctrl <= up_left;
3643
                                          when "0100" =>
3644
                                            left_ctrl <= sp_left;
3645
                                          when "0101" =>
3646
                                            left_ctrl <= pc_left;
3647
                                          when "1000" =>
3648
                                            left_ctrl <= acca_left;
3649
                                          when "1001" =>
3650
                                            left_ctrl <= accb_left;
3651
                                          when "1010" =>
3652
                                            left_ctrl <= cc_left;
3653
                                          when "1011" =>
3654
                                            left_ctrl <= dp_left;
3655
                                          when others =>
3656
                   left_ctrl  <= md_left;
3657
                                          end case;
3658
                 right_ctrl <= zero_right;
3659
                 alu_ctrl   <= alu_tfr;
3660
                 ea_ctrl    <= load_ea;
3661
                                          -- call tranfer microcode
3662
                                     next_state   <= exg1_state;
3663
 
3664
                                 when exg1_state =>
3665
                                          -- select source register
3666
                                          case md(7 downto 4) is
3667
                                          when "0000" =>
3668
                                            left_ctrl <= accd_left;
3669
                                          when "0001" =>
3670
                                            left_ctrl <= ix_left;
3671
                                          when "0010" =>
3672
                                            left_ctrl <= iy_left;
3673
                                          when "0011" =>
3674
                                            left_ctrl <= up_left;
3675
                                          when "0100" =>
3676
                                            left_ctrl <= sp_left;
3677
                                          when "0101" =>
3678
                                            left_ctrl <= pc_left;
3679
                                          when "1000" =>
3680
                                            left_ctrl <= acca_left;
3681
                                          when "1001" =>
3682
                                            left_ctrl <= accb_left;
3683
                                          when "1010" =>
3684
                                            left_ctrl <= cc_left;
3685
                                          when "1011" =>
3686
                                            left_ctrl <= dp_left;
3687
                                          when others =>
3688
                   left_ctrl  <= md_left;
3689
                                          end case;
3690
                 right_ctrl <= zero_right;
3691
                 alu_ctrl   <= alu_tfr;
3692
                                          -- select destination register
3693
                                          case md(3 downto 0) is
3694
                                          when "0000" => -- accd
3695
                   acca_ctrl  <= load_hi_acca;
3696
                   accb_ctrl  <= load_accb;
3697
                                          when "0001" => -- ix
3698
                   ix_ctrl    <= load_ix;
3699
                                          when "0010" => -- iy
3700
                   iy_ctrl    <= load_iy;
3701
                                          when "0011" => -- up
3702
                   up_ctrl    <= load_up;
3703
                                          when "0100" => -- sp
3704
                   sp_ctrl    <= load_sp;
3705
                                          when "0101" => -- pc
3706
                   pc_ctrl    <= load_pc;
3707
                                          when "1000" => -- acca
3708
                   acca_ctrl  <= load_acca;
3709
                                          when "1001" => -- accb
3710
                   accb_ctrl  <= load_accb;
3711
                                          when "1010" => -- cc
3712
                   cc_ctrl    <= load_cc;
3713
                                          when "1011" => --dp
3714
                   dp_ctrl    <= load_dp;
3715
                                          when others =>
3716
                                            null;
3717
                                          end case;
3718
                                     next_state   <= exg2_state;
3719
 
3720
                                 when exg2_state =>
3721
                                          -- restore destination
3722
                 left_ctrl  <= ea_left;
3723
                 right_ctrl <= zero_right;
3724
                 alu_ctrl   <= alu_tfr;
3725
                                          -- save as source register
3726
                                          case md(7 downto 4) is
3727
                                          when "0000" => -- accd
3728
                   acca_ctrl  <= load_hi_acca;
3729
                   accb_ctrl  <= load_accb;
3730
                                          when "0001" => -- ix
3731
                   ix_ctrl    <= load_ix;
3732
                                          when "0010" => -- iy
3733
                   iy_ctrl    <= load_iy;
3734
                                          when "0011" => -- up
3735
                   up_ctrl    <= load_up;
3736
                                          when "0100" => -- sp
3737
                   sp_ctrl    <= load_sp;
3738
                                          when "0101" => -- pc
3739
                   pc_ctrl    <= load_pc;
3740
                                          when "1000" => -- acca
3741
                   acca_ctrl  <= load_acca;
3742
                                          when "1001" => -- accb
3743
                   accb_ctrl  <= load_accb;
3744
                                          when "1010" => -- cc
3745
                   cc_ctrl    <= load_cc;
3746
                                          when "1011" => --dp
3747
                   dp_ctrl    <= load_dp;
3748
                                          when others =>
3749
                                            null;
3750
                                          end case;
3751
                 lic          <= '1';
3752
                                     next_state   <= fetch_state;
3753
 
3754
                                 when mulea_state =>
3755
                                          -- move accb to ea
3756
                 left_ctrl  <= accb_left;
3757
                 right_ctrl <= zero_right;
3758
                 alu_ctrl   <= alu_st16;
3759
                 ea_ctrl    <= load_ea;
3760
                                     next_state <= muld_state;
3761
 
3762
                                 when muld_state =>
3763
                                          -- clear accd
3764
                 left_ctrl  <= acca_left;
3765
                 right_ctrl <= zero_right;
3766
                 alu_ctrl   <= alu_ld8;
3767
                 acca_ctrl  <= load_hi_acca;
3768
                 accb_ctrl  <= load_accb;
3769
                                     next_state <= mul0_state;
3770
 
3771
                                 when mul0_state =>
3772
                                          -- if bit 0 of ea set, add accd to md
3773
                 left_ctrl  <= accd_left;
3774
                                          if ea(0) = '1' then
3775
                   right_ctrl <= md_right;
3776
                                          else
3777
                   right_ctrl <= zero_right;
3778
                                          end if;
3779
                 alu_ctrl   <= alu_mul;
3780
                 cc_ctrl    <= load_cc;
3781
                 acca_ctrl  <= load_hi_acca;
3782
                 accb_ctrl  <= load_accb;
3783
                 md_ctrl    <= shiftl_md;
3784
                                     next_state <= mul1_state;
3785
 
3786
                                 when mul1_state =>
3787
                                          -- if bit 1 of ea set, add accd to md
3788
                 left_ctrl  <= accd_left;
3789
                                          if ea(1) = '1' then
3790
                   right_ctrl <= md_right;
3791
                                          else
3792
                   right_ctrl <= zero_right;
3793
                                          end if;
3794
                 alu_ctrl   <= alu_mul;
3795
                 cc_ctrl    <= load_cc;
3796
                 acca_ctrl  <= load_hi_acca;
3797
                 accb_ctrl  <= load_accb;
3798
                 md_ctrl    <= shiftl_md;
3799
                                     next_state <= mul2_state;
3800
 
3801
                                 when mul2_state =>
3802
                                          -- if bit 2 of ea set, add accd to md
3803
                 left_ctrl  <= accd_left;
3804
                                          if ea(2) = '1' then
3805
                   right_ctrl <= md_right;
3806
                                          else
3807
                   right_ctrl <= zero_right;
3808
                                          end if;
3809
                 alu_ctrl   <= alu_mul;
3810
                 cc_ctrl    <= load_cc;
3811
                 acca_ctrl  <= load_hi_acca;
3812
                 accb_ctrl  <= load_accb;
3813
                 md_ctrl    <= shiftl_md;
3814
                                     next_state <= mul3_state;
3815
 
3816
                                 when mul3_state =>
3817
                                          -- if bit 3 of ea set, add accd to md
3818
                 left_ctrl  <= accd_left;
3819
                                          if ea(3) = '1' then
3820
                   right_ctrl <= md_right;
3821
                                          else
3822
                   right_ctrl <= zero_right;
3823
                                          end if;
3824
                 alu_ctrl   <= alu_mul;
3825
                 cc_ctrl    <= load_cc;
3826
                 acca_ctrl  <= load_hi_acca;
3827
                 accb_ctrl  <= load_accb;
3828
                 md_ctrl    <= shiftl_md;
3829
                                     next_state <= mul4_state;
3830
 
3831
                                 when mul4_state =>
3832
                                          -- if bit 4 of ea set, add accd to md
3833
                 left_ctrl  <= accd_left;
3834
                                          if ea(4) = '1' then
3835
                   right_ctrl <= md_right;
3836
                                          else
3837
                   right_ctrl <= zero_right;
3838
                                          end if;
3839
                 alu_ctrl   <= alu_mul;
3840
                 cc_ctrl    <= load_cc;
3841
                 acca_ctrl  <= load_hi_acca;
3842
                 accb_ctrl  <= load_accb;
3843
                 md_ctrl    <= shiftl_md;
3844
                                     next_state <= mul5_state;
3845
 
3846
                                 when mul5_state =>
3847
                                          -- if bit 5 of ea set, add accd to md
3848
                 left_ctrl  <= accd_left;
3849
                                          if ea(5) = '1' then
3850
                   right_ctrl <= md_right;
3851
                                          else
3852
                   right_ctrl <= zero_right;
3853
                                          end if;
3854
                 alu_ctrl   <= alu_mul;
3855
                 cc_ctrl    <= load_cc;
3856
                 acca_ctrl  <= load_hi_acca;
3857
                 accb_ctrl  <= load_accb;
3858
                 md_ctrl    <= shiftl_md;
3859
                                     next_state <= mul6_state;
3860
 
3861
                                 when mul6_state =>
3862
                                          -- if bit 6 of ea set, add accd to md
3863
                 left_ctrl  <= accd_left;
3864
                                          if ea(6) = '1' then
3865
                   right_ctrl <= md_right;
3866
                                          else
3867
                   right_ctrl <= zero_right;
3868
                                          end if;
3869
                 alu_ctrl   <= alu_mul;
3870
                 cc_ctrl    <= load_cc;
3871
                 acca_ctrl  <= load_hi_acca;
3872
                 accb_ctrl  <= load_accb;
3873
                 md_ctrl    <= shiftl_md;
3874
                 lic        <= '1';
3875
                                     next_state <= fetch_state;
3876
 
3877
                          --
3878
                          -- Enter here on pushs
3879
                          -- ea holds post byte
3880
                          --
3881
                          when pshs_state =>
3882
             -- decrement sp if any registers to be pushed
3883
             left_ctrl  <= sp_left;
3884
             right_ctrl <= one_right;
3885
             alu_ctrl   <= alu_sub16;
3886
                                 -- idle        address
3887
             addr_ctrl  <= idle_ad;
3888
                            dout_ctrl  <= cc_dout;
3889
                                 if ea(7 downto 0) = "00000000" then
3890
               sp_ctrl    <= latch_sp;
3891
                                 else
3892
               sp_ctrl    <= load_sp;
3893
                                 end if;
3894
                                 if ea(7) = '1' then
3895
               next_state <= pshs_pcl_state;
3896
                                 elsif ea(6) = '1' then
3897
               next_state <= pshs_upl_state;
3898
                                 elsif ea(5) = '1' then
3899
                                   next_state <= pshs_iyl_state;
3900
                                 elsif ea(4) = '1' then
3901
                                   next_state <= pshs_ixl_state;
3902
                                 elsif ea(3) = '1' then
3903
                                   next_state <= pshs_dp_state;
3904
                                 elsif ea(2) = '1' then
3905
                                   next_state <= pshs_accb_state;
3906
                                 elsif ea(1) = '1' then
3907
                                   next_state <= pshs_acca_state;
3908
                                 elsif ea(0) = '1' then
3909
                                   next_state <= pshs_cc_state;
3910
                                 else
3911
               lic        <= '1';
3912
                                   next_state <= fetch_state;
3913
                                 end if;
3914
 
3915
                          when pshs_pcl_state =>
3916
             -- decrement sp
3917
             left_ctrl  <= sp_left;
3918
             right_ctrl <= one_right;
3919
             alu_ctrl   <= alu_sub16;
3920
             sp_ctrl    <= load_sp;
3921
                                 -- write pc low
3922
             addr_ctrl  <= pushs_ad;
3923
                            dout_ctrl  <= pc_lo_dout;
3924
             next_state <= pshs_pch_state;
3925
 
3926
                          when pshs_pch_state =>
3927
             -- decrement sp
3928
             left_ctrl  <= sp_left;
3929
             right_ctrl <= one_right;
3930
             alu_ctrl   <= alu_sub16;
3931
                                 if ea(6 downto 0) = "0000000" then
3932
               sp_ctrl    <= latch_sp;
3933
                                 else
3934
               sp_ctrl    <= load_sp;
3935
                                 end if;
3936
                                 -- write pc hi
3937
             addr_ctrl  <= pushs_ad;
3938
                            dout_ctrl  <= pc_hi_dout;
3939
                                 if ea(6) = '1' then
3940
               next_state <= pshs_upl_state;
3941
                                 elsif ea(5) = '1' then
3942
                                   next_state <= pshs_iyl_state;
3943
                                 elsif ea(4) = '1' then
3944
                                   next_state <= pshs_ixl_state;
3945
                                 elsif ea(3) = '1' then
3946
                                   next_state <= pshs_dp_state;
3947
                                 elsif ea(2) = '1' then
3948
                                   next_state <= pshs_accb_state;
3949
                                 elsif ea(1) = '1' then
3950
                                   next_state <= pshs_acca_state;
3951
                                 elsif ea(0) = '1' then
3952
                                   next_state <= pshs_cc_state;
3953
                                 else
3954
               lic        <= '1';
3955
                                   next_state <= fetch_state;
3956
                                 end if;
3957
 
3958
 
3959
                          when pshs_upl_state =>
3960
             -- decrement sp
3961
             left_ctrl  <= sp_left;
3962
             right_ctrl <= one_right;
3963
             alu_ctrl   <= alu_sub16;
3964
             sp_ctrl    <= load_sp;
3965
                                 -- write pc low
3966
             addr_ctrl  <= pushs_ad;
3967
                            dout_ctrl  <= up_lo_dout;
3968
             next_state <= pshs_uph_state;
3969
 
3970
                          when pshs_uph_state =>
3971
             -- decrement sp
3972
             left_ctrl  <= sp_left;
3973
             right_ctrl <= one_right;
3974
             alu_ctrl   <= alu_sub16;
3975
                                 if ea(5 downto 0) = "000000" then
3976
               sp_ctrl    <= latch_sp;
3977
                                 else
3978
               sp_ctrl    <= load_sp;
3979
                                 end if;
3980
                                 -- write pc hi
3981
             addr_ctrl  <= pushs_ad;
3982
                            dout_ctrl  <= up_hi_dout;
3983
                                 if ea(5) = '1' then
3984
                                   next_state   <= pshs_iyl_state;
3985
                                 elsif ea(4) = '1' then
3986
                                   next_state   <= pshs_ixl_state;
3987
                                 elsif ea(3) = '1' then
3988
                                   next_state   <= pshs_dp_state;
3989
                                 elsif ea(2) = '1' then
3990
                                   next_state   <= pshs_accb_state;
3991
                                 elsif ea(1) = '1' then
3992
                                   next_state   <= pshs_acca_state;
3993
                                 elsif ea(0) = '1' then
3994
                                   next_state   <= pshs_cc_state;
3995
                                 else
3996
               lic          <= '1';
3997
                                   next_state   <= fetch_state;
3998
                                 end if;
3999
 
4000
                          when pshs_iyl_state =>
4001
             -- decrement sp
4002
             left_ctrl  <= sp_left;
4003
             right_ctrl <= one_right;
4004
             alu_ctrl   <= alu_sub16;
4005
             sp_ctrl    <= load_sp;
4006
                                 -- write iy low
4007
             addr_ctrl  <= pushs_ad;
4008
                            dout_ctrl  <= iy_lo_dout;
4009
             next_state <= pshs_iyh_state;
4010
 
4011
                          when pshs_iyh_state =>
4012
             -- decrement sp
4013
             left_ctrl  <= sp_left;
4014
             right_ctrl <= one_right;
4015
             alu_ctrl   <= alu_sub16;
4016
                                 if ea(4 downto 0) = "00000" then
4017
               sp_ctrl    <= latch_sp;
4018
                                 else
4019
               sp_ctrl    <= load_sp;
4020
                                 end if;
4021
                                 -- write iy hi
4022
             addr_ctrl  <= pushs_ad;
4023
                            dout_ctrl  <= iy_hi_dout;
4024
                                 if ea(4) = '1' then
4025
                                   next_state   <= pshs_ixl_state;
4026
                                 elsif ea(3) = '1' then
4027
                                   next_state   <= pshs_dp_state;
4028
                                 elsif ea(2) = '1' then
4029
                                   next_state   <= pshs_accb_state;
4030
                                 elsif ea(1) = '1' then
4031
                                   next_state   <= pshs_acca_state;
4032
                                 elsif ea(0) = '1' then
4033
                                   next_state   <= pshs_cc_state;
4034
                                 else
4035
               lic          <= '1';
4036
                                   next_state   <= fetch_state;
4037
                                 end if;
4038
 
4039
                          when pshs_ixl_state =>
4040
             -- decrement sp
4041
             left_ctrl  <= sp_left;
4042
             right_ctrl <= one_right;
4043
             alu_ctrl   <= alu_sub16;
4044
             sp_ctrl    <= load_sp;
4045
                                 -- write ix low
4046
             addr_ctrl  <= pushs_ad;
4047
                            dout_ctrl  <= ix_lo_dout;
4048
             next_state <= pshs_ixh_state;
4049
 
4050
                          when pshs_ixh_state =>
4051
             -- decrement sp
4052
             left_ctrl  <= sp_left;
4053
             right_ctrl <= one_right;
4054
             alu_ctrl   <= alu_sub16;
4055
                                 if ea(3 downto 0) = "0000" then
4056
               sp_ctrl    <= latch_sp;
4057
                                 else
4058
               sp_ctrl    <= load_sp;
4059
                                 end if;
4060
                                 -- write ix hi
4061
             addr_ctrl  <= pushs_ad;
4062
                            dout_ctrl  <= ix_hi_dout;
4063
                                 if ea(3) = '1' then
4064
                                   next_state   <= pshs_dp_state;
4065
                                 elsif ea(2) = '1' then
4066
                                   next_state   <= pshs_accb_state;
4067
                                 elsif ea(1) = '1' then
4068
                                   next_state   <= pshs_acca_state;
4069
                                 elsif ea(0) = '1' then
4070
                                   next_state   <= pshs_cc_state;
4071
                                 else
4072
               lic          <= '1';
4073
                                   next_state   <= fetch_state;
4074
                                 end if;
4075
 
4076
                          when pshs_dp_state =>
4077
             -- decrement sp
4078
             left_ctrl  <= sp_left;
4079
             right_ctrl <= one_right;
4080
             alu_ctrl   <= alu_sub16;
4081
                                 if ea(2 downto 0) = "000" then
4082
               sp_ctrl    <= latch_sp;
4083
                                 else
4084
               sp_ctrl    <= load_sp;
4085
                                 end if;
4086
                                 -- write dp
4087
             addr_ctrl  <= pushs_ad;
4088
                            dout_ctrl  <= dp_dout;
4089
                                 if ea(2) = '1' then
4090
                                   next_state   <= pshs_accb_state;
4091
                                 elsif ea(1) = '1' then
4092
                                   next_state   <= pshs_acca_state;
4093
                                 elsif ea(0) = '1' then
4094
                                   next_state   <= pshs_cc_state;
4095
                                 else
4096
               lic          <= '1';
4097
                                   next_state   <= fetch_state;
4098
                                 end if;
4099
 
4100
                          when pshs_accb_state =>
4101
             -- decrement sp
4102
             left_ctrl  <= sp_left;
4103
             right_ctrl <= one_right;
4104
             alu_ctrl   <= alu_sub16;
4105
                                 if ea(1 downto 0) = "00" then
4106
               sp_ctrl    <= latch_sp;
4107
                                 else
4108
               sp_ctrl    <= load_sp;
4109
                                 end if;
4110
                                 -- write accb
4111
             addr_ctrl  <= pushs_ad;
4112
                            dout_ctrl  <= accb_dout;
4113
                                 if ea(1) = '1' then
4114
                                   next_state   <= pshs_acca_state;
4115
                                 elsif ea(0) = '1' then
4116
                                   next_state   <= pshs_cc_state;
4117
                                 else
4118
               lic          <= '1';
4119
                                   next_state   <= fetch_state;
4120
                                 end if;
4121
 
4122
                          when pshs_acca_state =>
4123
             -- decrement sp
4124
             left_ctrl  <= sp_left;
4125
             right_ctrl <= one_right;
4126
             alu_ctrl   <= alu_sub16;
4127
                                 if ea(0) = '1' then
4128
               sp_ctrl    <= load_sp;
4129
                                 else
4130
               sp_ctrl    <= latch_sp;
4131
                                 end if;
4132
                                 -- write acca
4133
             addr_ctrl  <= pushs_ad;
4134
                            dout_ctrl  <= acca_dout;
4135
                                 if ea(0) = '1' then
4136
                                   next_state   <= pshs_cc_state;
4137
                                 else
4138
               lic          <= '1';
4139
                                   next_state   <= fetch_state;
4140
                                 end if;
4141
 
4142
                          when pshs_cc_state =>
4143
             -- idle sp
4144
                                 -- write cc
4145
             addr_ctrl  <= pushs_ad;
4146
                            dout_ctrl  <= cc_dout;
4147
             lic          <= '1';
4148
             next_state <= fetch_state;
4149
 
4150
                          --
4151
                          -- enter here on PULS
4152
                          -- ea hold register mask
4153
                          --
4154
                          when puls_state =>
4155
                                 if ea(0) = '1' then
4156
                                   next_state <= puls_cc_state;
4157
                                 elsif ea(1) = '1' then
4158
                                   next_state <= puls_acca_state;
4159
                                 elsif ea(2) = '1' then
4160
                                   next_state <= puls_accb_state;
4161
                                 elsif ea(3) = '1' then
4162
                                   next_state <= puls_dp_state;
4163
                                 elsif ea(4) = '1' then
4164
                                   next_state <= puls_ixh_state;
4165
                                 elsif ea(5) = '1' then
4166
                                   next_state <= puls_iyh_state;
4167
                                 elsif ea(6) = '1' then
4168
               next_state <= puls_uph_state;
4169
                                 elsif ea(7) = '1' then
4170
               next_state <= puls_pch_state;
4171
                                 else
4172
               lic        <= '1';
4173
                                   next_state <= fetch_state;
4174
                                 end if;
4175
 
4176
                          when puls_cc_state =>
4177
                                 -- increment sp
4178
             left_ctrl  <= sp_left;
4179
             right_ctrl <= one_right;
4180
             alu_ctrl   <= alu_add16;
4181
             sp_ctrl    <= load_sp;
4182
                                 -- read cc
4183
             cc_ctrl    <= pull_cc;
4184
             addr_ctrl  <= pulls_ad;
4185
                                 if ea(1) = '1' then
4186
                                   next_state <= puls_acca_state;
4187
                                 elsif ea(2) = '1' then
4188
                                   next_state <= puls_accb_state;
4189
                                 elsif ea(3) = '1' then
4190
                                   next_state <= puls_dp_state;
4191
                                 elsif ea(4) = '1' then
4192
                                   next_state <= puls_ixh_state;
4193
                                 elsif ea(5) = '1' then
4194
                                   next_state <= puls_iyh_state;
4195
                                 elsif ea(6) = '1' then
4196
               next_state <= puls_uph_state;
4197
                                 elsif ea(7) = '1' then
4198
               next_state <= puls_pch_state;
4199
                                 else
4200
               lic        <= '1';
4201
                                   next_state <= fetch_state;
4202
                                 end if;
4203
 
4204
                          when puls_acca_state =>
4205
                                 -- increment sp
4206
             left_ctrl  <= sp_left;
4207
             right_ctrl <= one_right;
4208
             alu_ctrl   <= alu_add16;
4209
             sp_ctrl    <= load_sp;
4210
                                 -- read acca
4211
                                 acca_ctrl  <= pull_acca;
4212
             addr_ctrl  <= pulls_ad;
4213
                                 if ea(2) = '1' then
4214
                                   next_state <= puls_accb_state;
4215
                                 elsif ea(3) = '1' then
4216
                                   next_state <= puls_dp_state;
4217
                                 elsif ea(4) = '1' then
4218
                                   next_state <= puls_ixh_state;
4219
                                 elsif ea(5) = '1' then
4220
                                   next_state <= puls_iyh_state;
4221
                                 elsif ea(6) = '1' then
4222
               next_state <= puls_uph_state;
4223
                                 elsif ea(7) = '1' then
4224
               next_state <= puls_pch_state;
4225
                                 else
4226
               lic          <= '1';
4227
                                   next_state <= fetch_state;
4228
                                 end if;
4229
 
4230
                          when puls_accb_state =>
4231
                                 -- increment sp
4232
             left_ctrl  <= sp_left;
4233
             right_ctrl <= one_right;
4234
             alu_ctrl   <= alu_add16;
4235
             sp_ctrl    <= load_sp;
4236
                                 -- read accb
4237
                                 accb_ctrl  <= pull_accb;
4238
             addr_ctrl  <= pulls_ad;
4239
                                 if ea(3) = '1' then
4240
                                   next_state <= puls_dp_state;
4241
                                 elsif ea(4) = '1' then
4242
                                   next_state <= puls_ixh_state;
4243
                                 elsif ea(5) = '1' then
4244
                                   next_state <= puls_iyh_state;
4245
                                 elsif ea(6) = '1' then
4246
               next_state <= puls_uph_state;
4247
                                 elsif ea(7) = '1' then
4248
               next_state <= puls_pch_state;
4249
                                 else
4250
               lic        <= '1';
4251
                                   next_state <= fetch_state;
4252
                                 end if;
4253
 
4254
                          when puls_dp_state =>
4255
                                 -- increment sp
4256
             left_ctrl  <= sp_left;
4257
             right_ctrl <= one_right;
4258
             alu_ctrl   <= alu_add16;
4259
             sp_ctrl    <= load_sp;
4260
                                 -- read dp
4261
                                 dp_ctrl    <= pull_dp;
4262
             addr_ctrl  <= pulls_ad;
4263
                                 if ea(4) = '1' then
4264
                                   next_state <= puls_ixh_state;
4265
                                 elsif ea(5) = '1' then
4266
                                   next_state <= puls_iyh_state;
4267
                                 elsif ea(6) = '1' then
4268
               next_state <= puls_uph_state;
4269
                                 elsif ea(7) = '1' then
4270
               next_state <= puls_pch_state;
4271
                                 else
4272
               lic        <= '1';
4273
                                   next_state <= fetch_state;
4274
                                 end if;
4275
 
4276
                          when puls_ixh_state =>
4277
             -- increment sp
4278
             left_ctrl  <= sp_left;
4279
             right_ctrl <= one_right;
4280
             alu_ctrl   <= alu_add16;
4281
             sp_ctrl    <= load_sp;
4282
                                 -- pull ix hi
4283
                                 ix_ctrl    <= pull_hi_ix;
4284
             addr_ctrl  <= pulls_ad;
4285
             next_state <= puls_ixl_state;
4286
 
4287
                          when puls_ixl_state =>
4288
                                 -- increment sp
4289
             left_ctrl  <= sp_left;
4290
             right_ctrl <= one_right;
4291
             alu_ctrl   <= alu_add16;
4292
             sp_ctrl    <= load_sp;
4293
                                 -- read ix low
4294
                                 ix_ctrl    <= pull_lo_ix;
4295
             addr_ctrl  <= pulls_ad;
4296
                                 if ea(5) = '1' then
4297
                                   next_state <= puls_iyh_state;
4298
                                 elsif ea(6) = '1' then
4299
               next_state <= puls_uph_state;
4300
                                 elsif ea(7) = '1' then
4301
               next_state <= puls_pch_state;
4302
                                 else
4303
               lic        <= '1';
4304
                                   next_state <= fetch_state;
4305
                                 end if;
4306
 
4307
                          when puls_iyh_state =>
4308
             -- increment sp
4309
             left_ctrl  <= sp_left;
4310
             right_ctrl <= one_right;
4311
             alu_ctrl   <= alu_add16;
4312
             sp_ctrl    <= load_sp;
4313
                                 -- pull iy hi
4314
                                 iy_ctrl    <= pull_hi_iy;
4315
             addr_ctrl  <= pulls_ad;
4316
             next_state   <= puls_iyl_state;
4317
 
4318
                          when puls_iyl_state =>
4319
             -- increment sp
4320
             left_ctrl  <= sp_left;
4321
             right_ctrl <= one_right;
4322
             alu_ctrl   <= alu_add16;
4323
             sp_ctrl    <= load_sp;
4324
                                 -- read iy low
4325
                                 iy_ctrl    <= pull_lo_iy;
4326
             addr_ctrl  <= pulls_ad;
4327
                                 if ea(6) = '1' then
4328
               next_state <= puls_uph_state;
4329
                                 elsif ea(7) = '1' then
4330
               next_state <= puls_pch_state;
4331
                                 else
4332
               lic        <= '1';
4333
                                   next_state <= fetch_state;
4334
                                 end if;
4335
 
4336
                          when puls_uph_state =>
4337
             -- increment sp
4338
             left_ctrl  <= sp_left;
4339
             right_ctrl <= one_right;
4340
             alu_ctrl   <= alu_add16;
4341
             sp_ctrl    <= load_sp;
4342
                                 -- pull up hi
4343
                                 up_ctrl    <= pull_hi_up;
4344
             addr_ctrl  <= pulls_ad;
4345
             next_state <= puls_upl_state;
4346
 
4347
                          when puls_upl_state =>
4348
                                 -- increment sp
4349
             left_ctrl  <= sp_left;
4350
             right_ctrl <= one_right;
4351
             alu_ctrl   <= alu_add16;
4352
             sp_ctrl    <= load_sp;
4353
                                 -- read up low
4354
                                 up_ctrl    <= pull_lo_up;
4355
             addr_ctrl  <= pulls_ad;
4356
                                 if ea(7) = '1' then
4357
               next_state <= puls_pch_state;
4358
                                 else
4359
               lic        <= '1';
4360
                                   next_state <= fetch_state;
4361
                                 end if;
4362
 
4363
                          when puls_pch_state =>
4364
             -- increment sp
4365
             left_ctrl  <= sp_left;
4366
             right_ctrl <= one_right;
4367
             alu_ctrl   <= alu_add16;
4368
             sp_ctrl    <= load_sp;
4369
                                 -- pull pc hi
4370
                                 pc_ctrl    <= pull_hi_pc;
4371
             addr_ctrl  <= pulls_ad;
4372
             next_state <= puls_pcl_state;
4373
 
4374
                          when puls_pcl_state =>
4375
                                 -- increment sp
4376
             left_ctrl  <= sp_left;
4377
             right_ctrl <= one_right;
4378
             alu_ctrl   <= alu_add16;
4379
             sp_ctrl    <= load_sp;
4380
                                 -- read pc low
4381
                                 pc_ctrl    <= pull_lo_pc;
4382
             addr_ctrl  <= pulls_ad;
4383
             lic        <= '1';
4384
             next_state <= fetch_state;
4385
 
4386
                          --
4387
                          -- Enter here on pshu
4388
                          -- ea holds post byte
4389
                          --
4390
                          when pshu_state =>
4391
             -- decrement up if any registers to be pushed
4392
             left_ctrl  <= up_left;
4393
             right_ctrl <= one_right;
4394
             alu_ctrl   <= alu_sub16;
4395
                                 if ea(7 downto 0) = "00000000" then
4396
               up_ctrl    <= latch_up;
4397
                                 else
4398
               up_ctrl    <= load_up;
4399
                                 end if;
4400
                                 -- write idle bus
4401
                                 if ea(7) = '1' then
4402
               next_state   <= pshu_pcl_state;
4403
                                 elsif ea(6) = '1' then
4404
               next_state   <= pshu_spl_state;
4405
                                 elsif ea(5) = '1' then
4406
                                   next_state   <= pshu_iyl_state;
4407
                                 elsif ea(4) = '1' then
4408
                                   next_state   <= pshu_ixl_state;
4409
                                 elsif ea(3) = '1' then
4410
                                   next_state   <= pshu_dp_state;
4411
                                 elsif ea(2) = '1' then
4412
                                   next_state   <= pshu_accb_state;
4413
                                 elsif ea(1) = '1' then
4414
                                   next_state   <= pshu_acca_state;
4415
                                 elsif ea(0) = '1' then
4416
                                   next_state   <= pshu_cc_state;
4417
                                 else
4418
               lic          <= '1';
4419
                                   next_state   <= fetch_state;
4420
                                 end if;
4421
                          --
4422
                          -- push PC onto U stack
4423
                          --
4424
                          when pshu_pcl_state =>
4425
             -- decrement up
4426
             left_ctrl  <= up_left;
4427
             right_ctrl <= one_right;
4428
             alu_ctrl   <= alu_sub16;
4429
             up_ctrl    <= load_up;
4430
                                 -- write pc low
4431
             addr_ctrl  <= pushu_ad;
4432
                            dout_ctrl  <= pc_lo_dout;
4433
             next_state <= pshu_pch_state;
4434
 
4435
                          when pshu_pch_state =>
4436
             -- decrement up
4437
             left_ctrl  <= up_left;
4438
             right_ctrl <= one_right;
4439
             alu_ctrl   <= alu_sub16;
4440
                                 if ea(6 downto 0) = "0000000" then
4441
               up_ctrl    <= latch_up;
4442
                                 else
4443
               up_ctrl    <= load_up;
4444
                                 end if;
4445
                                 -- write pc hi
4446
             addr_ctrl  <= pushu_ad;
4447
                            dout_ctrl  <= pc_hi_dout;
4448
                                 if ea(6) = '1' then
4449
               next_state   <= pshu_spl_state;
4450
                                 elsif ea(5) = '1' then
4451
                                   next_state   <= pshu_iyl_state;
4452
                                 elsif ea(4) = '1' then
4453
                                   next_state   <= pshu_ixl_state;
4454
                                 elsif ea(3) = '1' then
4455
                                   next_state   <= pshu_dp_state;
4456
                                 elsif ea(2) = '1' then
4457
                                   next_state   <= pshu_accb_state;
4458
                                 elsif ea(1) = '1' then
4459
                                   next_state   <= pshu_acca_state;
4460
                                 elsif ea(0) = '1' then
4461
                                   next_state   <= pshu_cc_state;
4462
                                 else
4463
               lic          <= '1';
4464
                                   next_state   <= fetch_state;
4465
                                 end if;
4466
 
4467
                          when pshu_spl_state =>
4468
             -- decrement up
4469
             left_ctrl  <= up_left;
4470
             right_ctrl <= one_right;
4471
             alu_ctrl   <= alu_sub16;
4472
             up_ctrl    <= load_up;
4473
                                 -- write sp low
4474
             addr_ctrl  <= pushu_ad;
4475
                            dout_ctrl  <= sp_lo_dout;
4476
             next_state <= pshu_sph_state;
4477
 
4478
                          when pshu_sph_state =>
4479
             -- decrement up
4480
             left_ctrl  <= up_left;
4481
             right_ctrl <= one_right;
4482
             alu_ctrl   <= alu_sub16;
4483
                                 if ea(5 downto 0) = "000000" then
4484
               up_ctrl    <= latch_up;
4485
                                 else
4486
               up_ctrl    <= load_up;
4487
                                 end if;
4488
                                 -- write sp hi
4489
             addr_ctrl  <= pushu_ad;
4490
                            dout_ctrl  <= sp_hi_dout;
4491
                                 if ea(5) = '1' then
4492
                                   next_state   <= pshu_iyl_state;
4493
                                 elsif ea(4) = '1' then
4494
                                   next_state   <= pshu_ixl_state;
4495
                                 elsif ea(3) = '1' then
4496
                                   next_state   <= pshu_dp_state;
4497
                                 elsif ea(2) = '1' then
4498
                                   next_state   <= pshu_accb_state;
4499
                                 elsif ea(1) = '1' then
4500
                                   next_state   <= pshu_acca_state;
4501
                                 elsif ea(0) = '1' then
4502
                                   next_state   <= pshu_cc_state;
4503
                                 else
4504
               lic          <= '1';
4505
                                   next_state   <= fetch_state;
4506
                                 end if;
4507
 
4508
                          when pshu_iyl_state =>
4509
             -- decrement up
4510
             left_ctrl  <= up_left;
4511
             right_ctrl <= one_right;
4512
             alu_ctrl   <= alu_sub16;
4513
             up_ctrl    <= load_up;
4514
                                 -- write iy low
4515
             addr_ctrl  <= pushu_ad;
4516
                            dout_ctrl  <= iy_lo_dout;
4517
             next_state <= pshu_iyh_state;
4518
 
4519
                          when pshu_iyh_state =>
4520
             -- decrement up
4521
             left_ctrl  <= up_left;
4522
             right_ctrl <= one_right;
4523
             alu_ctrl   <= alu_sub16;
4524
                                 if ea(4 downto 0) = "00000" then
4525
               up_ctrl    <= latch_up;
4526
                                 else
4527
               up_ctrl    <= load_up;
4528
                                 end if;
4529
                                 -- write iy hi
4530
             addr_ctrl  <= pushu_ad;
4531
                            dout_ctrl  <= iy_hi_dout;
4532
                                 if ea(4) = '1' then
4533
                                   next_state   <= pshu_ixl_state;
4534
                                 elsif ea(3) = '1' then
4535
                                   next_state   <= pshu_dp_state;
4536
                                 elsif ea(2) = '1' then
4537
                                   next_state   <= pshu_accb_state;
4538
                                 elsif ea(1) = '1' then
4539
                                   next_state   <= pshu_acca_state;
4540
                                 elsif ea(0) = '1' then
4541
                                   next_state   <= pshu_cc_state;
4542
                                 else
4543
               lic          <= '1';
4544
                                   next_state   <= fetch_state;
4545
                                 end if;
4546
 
4547
                          when pshu_ixl_state =>
4548
             -- decrement up
4549
             left_ctrl  <= up_left;
4550
             right_ctrl <= one_right;
4551
             alu_ctrl   <= alu_sub16;
4552
             up_ctrl    <= load_up;
4553
                                 -- write ix low
4554
             addr_ctrl  <= pushu_ad;
4555
                            dout_ctrl  <= ix_lo_dout;
4556
             next_state <= pshu_ixh_state;
4557
 
4558
                          when pshu_ixh_state =>
4559
             -- decrement up
4560
             left_ctrl  <= up_left;
4561
             right_ctrl <= one_right;
4562
             alu_ctrl   <= alu_sub16;
4563
                                 if ea(3 downto 0) = "0000" then
4564
               up_ctrl    <= latch_up;
4565
                                 else
4566
               up_ctrl    <= load_up;
4567
                                 end if;
4568
                                 -- write ix hi
4569
             addr_ctrl  <= pushu_ad;
4570
                            dout_ctrl  <= ix_hi_dout;
4571
                                 if ea(3) = '1' then
4572
                                   next_state   <= pshu_dp_state;
4573
                                 elsif ea(2) = '1' then
4574
                                   next_state   <= pshu_accb_state;
4575
                                 elsif ea(1) = '1' then
4576
                                   next_state   <= pshu_acca_state;
4577
                                 elsif ea(0) = '1' then
4578
                                   next_state   <= pshu_cc_state;
4579
                                 else
4580
               lic          <= '1';
4581
                                   next_state   <= fetch_state;
4582
                                 end if;
4583
 
4584
                          when pshu_dp_state =>
4585
             -- decrement up
4586
             left_ctrl  <= up_left;
4587
             right_ctrl <= one_right;
4588
             alu_ctrl   <= alu_sub16;
4589
                                 if ea(2 downto 0) = "000" then
4590
               up_ctrl    <= latch_up;
4591
                                 else
4592
               up_ctrl    <= load_up;
4593
                                 end if;
4594
                                 -- write dp
4595
             addr_ctrl  <= pushu_ad;
4596
                            dout_ctrl  <= dp_dout;
4597
                                 if ea(2) = '1' then
4598
                                   next_state   <= pshu_accb_state;
4599
                                 elsif ea(1) = '1' then
4600
                                   next_state   <= pshu_acca_state;
4601
                                 elsif ea(0) = '1' then
4602
                                   next_state   <= pshu_cc_state;
4603
                                 else
4604
               lic          <= '1';
4605
                                   next_state   <= fetch_state;
4606
                                 end if;
4607
 
4608
                          when pshu_accb_state =>
4609
             -- decrement up
4610
             left_ctrl  <= up_left;
4611
             right_ctrl <= one_right;
4612
             alu_ctrl   <= alu_sub16;
4613
                                 if ea(1 downto 0) = "00" then
4614
               up_ctrl    <= latch_up;
4615
                                 else
4616
               up_ctrl    <= load_up;
4617
                                 end if;
4618
                                 -- write accb
4619
             addr_ctrl  <= pushu_ad;
4620
                            dout_ctrl  <= accb_dout;
4621
                                 if ea(1) = '1' then
4622
                                   next_state   <= pshu_acca_state;
4623
                                 elsif ea(0) = '1' then
4624
                                   next_state   <= pshu_cc_state;
4625
                                 else
4626
               lic          <= '1';
4627
                                   next_state   <= fetch_state;
4628
                                 end if;
4629
 
4630
                          when pshu_acca_state =>
4631
             -- decrement up
4632
             left_ctrl  <= up_left;
4633
             right_ctrl <= one_right;
4634
             alu_ctrl   <= alu_sub16;
4635
                                 if ea(0) = '0' then
4636
               up_ctrl    <= latch_up;
4637
                                 else
4638
               up_ctrl    <= load_up;
4639
                                 end if;
4640
                                 -- write acca
4641
             addr_ctrl  <= pushu_ad;
4642
                            dout_ctrl  <= acca_dout;
4643
                                 if ea(0) = '1' then
4644
                                   next_state   <= pshu_cc_state;
4645
                                 else
4646
               lic          <= '1';
4647
                                   next_state   <= fetch_state;
4648
                                 end if;
4649
 
4650
                          when pshu_cc_state =>
4651
             -- idle up
4652
                                 -- write cc
4653
             addr_ctrl  <= pushu_ad;
4654
                            dout_ctrl  <= cc_dout;
4655
             lic        <= '1';
4656
             next_state <= fetch_state;
4657
 
4658
                          --
4659
                          -- enter here on PULU
4660
                          -- ea hold register mask
4661
                          --
4662
                          when pulu_state =>
4663
                                 -- idle UP
4664
                                 -- idle bus
4665
                                 if ea(0) = '1' then
4666
                                   next_state <= pulu_cc_state;
4667
                                 elsif ea(1) = '1' then
4668
                                   next_state <= pulu_acca_state;
4669
                                 elsif ea(2) = '1' then
4670
                                   next_state <= pulu_accb_state;
4671
                                 elsif ea(3) = '1' then
4672
                                   next_state <= pulu_dp_state;
4673
                                 elsif ea(4) = '1' then
4674
                                   next_state <= pulu_ixh_state;
4675
                                 elsif ea(5) = '1' then
4676
                                   next_state <= pulu_iyh_state;
4677
                                 elsif ea(6) = '1' then
4678
               next_state <= pulu_sph_state;
4679
                                 elsif ea(7) = '1' then
4680
               next_state <= pulu_pch_state;
4681
                                 else
4682
               lic        <= '1';
4683
                                   next_state <= fetch_state;
4684
                                 end if;
4685
 
4686
                          when pulu_cc_state =>
4687
                                 -- increment up
4688
             left_ctrl  <= up_left;
4689
             right_ctrl <= one_right;
4690
             alu_ctrl   <= alu_add16;
4691
             up_ctrl    <= load_up;
4692
                                 -- read cc
4693
             cc_ctrl    <= pull_cc;
4694
             addr_ctrl  <= pullu_ad;
4695
                                 if ea(1) = '1' then
4696
                                   next_state <= pulu_acca_state;
4697
                                 elsif ea(2) = '1' then
4698
                                   next_state <= pulu_accb_state;
4699
                                 elsif ea(3) = '1' then
4700
                                   next_state <= pulu_dp_state;
4701
                                 elsif ea(4) = '1' then
4702
                                   next_state <= pulu_ixh_state;
4703
                                 elsif ea(5) = '1' then
4704
                                   next_state <= pulu_iyh_state;
4705
                                 elsif ea(6) = '1' then
4706
               next_state <= pulu_sph_state;
4707
                                 elsif ea(7) = '1' then
4708
               next_state <= pulu_pch_state;
4709
                                 else
4710
               lic        <= '1';
4711
                                   next_state <= fetch_state;
4712
                                 end if;
4713
 
4714
                          when pulu_acca_state =>
4715
                                 -- increment up
4716
             left_ctrl  <= up_left;
4717
             right_ctrl <= one_right;
4718
             alu_ctrl   <= alu_add16;
4719
             up_ctrl    <= load_up;
4720
                                 -- read acca
4721
                                 acca_ctrl  <= pull_acca;
4722
             addr_ctrl  <= pullu_ad;
4723
                                 if ea(2) = '1' then
4724
                                   next_state <= pulu_accb_state;
4725
                                 elsif ea(3) = '1' then
4726
                                   next_state <= pulu_dp_state;
4727
                                 elsif ea(4) = '1' then
4728
                                   next_state <= pulu_ixh_state;
4729
                                 elsif ea(5) = '1' then
4730
                                   next_state <= pulu_iyh_state;
4731
                                 elsif ea(6) = '1' then
4732
               next_state <= pulu_sph_state;
4733
                                 elsif ea(7) = '1' then
4734
               next_state <= pulu_pch_state;
4735
                                 else
4736
               lic        <= '1';
4737
                                   next_state <= fetch_state;
4738
                                 end if;
4739
 
4740
                          when pulu_accb_state =>
4741
                                 -- increment up
4742
             left_ctrl  <= up_left;
4743
             right_ctrl <= one_right;
4744
             alu_ctrl   <= alu_add16;
4745
             up_ctrl    <= load_up;
4746
                                 -- read accb
4747
                                 accb_ctrl  <= pull_accb;
4748
             addr_ctrl  <= pullu_ad;
4749
                                 if ea(3) = '1' then
4750
                                   next_state <= pulu_dp_state;
4751
                                 elsif ea(4) = '1' then
4752
                                   next_state <= pulu_ixh_state;
4753
                                 elsif ea(5) = '1' then
4754
                                   next_state <= pulu_iyh_state;
4755
                                 elsif ea(6) = '1' then
4756
               next_state <= pulu_sph_state;
4757
                                 elsif ea(7) = '1' then
4758
               next_state <= pulu_pch_state;
4759
                                 else
4760
               lic        <= '1';
4761
                                   next_state <= fetch_state;
4762
                                 end if;
4763
 
4764
                          when pulu_dp_state =>
4765
                                 -- increment up
4766
             left_ctrl  <= up_left;
4767
             right_ctrl <= one_right;
4768
             alu_ctrl   <= alu_add16;
4769
             up_ctrl    <= load_up;
4770
                                 -- read dp
4771
                                 dp_ctrl    <= pull_dp;
4772
             addr_ctrl  <= pullu_ad;
4773
                                 if ea(4) = '1' then
4774
                                   next_state <= pulu_ixh_state;
4775
                                 elsif ea(5) = '1' then
4776
                                   next_state <= pulu_iyh_state;
4777
                                 elsif ea(6) = '1' then
4778
               next_state <= pulu_sph_state;
4779
                                 elsif ea(7) = '1' then
4780
               next_state <= pulu_pch_state;
4781
                                 else
4782
               lic        <= '1';
4783
                                   next_state <= fetch_state;
4784
                                 end if;
4785
 
4786
                          when pulu_ixh_state =>
4787
             -- increment up
4788
             left_ctrl  <= up_left;
4789
             right_ctrl <= one_right;
4790
             alu_ctrl   <= alu_add16;
4791
             up_ctrl    <= load_up;
4792
                                 -- read ix hi
4793
                                 ix_ctrl    <= pull_hi_ix;
4794
             addr_ctrl  <= pullu_ad;
4795
             next_state <= pulu_ixl_state;
4796
 
4797
                          when pulu_ixl_state =>
4798
                                 -- increment up
4799
             left_ctrl  <= up_left;
4800
             right_ctrl <= one_right;
4801
             alu_ctrl   <= alu_add16;
4802
             up_ctrl    <= load_up;
4803
                                 -- read ix low
4804
                                 ix_ctrl    <= pull_lo_ix;
4805
             addr_ctrl  <= pullu_ad;
4806
                                 if ea(5) = '1' then
4807
                                   next_state <= pulu_iyh_state;
4808
                                 elsif ea(6) = '1' then
4809
               next_state <= pulu_sph_state;
4810
                                 elsif ea(7) = '1' then
4811
               next_state <= pulu_pch_state;
4812
                                 else
4813
               lic        <= '1';
4814
                                   next_state <= fetch_state;
4815
                                 end if;
4816
 
4817
                          when pulu_iyh_state =>
4818
             -- increment up
4819
             left_ctrl  <= up_left;
4820
             right_ctrl <= one_right;
4821
             alu_ctrl   <= alu_add16;
4822
             up_ctrl    <= load_up;
4823
                                 -- read iy hi
4824
                                 iy_ctrl    <= pull_hi_iy;
4825
             addr_ctrl  <= pullu_ad;
4826
             next_state <= pulu_iyl_state;
4827
 
4828
                          when pulu_iyl_state =>
4829
             -- increment up
4830
             left_ctrl  <= up_left;
4831
             right_ctrl <= one_right;
4832
             alu_ctrl   <= alu_add16;
4833
             up_ctrl    <= load_up;
4834
                                 -- read iy low
4835
                                 iy_ctrl    <= pull_lo_iy;
4836
             addr_ctrl  <= pullu_ad;
4837
                                 if ea(6) = '1' then
4838
               next_state <= pulu_sph_state;
4839
                                 elsif ea(7) = '1' then
4840
               next_state <= pulu_pch_state;
4841
                                 else
4842
               lic        <= '1';
4843
                                   next_state <= fetch_state;
4844
                                 end if;
4845
 
4846
                          when pulu_sph_state =>
4847
             -- increment up
4848
             left_ctrl  <= up_left;
4849
             right_ctrl <= one_right;
4850
             alu_ctrl   <= alu_add16;
4851
             up_ctrl    <= load_up;
4852
                                 -- read sp hi
4853
                                 sp_ctrl    <= pull_hi_sp;
4854
             addr_ctrl  <= pullu_ad;
4855
             next_state <= pulu_spl_state;
4856
 
4857
                          when pulu_spl_state =>
4858
                                 -- increment up
4859
             left_ctrl  <= up_left;
4860
             right_ctrl <= one_right;
4861
             alu_ctrl   <= alu_add16;
4862
             up_ctrl    <= load_up;
4863
                                 -- read sp low
4864
                                 sp_ctrl    <= pull_lo_sp;
4865
             addr_ctrl  <= pullu_ad;
4866
                                 if ea(7) = '1' then
4867
               next_state <= pulu_pch_state;
4868
                                 else
4869
               lic        <= '1';
4870
                                   next_state <= fetch_state;
4871
                                 end if;
4872
 
4873
                          when pulu_pch_state =>
4874
             -- increment up
4875
             left_ctrl  <= up_left;
4876
             right_ctrl <= one_right;
4877
             alu_ctrl   <= alu_add16;
4878
             up_ctrl    <= load_up;
4879
                                 -- pull pc hi
4880
                                 pc_ctrl    <= pull_hi_pc;
4881
             addr_ctrl  <= pullu_ad;
4882
             next_state <= pulu_pcl_state;
4883
 
4884
                          when pulu_pcl_state =>
4885
                                 -- increment up
4886
             left_ctrl  <= up_left;
4887
             right_ctrl <= one_right;
4888
             alu_ctrl   <= alu_add16;
4889
             up_ctrl    <= load_up;
4890
                                 -- read pc low
4891
                                 pc_ctrl    <= pull_lo_pc;
4892
             addr_ctrl  <= pullu_ad;
4893
             lic        <= '1';
4894
             next_state <= fetch_state;
4895
 
4896
                          --
4897
                          -- pop the Condition codes
4898
                          --
4899
                          when rti_cc_state =>
4900
                                 -- increment sp
4901
             left_ctrl  <= sp_left;
4902
             right_ctrl <= one_right;
4903
             alu_ctrl   <= alu_add16;
4904
             sp_ctrl    <= load_sp;
4905
                                 -- read cc
4906
             cc_ctrl    <= pull_cc;
4907
             addr_ctrl  <= pulls_ad;
4908
             next_state <= rti_entire_state;
4909
 
4910
                          --
4911
                          -- Added RTI cycle 11th July 2006 John Kent.
4912
                          -- test the "Entire" Flag
4913
                          -- that has just been popped off the stack
4914
                          --
4915
                          when rti_entire_state =>
4916
                                 --
4917
                                 -- The Entire flag must be recovered from the stack
4918
                                 -- before testing.
4919
                                 --
4920
                                 if cc(EBIT) = '1' then
4921
               next_state   <= rti_acca_state;
4922
                                 else
4923
               next_state   <= rti_pch_state;
4924
                                 end if;
4925
 
4926
                          when rti_acca_state =>
4927
                                 -- increment sp
4928
             left_ctrl  <= sp_left;
4929
             right_ctrl <= one_right;
4930
             alu_ctrl   <= alu_add16;
4931
             sp_ctrl    <= load_sp;
4932
                                 -- read acca
4933
                                 acca_ctrl  <= pull_acca;
4934
             addr_ctrl  <= pulls_ad;
4935
             next_state <= rti_accb_state;
4936
 
4937
                          when rti_accb_state =>
4938
                                 -- increment sp
4939
             left_ctrl  <= sp_left;
4940
             right_ctrl <= one_right;
4941
             alu_ctrl   <= alu_add16;
4942
             sp_ctrl    <= load_sp;
4943
                                 -- read accb
4944
                                 accb_ctrl  <= pull_accb;
4945
             addr_ctrl  <= pulls_ad;
4946
             next_state <= rti_dp_state;
4947
 
4948
                          when rti_dp_state =>
4949
                                 -- increment sp
4950
             left_ctrl  <= sp_left;
4951
             right_ctrl <= one_right;
4952
             alu_ctrl   <= alu_add16;
4953
             sp_ctrl    <= load_sp;
4954
                                 -- read dp
4955
                                 dp_ctrl    <= pull_dp;
4956
             addr_ctrl  <= pulls_ad;
4957
             next_state <= rti_ixh_state;
4958
 
4959
                          when rti_ixh_state =>
4960
                                 -- increment sp
4961
             left_ctrl  <= sp_left;
4962
             right_ctrl <= one_right;
4963
             alu_ctrl   <= alu_add16;
4964
             sp_ctrl    <= load_sp;
4965
                                 -- read ix hi
4966
                                 ix_ctrl    <= pull_hi_ix;
4967
             addr_ctrl  <= pulls_ad;
4968
             next_state <= rti_ixl_state;
4969
 
4970
                          when rti_ixl_state =>
4971
                                 -- increment sp
4972
             left_ctrl  <= sp_left;
4973
             right_ctrl <= one_right;
4974
             alu_ctrl   <= alu_add16;
4975
             sp_ctrl    <= load_sp;
4976
                                 -- read ix low
4977
                                 ix_ctrl    <= pull_lo_ix;
4978
             addr_ctrl  <= pulls_ad;
4979
             next_state <= rti_iyh_state;
4980
 
4981
                          when rti_iyh_state =>
4982
                                 -- increment sp
4983
             left_ctrl  <= sp_left;
4984
             right_ctrl <= one_right;
4985
             alu_ctrl   <= alu_add16;
4986
             sp_ctrl    <= load_sp;
4987
                                 -- read iy hi
4988
                                 iy_ctrl    <= pull_hi_iy;
4989
             addr_ctrl  <= pulls_ad;
4990
             next_state <= rti_iyl_state;
4991
 
4992
                          when rti_iyl_state =>
4993
                                 -- increment sp
4994
             left_ctrl  <= sp_left;
4995
             right_ctrl <= one_right;
4996
             alu_ctrl   <= alu_add16;
4997
             sp_ctrl    <= load_sp;
4998
                                 -- read iy low
4999
                                 iy_ctrl    <= pull_lo_iy;
5000
             addr_ctrl  <= pulls_ad;
5001
             next_state <= rti_uph_state;
5002
 
5003
 
5004
                          when rti_uph_state =>
5005
                                 -- increment sp
5006
             left_ctrl  <= sp_left;
5007
             right_ctrl <= one_right;
5008
             alu_ctrl   <= alu_add16;
5009
             sp_ctrl    <= load_sp;
5010
                                 -- read up hi
5011
                                 up_ctrl    <= pull_hi_up;
5012
             addr_ctrl  <= pulls_ad;
5013
             next_state <= rti_upl_state;
5014
 
5015
                          when rti_upl_state =>
5016
                                 -- increment sp
5017
             left_ctrl  <= sp_left;
5018
             right_ctrl <= one_right;
5019
             alu_ctrl   <= alu_add16;
5020
             sp_ctrl    <= load_sp;
5021
                                 -- read up low
5022
             up_ctrl    <= pull_lo_up;
5023
             addr_ctrl  <= pulls_ad;
5024
             next_state <= rti_pch_state;
5025
 
5026
                          when rti_pch_state =>
5027
                  -- increment sp
5028
             left_ctrl  <= sp_left;
5029
             right_ctrl <= one_right;
5030
             alu_ctrl   <= alu_add16;
5031
             sp_ctrl    <= load_sp;
5032
                                 -- pull pc hi
5033
                                 pc_ctrl    <= pull_hi_pc;
5034
             addr_ctrl  <= pulls_ad;
5035
             next_state <= rti_pcl_state;
5036
 
5037
                          when rti_pcl_state =>
5038
                                 -- increment sp
5039
             left_ctrl  <= sp_left;
5040
             right_ctrl <= one_right;
5041
             alu_ctrl   <= alu_add16;
5042
             sp_ctrl    <= load_sp;
5043
                  -- pull pc low
5044
                                 pc_ctrl    <= pull_lo_pc;
5045
             addr_ctrl  <= pulls_ad;
5046
             lic        <= '1';
5047
             next_state <= fetch_state;
5048
 
5049
                          --
5050
                          -- here on NMI interrupt
5051
                          -- Complete execute cycle of the last instruction.
5052
           -- If it was a dual operand instruction
5053
           --
5054
                          when int_nmi_state =>
5055
             next_state   <= int_nmi1_state;
5056
 
5057
                          -- Idle bus cycle
5058
           when int_nmi1_state =>
5059
             -- pre decrement sp
5060
             left_ctrl    <= sp_left;
5061
             right_ctrl   <= one_right;
5062
             alu_ctrl     <= alu_sub16;
5063
             sp_ctrl      <= load_sp;
5064
                                 iv_ctrl      <= nmi_iv;
5065
                                 st_ctrl      <= push_st;
5066
                                 return_state <= int_nmimask_state;
5067
             next_state   <= int_entire_state;
5068
 
5069
                          --
5070
                          -- here on IRQ interrupt
5071
                          -- Complete execute cycle of the last instruction.
5072
           -- If it was a dual operand instruction
5073
           --
5074
                          when int_irq_state =>
5075
             next_state   <= int_irq1_state;
5076
 
5077
                          -- pre decrement the sp
5078
                          -- Idle bus cycle
5079
           when int_irq1_state =>
5080
             -- pre decrement sp
5081
             left_ctrl    <= sp_left;
5082
             right_ctrl   <= one_right;
5083
             alu_ctrl     <= alu_sub16;
5084
             sp_ctrl      <= load_sp;
5085
                                 iv_ctrl      <= irq_iv;
5086
                                 st_ctrl      <= push_st;
5087
                                 return_state <= int_irqmask_state;
5088
             next_state   <= int_entire_state;
5089
 
5090
                          --
5091
                          -- here on FIRQ interrupt
5092
                          -- Complete execution cycle of the last instruction
5093
           -- if it was a dual operand instruction
5094
           --
5095
                          when int_firq_state =>
5096
             next_state   <= int_firq1_state;
5097
 
5098
                          -- Idle bus cycle
5099
           when int_firq1_state =>
5100
             -- pre decrement sp
5101
             left_ctrl    <= sp_left;
5102
             right_ctrl   <= one_right;
5103
             alu_ctrl     <= alu_sub16;
5104
             sp_ctrl      <= load_sp;
5105
                                 iv_ctrl      <= firq_iv;
5106
                                 st_ctrl      <= push_st;
5107
                                 return_state <= int_firqmask_state;
5108
             next_state   <= int_fast_state;
5109
 
5110
           --
5111
           -- CWAI entry point
5112
           -- stack pointer already pre-decremented
5113
           -- mask condition codes
5114
           --
5115
           when cwai_state =>
5116
              -- AND CC with md
5117
              left_ctrl    <= md_left;
5118
              right_ctrl   <= zero_right;
5119
              alu_ctrl     <= alu_andcc;
5120
              cc_ctrl      <= load_cc;
5121
                                  st_ctrl      <= push_st;
5122
                                  return_state <= int_cwai_state;
5123
                                  next_state   <= int_entire_state;
5124
 
5125
                          --
5126
                          -- wait here for an interrupt
5127
                          --
5128
                          when int_cwai_state =>
5129
             if (nmi_req = '1') then
5130
                                   iv_ctrl    <= nmi_iv;
5131
                              next_state <= int_nmimask_state;
5132
                                 --
5133
                                 -- FIRQ & IRQ are level sensitive
5134
                                 --
5135
             elsif (firq = '1') and (cc(FBIT) = '0') then
5136
                                   iv_ctrl     <= firq_iv;
5137
                              next_state  <= int_firqmask_state;
5138
 
5139
                            elsif (irq = '1') and (cc(IBIT) = '0') then
5140
                                   iv_ctrl     <= irq_iv;
5141
                              next_state  <= int_irqmask_state;
5142
                            else
5143
                                   next_state <= int_cwai_state;
5144
             end if;
5145
 
5146
           --
5147
                          -- State to mask I Flag and F Flag (NMI)
5148
                          --
5149
                          when int_nmimask_state =>
5150
                            alu_ctrl   <= alu_seif;
5151
                                 cc_ctrl    <= load_cc;
5152
             next_state <= vect_hi_state;
5153
 
5154
           --
5155
                          -- State to mask I Flag and F Flag (FIRQ)
5156
                          --
5157
                          when int_firqmask_state =>
5158
                            alu_ctrl   <= alu_seif;
5159
                                 cc_ctrl    <= load_cc;
5160
             next_state <= vect_hi_state;
5161
 
5162
 
5163
           --
5164
                          -- State to mask I Flag and F Flag (SWI)
5165
                          --
5166
                          when int_swimask_state =>
5167
                            alu_ctrl   <= alu_seif;
5168
                                 cc_ctrl    <= load_cc;
5169
             next_state <= vect_hi_state;
5170
 
5171
           --
5172
                          -- State to mask I Flag only (IRQ)
5173
                          --
5174
           when int_irqmask_state =>
5175
                                 alu_ctrl   <= alu_sei;
5176
                                 cc_ctrl    <= load_cc;
5177
             next_state <= vect_hi_state;
5178
 
5179
                          --
5180
                          -- set Entire Flag on SWI, SWI2, SWI3 and CWAI, IRQ and NMI
5181
                          -- before stacking all registers
5182
                          --
5183
                          when int_entire_state =>
5184
             -- set entire flag
5185
             alu_ctrl   <= alu_see;
5186
             cc_ctrl    <= load_cc;
5187
             next_state <= int_pcl_state;
5188
 
5189
                          --
5190
                          -- clear Entire Flag on FIRQ
5191
                          -- before stacking all registers
5192
                          --
5193
                          when int_fast_state =>
5194
             -- clear entire flag
5195
             alu_ctrl   <= alu_cle;
5196
             cc_ctrl    <= load_cc;
5197
             next_state <= int_pcl_state;
5198
 
5199
                          when int_pcl_state =>
5200
             -- decrement sp
5201
             left_ctrl  <= sp_left;
5202
             right_ctrl <= one_right;
5203
             alu_ctrl   <= alu_sub16;
5204
             sp_ctrl    <= load_sp;
5205
                                 -- write pc low
5206
             addr_ctrl  <= pushs_ad;
5207
                            dout_ctrl  <= pc_lo_dout;
5208
             next_state <= int_pch_state;
5209
 
5210
                          when int_pch_state =>
5211
             -- decrement sp
5212
             left_ctrl  <= sp_left;
5213
             right_ctrl <= one_right;
5214
             alu_ctrl   <= alu_sub16;
5215
             sp_ctrl    <= load_sp;
5216
                                 -- write pc hi
5217
             addr_ctrl  <= pushs_ad;
5218
                            dout_ctrl  <= pc_hi_dout;
5219
                                 if cc(EBIT) = '1' then
5220
               next_state   <= int_upl_state;
5221
                                 else
5222
               next_state   <= int_cc_state;
5223
                                 end if;
5224
 
5225
                          when int_upl_state =>
5226
             -- decrement sp
5227
             left_ctrl  <= sp_left;
5228
             right_ctrl <= one_right;
5229
             alu_ctrl   <= alu_sub16;
5230
             sp_ctrl    <= load_sp;
5231
                                 -- write up low
5232
             addr_ctrl  <= pushs_ad;
5233
                            dout_ctrl  <= up_lo_dout;
5234
             next_state <= int_uph_state;
5235
 
5236
                          when int_uph_state =>
5237
             -- decrement sp
5238
             left_ctrl  <= sp_left;
5239
             right_ctrl <= one_right;
5240
             alu_ctrl   <= alu_sub16;
5241
             sp_ctrl    <= load_sp;
5242
                                 -- write ix hi
5243
             addr_ctrl  <= pushs_ad;
5244
                            dout_ctrl  <= up_hi_dout;
5245
             next_state <= int_iyl_state;
5246
 
5247
                          when int_iyl_state =>
5248
             -- decrement sp
5249
             left_ctrl  <= sp_left;
5250
             right_ctrl <= one_right;
5251
             alu_ctrl   <= alu_sub16;
5252
             sp_ctrl    <= load_sp;
5253
                                 -- write ix low
5254
             addr_ctrl  <= pushs_ad;
5255
                            dout_ctrl  <= iy_lo_dout;
5256
             next_state <= int_iyh_state;
5257
 
5258
                          when int_iyh_state =>
5259
             -- decrement sp
5260
             left_ctrl  <= sp_left;
5261
             right_ctrl <= one_right;
5262
             alu_ctrl   <= alu_sub16;
5263
             sp_ctrl    <= load_sp;
5264
                                 -- write ix hi
5265
             addr_ctrl  <= pushs_ad;
5266
                            dout_ctrl  <= iy_hi_dout;
5267
             next_state <= int_ixl_state;
5268
 
5269
                          when int_ixl_state =>
5270
             -- decrement sp
5271
             left_ctrl  <= sp_left;
5272
             right_ctrl <= one_right;
5273
             alu_ctrl   <= alu_sub16;
5274
             sp_ctrl    <= load_sp;
5275
                                 -- write ix low
5276
             addr_ctrl  <= pushs_ad;
5277
                            dout_ctrl  <= ix_lo_dout;
5278
             next_state <= int_ixh_state;
5279
 
5280
                          when int_ixh_state =>
5281
             -- decrement sp
5282
             left_ctrl  <= sp_left;
5283
             right_ctrl <= one_right;
5284
             alu_ctrl   <= alu_sub16;
5285
             sp_ctrl    <= load_sp;
5286
                                 -- write ix hi
5287
             addr_ctrl  <= pushs_ad;
5288
                            dout_ctrl  <= ix_hi_dout;
5289
             next_state <= int_dp_state;
5290
 
5291
                          when int_dp_state =>
5292
             -- decrement sp
5293
             left_ctrl  <= sp_left;
5294
             right_ctrl <= one_right;
5295
             alu_ctrl   <= alu_sub16;
5296
             sp_ctrl    <= load_sp;
5297
                                 -- write accb
5298
             addr_ctrl  <= pushs_ad;
5299
                            dout_ctrl  <= dp_dout;
5300
             next_state <= int_accb_state;
5301
 
5302
                          when int_accb_state =>
5303
             -- decrement sp
5304
             left_ctrl  <= sp_left;
5305
             right_ctrl <= one_right;
5306
             alu_ctrl   <= alu_sub16;
5307
             sp_ctrl    <= load_sp;
5308
                                 -- write accb
5309
             addr_ctrl  <= pushs_ad;
5310
                            dout_ctrl  <= accb_dout;
5311
             next_state <= int_acca_state;
5312
 
5313
                          when int_acca_state =>
5314
             -- decrement sp
5315
             left_ctrl  <= sp_left;
5316
             right_ctrl <= one_right;
5317
             alu_ctrl   <= alu_sub16;
5318
             sp_ctrl    <= load_sp;
5319
                                 -- write acca
5320
             addr_ctrl  <= pushs_ad;
5321
                            dout_ctrl  <= acca_dout;
5322
             next_state <= int_cc_state;
5323
 
5324
                          when int_cc_state =>
5325
                                 -- write cc
5326
             addr_ctrl  <= pushs_ad;
5327
                            dout_ctrl  <= cc_dout;
5328
                                 next_state <= saved_state;
5329
 
5330
                          --
5331
                          -- According to the 6809 programming manual:
5332
                          -- If an interrupt is received and is masked 
5333
                          -- or lasts for less than three cycles, the PC 
5334
                          -- will advance to the next instruction.
5335
                          -- If an interrupt is unmasked and lasts
5336
                          -- for more than three cycles, an interrupt
5337
                          -- will be generated.
5338
                          -- Note that I don't wait 3 clock cycles.
5339
                          -- John Kent 11th July 2006
5340
                          --
5341
                          when sync_state =>
5342
             lic        <= '1';
5343
             ba         <= '1';
5344
                         --
5345
                         -- Version 1.28 2015-05-30
5346
                         -- Exit sync_state on interrupt.
5347
                         -- If the interrupts are active
5348
                         -- they will be caught in the state_machine process
5349
                         -- and the interrupt service routine microcode will be executed.
5350
                         -- Masked interrupts will exit the sync_state.
5351
                         -- Moved from the state_machine process to the state_sequencer process
5352
                         --
5353
                                if (firq = '1') or (irq = '1') then
5354
               next_state <= fetch_state;
5355
                                else
5356
                    next_state <= sync_state;
5357
            end if;
5358
 
5359
                          when halt_state =>
5360
           --
5361
           -- 2011-10-30 John Kent
5362
           -- ba & bs should be high
5363
             ba           <= '1';
5364
             bs           <= '1';
5365
                                 if halt = '1' then
5366
               next_state   <= halt_state;
5367
                                 else
5368
               next_state   <= fetch_state;
5369
                                 end if;
5370
 
5371
                  end case;
5372
 
5373
--
5374
-- Ver 1.23 2011-10-30 John Kent
5375
-- First instruction cycle might be
5376
-- fetch_state
5377
-- halt_state
5378
-- int_nmirq_state
5379
-- int_firq_state
5380
--
5381
        if fic = '1' then
5382
                           --
5383
                                        case op_code(7 downto 6) is
5384
                                        --
5385
                                        -- ver 1.29 
5386
                                        -- hide last cycle of multiply in fetch
5387
                                        --
5388
                                        when "00" =>
5389
                                          case op_code(5 downto 0) is
5390
                                          when "111101" => -- mul
5391
                                            -- if bit 7 of ea set, add accd to md
5392
                   left_ctrl  <= accd_left;
5393
                                            if ea(7) = '1' then
5394
                     right_ctrl <= md_right;
5395
                                            else
5396
                     right_ctrl <= zero_right;
5397
                                            end if;
5398
                   alu_ctrl   <= alu_mul;
5399
                   cc_ctrl    <= load_cc;
5400
                   acca_ctrl  <= load_hi_acca;
5401
                   accb_ctrl  <= load_accb;
5402
                 when others =>
5403
                                             null;
5404
                                          end case;
5405
                                        when "10" => -- acca
5406
                                     case op_code(3 downto 0) is
5407
                                          when "0000" => -- suba
5408
                                            left_ctrl  <= acca_left;
5409
                                            right_ctrl <= md_right;
5410
                                            alu_ctrl   <= alu_sub8;
5411
                                                 cc_ctrl    <= load_cc;
5412
                                            acca_ctrl  <= load_acca;
5413
                                          when "0001" => -- cmpa
5414
                                            left_ctrl   <= acca_left;
5415
                                            right_ctrl  <= md_right;
5416
                                            alu_ctrl    <= alu_sub8;
5417
                                                 cc_ctrl     <= load_cc;
5418
                                          when "0010" => -- sbca
5419
                                            left_ctrl   <= acca_left;
5420
                                            right_ctrl  <= md_right;
5421
                                            alu_ctrl    <= alu_sbc;
5422
                                                 cc_ctrl     <= load_cc;
5423
                                            acca_ctrl   <= load_acca;
5424
                                          when "0011" =>
5425
                                            case pre_code is
5426
                                                 when "00010000" => -- page 2 -- cmpd
5427
                                              left_ctrl   <= accd_left;
5428
                                              right_ctrl  <= md_right;
5429
                                              alu_ctrl    <= alu_sub16;
5430
                                                   cc_ctrl     <= load_cc;
5431
                                                 when "00010001" => -- page 3 -- cmpu
5432
                                              left_ctrl   <= up_left;
5433
                                              right_ctrl  <= md_right;
5434
                                              alu_ctrl    <= alu_sub16;
5435
                                                   cc_ctrl     <= load_cc;
5436
                                                 when others => -- page 1 -- subd
5437
                                              left_ctrl   <= accd_left;
5438
                                              right_ctrl  <= md_right;
5439
                                              alu_ctrl    <= alu_sub16;
5440
                                                   cc_ctrl     <= load_cc;
5441
                                              acca_ctrl   <= load_hi_acca;
5442
                                                   accb_ctrl   <= load_accb;
5443
                                                 end case;
5444
                                          when "0100" => -- anda
5445
                                            left_ctrl   <= acca_left;
5446
                                            right_ctrl  <= md_right;
5447
                                            alu_ctrl    <= alu_and;
5448
                                                 cc_ctrl     <= load_cc;
5449
                                            acca_ctrl   <= load_acca;
5450
                                          when "0101" => -- bita
5451
                                            left_ctrl   <= acca_left;
5452
                                            right_ctrl  <= md_right;
5453
                                            alu_ctrl    <= alu_and;
5454
                                                 cc_ctrl     <= load_cc;
5455
                                          when "0110" => -- ldaa
5456
                                            left_ctrl   <= acca_left;
5457
                                            right_ctrl  <= md_right;
5458
                                            alu_ctrl    <= alu_ld8;
5459
                                                 cc_ctrl     <= load_cc;
5460
                                            acca_ctrl   <= load_acca;
5461
                                          when "0111" => -- staa
5462
                                            left_ctrl   <= acca_left;
5463
                                            right_ctrl  <= md_right;
5464
                                            alu_ctrl    <= alu_st8;
5465
                                                 cc_ctrl     <= load_cc;
5466
                                          when "1000" => -- eora
5467
                                            left_ctrl   <= acca_left;
5468
                                            right_ctrl  <= md_right;
5469
                                            alu_ctrl    <= alu_eor;
5470
                                                 cc_ctrl     <= load_cc;
5471
                                            acca_ctrl   <= load_acca;
5472
                                          when "1001" => -- adca
5473
                                            left_ctrl   <= acca_left;
5474
                                            right_ctrl  <= md_right;
5475
                                            alu_ctrl    <= alu_adc;
5476
                                                 cc_ctrl     <= load_cc;
5477
                                            acca_ctrl   <= load_acca;
5478
                                          when "1010" => -- oraa
5479
                                            left_ctrl   <= acca_left;
5480
                                            right_ctrl  <= md_right;
5481
                                            alu_ctrl    <= alu_ora;
5482
                                                 cc_ctrl     <= load_cc;
5483
                                            acca_ctrl   <= load_acca;
5484
                                          when "1011" => -- adda
5485
                                            left_ctrl   <= acca_left;
5486
                                            right_ctrl  <= md_right;
5487
                                            alu_ctrl    <= alu_add8;
5488
                                                 cc_ctrl     <= load_cc;
5489
                                            acca_ctrl   <= load_acca;
5490
                                          when "1100" =>
5491
                                            case pre_code is
5492
                                                 when "00010000" => -- page 2 -- cmpy
5493
                                              left_ctrl   <= iy_left;
5494
                                              right_ctrl  <= md_right;
5495
                                              alu_ctrl    <= alu_sub16;
5496
                                                   cc_ctrl     <= load_cc;
5497
                                                 when "00010001" => -- page 3 -- cmps
5498
                                              left_ctrl   <= sp_left;
5499
                                              right_ctrl  <= md_right;
5500
                                              alu_ctrl    <= alu_sub16;
5501
                                                   cc_ctrl     <= load_cc;
5502
                                                 when others => -- page 1 -- cmpx
5503
                                              left_ctrl   <= ix_left;
5504
                                              right_ctrl  <= md_right;
5505
                                              alu_ctrl    <= alu_sub16;
5506
                                                   cc_ctrl     <= load_cc;
5507
                                                 end case;
5508
                                          when "1101" => -- bsr / jsr
5509
                                            null;
5510
                                          when "1110" => -- ldx
5511
                                            case pre_code is
5512
                                                 when "00010000" => -- page 2 -- ldy
5513
                                              left_ctrl   <= iy_left;
5514
                                              right_ctrl  <= md_right;
5515
                                              alu_ctrl    <= alu_ld16;
5516
                                                   cc_ctrl     <= load_cc;
5517
                     iy_ctrl     <= load_iy;
5518
                                                 when others =>   -- page 1 -- ldx
5519
                                              left_ctrl   <= ix_left;
5520
                                              right_ctrl  <= md_right;
5521
                                              alu_ctrl    <= alu_ld16;
5522
                                                   cc_ctrl     <= load_cc;
5523
                     ix_ctrl     <= load_ix;
5524
                                                 end case;
5525
                                          when "1111" => -- stx
5526
                                            case pre_code is
5527
                                                 when "00010000" => -- page 2 -- sty
5528
                                              left_ctrl   <= iy_left;
5529
                                              right_ctrl  <= md_right;
5530
                                              alu_ctrl    <= alu_st16;
5531
                                                   cc_ctrl     <= load_cc;
5532
                                                 when others =>     -- page 1 -- stx
5533
                                              left_ctrl   <= ix_left;
5534
                                              right_ctrl  <= md_right;
5535
                                              alu_ctrl    <= alu_st16;
5536
                                                   cc_ctrl     <= load_cc;
5537
                                                 end case;
5538
                                          when others =>
5539
                                            null;
5540
                                          end case;
5541
                                        when "11" => -- accb dual op
5542
                                     case op_code(3 downto 0) is
5543
                                          when "0000" => -- subb
5544
                                            left_ctrl   <= accb_left;
5545
                                            right_ctrl  <= md_right;
5546
                                            alu_ctrl    <= alu_sub8;
5547
                                                 cc_ctrl     <= load_cc;
5548
                   accb_ctrl   <= load_accb;
5549
                                          when "0001" => -- cmpb
5550
                                            left_ctrl   <= accb_left;
5551
                                            right_ctrl  <= md_right;
5552
                                            alu_ctrl    <= alu_sub8;
5553
                                                 cc_ctrl     <= load_cc;
5554
                                          when "0010" => -- sbcb
5555
                                            left_ctrl   <= accb_left;
5556
                                            right_ctrl  <= md_right;
5557
                                            alu_ctrl    <= alu_sbc;
5558
                                                 cc_ctrl     <= load_cc;
5559
                   accb_ctrl   <= load_accb;
5560
                                          when "0011" => -- addd
5561
                                            left_ctrl   <= accd_left;
5562
                                            right_ctrl  <= md_right;
5563
                                            alu_ctrl    <= alu_add16;
5564
                                                 cc_ctrl     <= load_cc;
5565
                                            acca_ctrl   <= load_hi_acca;
5566
                                                 accb_ctrl   <= load_accb;
5567
                                          when "0100" => -- andb
5568
                                            left_ctrl   <= accb_left;
5569
                                            right_ctrl  <= md_right;
5570
                                            alu_ctrl    <= alu_and;
5571
                                                 cc_ctrl     <= load_cc;
5572
                   accb_ctrl   <= load_accb;
5573
                                          when "0101" => -- bitb
5574
                                            left_ctrl   <= accb_left;
5575
                                            right_ctrl  <= md_right;
5576
                                            alu_ctrl    <= alu_and;
5577
                                                 cc_ctrl     <= load_cc;
5578
                                          when "0110" => -- ldab
5579
                                            left_ctrl   <= accb_left;
5580
                                            right_ctrl  <= md_right;
5581
                                            alu_ctrl    <= alu_ld8;
5582
                                                 cc_ctrl     <= load_cc;
5583
                   accb_ctrl   <= load_accb;
5584
                                          when "0111" => -- stab
5585
                                            left_ctrl   <= accb_left;
5586
                                            right_ctrl  <= md_right;
5587
                                            alu_ctrl    <= alu_st8;
5588
                                                 cc_ctrl     <= load_cc;
5589
                                          when "1000" => -- eorb
5590
                                            left_ctrl   <= accb_left;
5591
                                            right_ctrl  <= md_right;
5592
                                            alu_ctrl    <= alu_eor;
5593
                                                 cc_ctrl     <= load_cc;
5594
                   accb_ctrl   <= load_accb;
5595
                                          when "1001" => -- adcb
5596
                                            left_ctrl   <= accb_left;
5597
                                            right_ctrl  <= md_right;
5598
                                            alu_ctrl    <= alu_adc;
5599
                                                 cc_ctrl     <= load_cc;
5600
                   accb_ctrl   <= load_accb;
5601
                                          when "1010" => -- orab
5602
                                            left_ctrl   <= accb_left;
5603
                                            right_ctrl  <= md_right;
5604
                                            alu_ctrl    <= alu_ora;
5605
                                                 cc_ctrl     <= load_cc;
5606
                   accb_ctrl   <= load_accb;
5607
                                          when "1011" => -- addb
5608
                                            left_ctrl   <= accb_left;
5609
                                            right_ctrl  <= md_right;
5610
                                            alu_ctrl    <= alu_add8;
5611
                                                 cc_ctrl     <= load_cc;
5612
                   accb_ctrl   <= load_accb;
5613
                                          when "1100" => -- ldd
5614
                                            left_ctrl   <= accd_left;
5615
                                            right_ctrl  <= md_right;
5616
                                            alu_ctrl    <= alu_ld16;
5617
                                                 cc_ctrl     <= load_cc;
5618
                                            acca_ctrl   <= load_hi_acca;
5619
                   accb_ctrl   <= load_accb;
5620
                                          when "1101" => -- std
5621
                                            left_ctrl   <= accd_left;
5622
                                            right_ctrl  <= md_right;
5623
                                            alu_ctrl    <= alu_st16;
5624
                                                 cc_ctrl     <= load_cc;
5625
                                          when "1110" => -- ldu
5626
                                            case pre_code is
5627
                                                 when "00010000" => -- page 2 -- lds
5628
                                              left_ctrl   <= sp_left;
5629
                                              right_ctrl  <= md_right;
5630
                                              alu_ctrl    <= alu_ld16;
5631
                                                   cc_ctrl     <= load_cc;
5632
                                                   sp_ctrl     <= load_sp;
5633
                                                 when others => -- page 1 -- ldu
5634
                                              left_ctrl   <= up_left;
5635
                                              right_ctrl  <= md_right;
5636
                                              alu_ctrl    <= alu_ld16;
5637
                                                   cc_ctrl     <= load_cc;
5638
                     up_ctrl     <= load_up;
5639
                                                 end case;
5640
                                          when "1111" =>
5641
                                            case pre_code is
5642
                                                 when "00010000" => -- page 2 -- sts
5643
                                              left_ctrl   <= sp_left;
5644
                                              right_ctrl  <= md_right;
5645
                                              alu_ctrl    <= alu_st16;
5646
                                                   cc_ctrl     <= load_cc;
5647
                                                 when others =>     -- page 1 -- stu
5648
                                              left_ctrl   <= up_left;
5649
                                              right_ctrl  <= md_right;
5650
                                              alu_ctrl    <= alu_st16;
5651
                                                   cc_ctrl     <= load_cc;
5652
                                                 end case;
5653
                                          when others =>
5654
                                            null;
5655
                                          end case;
5656
                                        when others =>
5657
                                          null;
5658
                                        end case;
5659
 
5660
       end if; -- first instruction cycle (fic)
5661
       lic_out <= lic;
5662
end process;
5663
 
5664
end rtl;
5665
 

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