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[/] [System09/] [trunk/] [rtl/] [VHDL/] [pia_timer.vhd] - Blame information for rev 113

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1 99 davidgb
--===========================================================================--
2
--                                                                           --
3
--  pia_timer.vhd - Synthesizable Parallel Interface Adapter with Timer      --
4
--                                                                           --
5
--===========================================================================--
6
--
7
--  File name      : pia_timer.vhd
8
--
9
--  Entity name    : pia_timer
10
--
11
--  Purpose        : Implements 2 x 8 bit parallel I/O ports
12
--                   with 8 bit presetable counter.
13
--                   Port A Data = output connected to presettable counter input
14
--                   Port B Data = input connected to counter output
15
--                   Used with Digilent Spartan 3E starter board
16
--                   to implement a single step trace function.
17
--                  
18
--  Dependencies   : ieee.std_logic_1164
19
--                   ieee.std_logic_unsigned
20
--                   unisim.vcomponents
21
--
22
--  Author         : John E. Kent
23
--
24
--  Email          : dilbert57@opencores.org      
25
--
26
--  Web            : http://opencores.org/project,system09
27
-- 
28
--  Description    : Register Memory Map
29
--
30
--                   Base + $00 - Port A Data & Direction register
31
--                   Base + $01 - Port A Control register
32
--                   Base + $02 - Port B Data & Direction Direction Register
33
--                   Base + $03 - Port B Control Register
34
--
35
--  Copyright (C) 2004 - 2010 John Kent
36
--
37
--  This program is free software: you can redistribute it and/or modify
38
--  it under the terms of the GNU General Public License as published by
39
--  the Free Software Foundation, either version 3 of the License, or
40
--  (at your option) any later version.
41
--
42
--  This program is distributed in the hope that it will be useful,
43
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
44
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
45
--  GNU General Public License for more details.
46
--
47
--  You should have received a copy of the GNU General Public License
48
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
49
--
50
--===========================================================================--
51
--                                                                           --
52
--                              Revision  History                            --
53
--                                                                           --
54
--===========================================================================--
55
--
56
-- Version  Author        Date               Description
57
-- 0.0      John Kent     1st May 2004       Initial version developed from ioport.vhd
58
--
59
-- 1.0      John Kent     22nd April 2006    Removed I/O ports and hard wired a binary
60
--                                           down counter. Port A is the preset output.
61
--                                           Port B is the timer count input.
62
--                                           CA1 & CB1 are interrupt inputs
63
--                                           CA2 is the counter load (active low)
64
--                                           CB2 is the counter reset (active high)
65
--                                           It may be necessary to offset the counter
66
--                                           to compensate for differences in cpu cycle
67
--                                           times between FPGA and real 6809 systems.
68
--
69
-- 1.1      John Kent     24th May 2006      Modified counter to subtract one from preset
70
--                                           so FPGA version of the CMC_BUG monitor is
71
--                                           compatible with the reference design.
72
--
73
-- 1.2      John Kent     30th May 2010      Revised header and added updated GPL
74
--
75
--===========================================================================----
76
--
77
-- Memory Map
78
--
79
-- IO + $00 - Port A Data & Direction register
80
-- IO + $01 - Port A Control register
81
-- IO + $02 - Port B Data & Direction Direction Register
82
-- IO + $03 - Port B Control Register
83
--
84
 
85
library ieee;
86
   use ieee.std_logic_1164.all;
87
   use ieee.std_logic_unsigned.all;
88
library unisim;
89
   use unisim.vcomponents.all;
90
 
91
entity pia_timer is
92
        port (
93
         clk       : in    std_logic;
94
    rst       : in    std_logic;
95
    cs        : in    std_logic;
96
    rw        : in    std_logic;
97
    addr      : in    std_logic_vector(1 downto 0);
98
    data_in   : in    std_logic_vector(7 downto 0);
99
         data_out  : out   std_logic_vector(7 downto 0);
100
         irqa      : out   std_logic;
101
         irqb      : out   std_logic
102
         );
103
end;
104
 
105
architecture pia_arch of pia_timer is
106
 
107
signal pa          : std_logic_vector(7 downto 0);
108
signal porta_ddr   : std_logic_vector(7 downto 0);
109
signal porta_data  : std_logic_vector(7 downto 0);
110
signal porta_ctrl  : std_logic_vector(5 downto 0);
111
signal porta_read  : std_logic;
112
 
113
signal pb          : std_logic_vector(7 downto 0);
114
signal portb_ddr   : std_logic_vector(7 downto 0);
115
signal portb_data  : std_logic_vector(7 downto 0);
116
signal portb_ctrl  : std_logic_vector(5 downto 0);
117
signal portb_read  : std_logic;
118
signal portb_write : std_logic;
119
 
120
signal ca1         : std_logic;
121
signal ca1_del     : std_logic;
122
signal ca1_rise    : std_logic;
123
signal ca1_fall    : std_logic;
124
signal ca1_edge    : std_logic;
125
signal irqa1       : std_logic;
126
 
127
signal ca2         : std_logic;
128
signal ca2_del     : std_logic;
129
signal ca2_rise    : std_logic;
130
signal ca2_fall    : std_logic;
131
signal ca2_edge    : std_logic;
132
signal irqa2       : std_logic;
133
signal ca2_out     : std_logic;
134
 
135
signal cb1         : std_logic;
136
signal cb1_del     : std_logic;
137
signal cb1_rise    : std_logic;
138
signal cb1_fall    : std_logic;
139
signal cb1_edge    : std_logic;
140
signal irqb1       : std_logic;
141
 
142
signal cb2         : std_logic;
143
signal cb2_del     : std_logic;
144
signal cb2_rise    : std_logic;
145
signal cb2_fall    : std_logic;
146
signal cb2_edge    : std_logic;
147
signal irqb2       : std_logic;
148
signal cb2_out     : std_logic;
149
 
150
-- 74193 down counter
151
signal timer       : std_logic_vector(7 downto 0);
152
 
153
begin
154
 
155
--------------------------------
156
--
157
-- read I/O port
158
--
159
--------------------------------
160
 
161
pia_read : process(  addr,      cs,
162
                     irqa1, irqa2, irqb1, irqb2,
163
                     porta_ddr,  portb_ddr,
164
                                                        porta_data, portb_data,
165
                                                        porta_ctrl, portb_ctrl,
166
                                                   pa,         pb )
167
variable count : integer;
168
begin
169
      case addr is
170
             when "00" =>
171
                    for count in 0 to 7 loop
172
                           if porta_ctrl(2) = '0' then
173
                                  data_out(count) <= porta_ddr(count);
174
                             porta_read <= '0';
175
            else
176
                                  if porta_ddr(count) = '1' then
177
                data_out(count) <= porta_data(count);
178
              else
179
                data_out(count) <= pa(count);
180
              end if;
181
                             porta_read <= cs;
182
            end if;
183
                         end loop;
184
                         portb_read <= '0';
185
 
186
             when "01" =>
187
                    data_out <= irqa1 & irqa2 & porta_ctrl;
188
                         porta_read <= '0';
189
                         portb_read <= '0';
190
 
191
                  when "10" =>
192
                    for count in 0 to 7 loop
193
                           if portb_ctrl(2) = '0' then
194
                                  data_out(count) <= portb_ddr(count);
195
                                  portb_read <= '0';
196
            else
197
                                  if portb_ddr(count) = '1' then
198
                data_out(count) <= portb_data(count);
199
              else
200
                data_out(count) <= pb(count);
201
                                  end if;
202
                                  portb_read <= cs;
203
            end if;
204
                         end loop;
205
                         porta_read <= '0';
206
 
207
                  when "11" =>
208
                    data_out <= irqb1 & irqb2 & portb_ctrl;
209
                         porta_read <= '0';
210
                         portb_read <= '0';
211
 
212
                  when others =>
213
                    data_out <= "00000000";
214
                         porta_read <= '0';
215
                         portb_read <= '0';
216
 
217
                end case;
218
end process;
219
 
220
---------------------------------
221
--
222
-- Write I/O ports
223
--
224
---------------------------------
225
 
226
pia_write : process( clk, rst, addr, cs, rw, data_in,
227
                        porta_ctrl, portb_ctrl,
228
                        porta_data, portb_data,
229
                                                                porta_ctrl, portb_ctrl,
230
                                                                porta_ddr, portb_ddr )
231
begin
232
  if rst = '1' then
233
      porta_ddr   <= "00000000";
234
      porta_data  <= "00000000";
235
      porta_ctrl  <= "000000";
236
      portb_ddr   <= "00000000";
237
      portb_data  <= "00000000";
238
                portb_ctrl  <= "000000";
239
                portb_write <= '0';
240
  elsif clk'event and clk = '1' then
241
    if cs = '1' and rw = '0' then
242
      case addr is
243
             when "00" =>
244
                    if porta_ctrl(2) = '0' then
245
                       porta_ddr  <= data_in;
246
                       porta_data <= porta_data;
247
                         else
248
                       porta_ddr  <= porta_ddr;
249
                       porta_data <= data_in;
250
                         end if;
251
                         porta_ctrl  <= porta_ctrl;
252
                    portb_ddr   <= portb_ddr;
253
                    portb_data  <= portb_data;
254
                         portb_ctrl  <= portb_ctrl;
255
                         portb_write <= '0';
256
                  when "01" =>
257
                    porta_ddr   <= porta_ddr;
258
                    porta_data  <= porta_data;
259
                         porta_ctrl  <= data_in(5 downto 0);
260
                    portb_ddr   <= portb_ddr;
261
                    portb_data  <= portb_data;
262
                         portb_ctrl  <= portb_ctrl;
263
                         portb_write <= '0';
264
             when "10" =>
265
                    porta_ddr   <= porta_ddr;
266
                    porta_data  <= porta_data;
267
                         porta_ctrl  <= porta_ctrl;
268
                    if portb_ctrl(2) = '0' then
269
                       portb_ddr   <= data_in;
270
                       portb_data  <= portb_data;
271
                            portb_write <= '0';
272
                         else
273
                       portb_ddr   <= portb_ddr;
274
                       portb_data  <= data_in;
275
                            portb_write <= '1';
276
                         end if;
277
                         portb_ctrl  <= portb_ctrl;
278
                  when "11" =>
279
                    porta_ddr   <= porta_ddr;
280
                    porta_data  <= porta_data;
281
                         porta_ctrl  <= porta_ctrl;
282
                    portb_ddr   <= portb_ddr;
283
                    portb_data  <= portb_data;
284
                         portb_ctrl  <= data_in(5 downto 0);
285
                         portb_write <= '0';
286
                  when others =>
287
                    porta_ddr   <= porta_ddr;
288
                    porta_data  <= porta_data;
289
                         porta_ctrl  <= porta_ctrl;
290
                    portb_ddr   <= portb_ddr;
291
                    portb_data  <= portb_data;
292
                         portb_ctrl  <= portb_ctrl;
293
                         portb_write <= '0';
294
                end case;
295
         else
296
                    porta_ddr   <= porta_ddr;
297
                    porta_data  <= porta_data;
298
                         porta_ctrl  <= porta_ctrl;
299
                    portb_data  <= portb_data;
300
                    portb_ddr   <= portb_ddr;
301
                         portb_ctrl  <= portb_ctrl;
302
                         portb_write <= '0';
303
         end if;
304
  end if;
305
end process;
306
 
307
---------------------------------
308
--
309
-- CA1 Edge detect
310
--
311
---------------------------------
312
ca1_input : process( clk, rst, ca1, ca1_del,
313
                     ca1_rise, ca1_fall, ca1_edge,
314
                                                        irqa1, porta_ctrl, porta_read )
315
begin
316
  if rst = '1' then
317
    ca1_del  <= '0';
318
         ca1_rise <= '0';
319
    ca1_fall <= '0';
320
         ca1_edge <= '0';
321
         irqa1    <= '0';
322
  elsif clk'event and clk = '0' then
323
    ca1_del  <= ca1;
324
    ca1_rise <= (not ca1_del) and ca1;
325
    ca1_fall <= ca1_del and (not ca1);
326
         if ca1_edge = '1' then
327
            irqa1 <= '1';
328
         elsif porta_read = '1' then
329
            irqa1 <= '0';
330
    else
331
            irqa1 <= irqa1;
332
    end if;
333
  end if;
334
 
335
  if porta_ctrl(1) = '0' then
336
         ca1_edge <= ca1_fall;
337
  else
338
         ca1_edge <= ca1_rise;
339
  end if;
340
end process;
341
 
342
---------------------------------
343
--
344
-- CA2 Edge detect
345
--
346
---------------------------------
347
ca2_input : process( clk, rst, ca2, ca2_del,
348
                     ca2_rise, ca2_fall, ca2_edge,
349
                                                        irqa2, porta_ctrl, porta_read )
350
begin
351
  if rst = '1' then
352
    ca2_del  <= '0';
353
         ca2_rise <= '0';
354
    ca2_fall <= '0';
355
         ca2_edge <= '0';
356
         irqa2    <= '0';
357
  elsif clk'event and clk = '0' then
358
    ca2_del  <= ca2;
359
    ca2_rise <= (not ca2_del) and ca2;
360
    ca2_fall <= ca2_del and (not ca2);
361
         if porta_ctrl(5) = '0' and ca2_edge = '1' then
362
            irqa2 <= '1';
363
         elsif porta_read = '1' then
364
            irqa2 <= '0';
365
    else
366
            irqa2 <= irqa2;
367
    end if;
368
  end if;
369
 
370
  if porta_ctrl(4) = '0' then
371
         ca2_edge <= ca2_fall;
372
  else
373
         ca2_edge <= ca2_rise;
374
  end if;
375
end process;
376
 
377
---------------------------------
378
--
379
-- CA2 output control
380
--
381
---------------------------------
382
ca2_output : process( clk, rst, porta_ctrl, porta_read, ca1_edge, ca2_out )
383
begin
384
  if rst='1' then
385
    ca2_out <= '0';
386
  elsif clk'event and clk='0' then
387
    case porta_ctrl(5 downto 3) is
388
    when "100" => -- read PA clears, CA1 edge sets
389
      if porta_read = '1' then
390
             ca2_out <= '0';
391
      elsif ca1_edge = '1' then
392
             ca2_out <= '1';
393
      else
394
             ca2_out <= ca2_out;
395
      end if;
396
    when "101" => -- read PA clears, E sets
397
      ca2_out <= not porta_read;
398
    when "110" =>       -- set low
399
           ca2_out <= '0';
400
    when "111" =>       -- set high
401
           ca2_out <= '1';
402
    when others => -- no change
403
           ca2_out <= ca2_out;
404
    end case;
405
  end if;
406
end process;
407
 
408
 
409
---------------------------------
410
--
411
-- CB1 Edge detect
412
--
413
---------------------------------
414
cb1_input : process( clk, rst, cb1, cb1_del,
415
                     cb1_rise, cb1_fall, cb1_edge,
416
                                                        irqb1, portb_ctrl, portb_read )
417
begin
418
  if rst = '1' then
419
    cb1_del  <= '0';
420
         cb1_rise <= '0';
421
    cb1_fall <= '0';
422
         cb1_edge <= '0';
423
         irqb1    <= '0';
424
  elsif clk'event and clk = '0' then
425
    cb1_del  <= cb1;
426
    cb1_rise <= (not cb1_del) and cb1;
427
    cb1_fall <= cb1_del and (not cb1);
428
         if cb1_edge = '1' then
429
            irqb1 <= '1';
430
         elsif portb_read = '1' then
431
            irqb1 <= '0';
432
    else
433
            irqb1 <= irqb1;
434
    end if;
435
  end if;
436
 
437
  if portb_ctrl(1) = '0' then
438
         cb1_edge <= cb1_fall;
439
  else
440
         cb1_edge <= cb1_rise;
441
  end if;
442
end process;
443
 
444
---------------------------------
445
--
446
-- CB2 Edge detect
447
--
448
---------------------------------
449
cb2_input : process( clk, rst, cb2, cb2_del,
450
                     cb2_rise, cb2_fall, cb2_edge,
451
                                                        irqb2, portb_ctrl, portb_read )
452
begin
453
  if rst = '1' then
454
    cb2_del  <= '0';
455
         cb2_rise <= '0';
456
    cb2_fall <= '0';
457
         cb2_edge <= '0';
458
         irqb2    <= '0';
459
  elsif clk'event and clk = '0' then
460
    cb2_del  <= cb2;
461
    cb2_rise <= (not cb2_del) and cb2;
462
    cb2_fall <= cb2_del and (not cb2);
463
         if portb_ctrl(5) = '0' and cb2_edge = '1' then
464
            irqb2 <= '1';
465
         elsif portb_read = '1' then
466
            irqb2 <= '0';
467
    else
468
            irqb2 <= irqb2;
469
    end if;
470
  end if;
471
 
472
  if portb_ctrl(4) = '0' then
473
         cb2_edge <= cb2_fall;
474
  else
475
         cb2_edge <= cb2_rise;
476
  end if;
477
 
478
end process;
479
 
480
---------------------------------
481
--
482
-- CB2 output control
483
--
484
---------------------------------
485
cb2_output : process( clk, rst, portb_ctrl, portb_write, cb1_edge, cb2_out )
486
begin
487
  if rst='1' then
488
    cb2_out <= '0';
489
  elsif clk'event and clk='0' then
490
    case portb_ctrl(5 downto 3) is
491
    when "100" => -- write PB clears, CA1 edge sets
492
      if portb_write = '1' then
493
             cb2_out <= '0';
494
      elsif cb1_edge = '1' then
495
             cb2_out <= '1';
496
      else
497
             cb2_out <= cb2_out;
498
      end if;
499
    when "101" => -- write PB clears, E sets
500
      cb2_out <= not portb_write;
501
    when "110" =>       -- set low
502
           cb2_out <= '0';
503
    when "111" =>       -- set high
504
           cb2_out <= '1';
505
    when others => -- no change
506
           cb2_out <= cb2_out;
507
    end case;
508
  end if;
509
end process;
510
 
511
---------------------------------
512
--
513
-- IRQ control
514
--
515
---------------------------------
516
pia_irq : process( irqa1, irqa2, irqb1, irqb2, porta_ctrl, portb_ctrl )
517
begin
518
  irqa <= (irqa1 and porta_ctrl(0)) or (irqa2 and porta_ctrl(3));
519
  irqb <= (irqb1 and portb_ctrl(0)) or (irqb2 and portb_ctrl(3));
520
end process;
521
 
522
---------------------------------
523
--
524
-- 2 x 74193 binary down counter
525
--
526
---------------------------------
527
--
528
-- On the reference 6809 board, 
529
-- RTI takes one more clock cycle than System09
530
-- So subtract 1 from the porta_data preset value.
531
-- 11th July 2006 John Kent
532
-- RTI in CPU09 has been extended by one bus cycle
533
-- so remove the subtract by one offset on porta_data
534
--
535
pia_counter : process( clk, timer, porta_data, ca2_out, cb2_out)
536
begin
537
  if cb2_out = '1' then
538
    timer <= "00000000";
539
  elsif ca2_out = '0' then
540
--    timer <= porta_data - "00000001";
541
    timer <= porta_data;
542
  elsif clk'event and clk='1' then
543
    timer <= timer - "00000001";
544
  end if;
545
  pa  <= "00000000";
546
  pb  <= timer;
547
  ca1 <= timer(7);
548
  cb1 <= timer(7);
549
  ca2 <= '0';
550
  cb2 <= '0';
551
end process;
552
 
553
end pia_arch;
554
 

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