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[/] [System09/] [trunk/] [rtl/] [VHDL/] [priority_rot.vhd] - Blame information for rev 152

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Line No. Rev Author Line
1 100 davidgb
--===========================================================================--
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--                                                                           --
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--  priority_rot.vhd - Synthesizable Rotating Priority Encoder               --
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--                                                                           --
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--===========================================================================--
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--
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--  File name      : priority_rot.vhd
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--
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--  Purpose        : Implements a rotating priority encoder
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--                  
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--  Dependencies   : ieee.std_logic_1164
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--                   ieee.std_logic_unsigned
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--                   ieee.std_logic_arith
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--                   unisim.vcomponents
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--
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--  Author         : John E. Kent
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--
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--  Email          : dilbert57@opencores.org      
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--
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--  Web            : http://opencores.org/project,system09
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--
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--  Priority_rot.vhd is a rotating priority encoder written in VHDL.
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-- 
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--  Copyright (C) 2010 John Kent
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--
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--  This program is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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--                                                                           --
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--                              Revision  History                            --
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--                                                                           --
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--===========================================================================--
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--
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-- Version  Author        Date               Description
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-- 0.1      John Kent     30th May 2010      Initial version
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--
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library ieee;
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  use ieee.std_logic_1164.all;
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  use ieee.std_logic_unsigned.all;
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  use ieee.std_logic_arith.all;
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library unisim;
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  use unisim.vcomponents.all;
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entity priority_rot is
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   generic (
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      WIDTH = 8
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   )
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        port (
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                clk      : in  std_logic;
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                rst      : in  std_logic;
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           input    : in  std_logic_vector(WIDTH-1 downto 0);
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           output   : out std_logic_vector(log2(WIDTH)-1 downto 0);
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      valid    : out std_logic
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   )
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                );
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end priority_rot;
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architecture rtl of priority_rot is
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constant OUT_WIDTH : integer := log2(WIDTH);
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begin
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  for i in 1 to WIDTH loop
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    j := log2( i );
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    if( input(i-1) = '1' ) then
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  end loop;
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end architecture;
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