OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [VHDL/] [spp.vhd] - Blame information for rev 176

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 99 davidgb
--===========================================================================--
2
--                                                                           --
3
--              Synthesizable Simple Parallel Port                           --
4
--                                                                           --
5
--===========================================================================--
6
--
7
--  File name      : spp.vhd
8
--
9
--  Entity name    : spp
10
--
11
--  Purpose        : implements a Simple Parallel Port for System09
12
--
13
--  Dependencies   : ieee.Std_Logic_1164
14
--                   ieee.std_logic_unsigned
15
--
16
--  Uses           : None
17
--
18
--  Author         : John E. Kent      
19
--
20
--  Email          : dilbert57@opencores.org      
21
--
22
--  Web            : http://opencores.org/project,system09
23
--
24
--  Description    : Register Memory Map
25
--
26
--  Address                                MSB                         LSB
27
--                                    Bit:   7   6   5   4   3   2   1   0
28
--  Base+$00 (SPP Data port)    Write Pin:   9   8   7   6   5   4   3   2
29
--  Base+$01 (SPP Status port)  Read  Pin: ~11  10  12  13  15   -   -   -                      
30
--  Base+$02 (SPP Control port) Write Pin:   -   -   -   - ~17  16 ~14  ~1
31
--  Base+$03 (EPP Address port) R/W
32
--  Base+$04 (EPP Data port)    R/W
33
-- 
34
--  ~ indicates a hardware inversion of the bit.
35
--  Parallel printer port pin assignment
36
-- 
37
--  Pin No (DB25) SPP Signal      EPP Signal    Direction Register  Bit Inverted
38
--  1             nStrobe         Write_n       Out       Control-0 Yes
39
--  2             Data0           Data0         In/Out    Data-0          No
40
--  3             Data1           Data1         In/Out    Data-1          No
41
--  4             Data2           Data2         In/Out    Data-2          No
42
--  5             Data3           Data3         In/Out    Data-3          No
43
--  6             Data4           Data4         In/Out    Data-4          No
44
--  7             Data5           Data5         In/Out    Data-5          No
45
--  8             Data6           Data6         In/Out    Data-6          No
46
--  9             Data7           Data7         In/Out    Data-7          No
47
--  10            nAck            Interrupt     In        Status-6  No
48
--  11            Busy            Wait          In        Status-7  Yes
49
--  12            Paper-Out       Spare         In        Status-5  No
50
--  13            Select          Spare         In        Status-4  No
51
--  14            Linefeed        Data_Strobe_n Out       Control-1 Yes
52
--  15            nError          Spare         In        Status-3  No
53
--  16            nInitialize     Reset         Out       Control-2 No
54
--  17            nSelect-Printer Addr_Strobe_n Out       Control-3 Yes
55
--  18-25         Ground          Ground        -         -         -
56
-- 
57
--  Copyright (C) 2008 - 2010 John Kent
58
--
59
--  This program is free software: you can redistribute it and/or modify
60
--  it under the terms of the GNU General Public License as published by
61
--  the Free Software Foundation, either version 3 of the License, or
62
--  (at your option) any later version.
63
--
64
--  This program is distributed in the hope that it will be useful,
65
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
66
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
67
--  GNU General Public License for more details.
68
--
69
--  You should have received a copy of the GNU General Public License
70
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
71
--
72
--===========================================================================--
73
--                                                                           --
74
--                    Revision History                                       --
75
--                                                                           --
76
--===========================================================================--
77
--
78
-- Version  Date       Author      Description
79
-- 0.1      2008-09-06 John Kent   Initial version generated from ioport.vhd
80
-- 0.2      2010-08-09 John Kent   Updated Header and added GPL
81
--
82
--===========================================================================
83
 
84
library ieee;
85
  use ieee.std_logic_1164.all;
86
  use ieee.std_logic_unsigned.all;
87
 
88
entity spp is
89
        port (
90
         clk       : in  std_logic;
91
    rst       : in  std_logic;
92
    cs        : in  std_logic;
93
    rw        : in  std_logic;
94
    addr      : in  std_logic_vector(2 downto 0);
95
    data_in   : in  std_logic_vector(7 downto 0);
96
         data_out  : out std_logic_vector(7 downto 0);
97
         spp_data  : out std_logic_vector(7 downto 0);
98
         spp_stat  : in  std_logic_vector(7 downto 3);
99
         spp_ctrl  : out std_logic_vector(3 downto 0);
100
         hold      : out std_logic;
101
    irq       : out std_logic
102
         );
103
end;
104
 
105
architecture rtl of spp is
106
 
107
signal spp_data_reg : std_logic_vector(7 downto 0);
108
signal spp_stat_reg : std_logic_vector(7 downto 3);
109
signal spp_ctrl_reg : std_logic_vector(3 downto 0);
110
 
111
begin
112
 
113
 
114
--------------------------------
115
--
116
-- read I/O port
117
--
118
--------------------------------
119
 
120
spp_read : process( addr,
121
                    spp_data_reg, spp_stat_reg, spp_ctrl_reg,
122
                                                  spp_stat )
123
begin
124
      spp_stat_reg(6 downto 3) <=     spp_stat(6 downto 3);
125
      spp_stat_reg(7)          <= not spp_stat(7);
126
      case addr is
127
             when "000" =>
128
          data_out <= spp_data_reg;
129
 
130
                  when "001" =>
131
          data_out <= spp_stat_reg & "000";
132
 
133
             when "010" =>
134
                    data_out <= "0000" & spp_ctrl_reg;
135
 
136
                  when others =>
137
                    data_out <= (others=> '0');
138
                end case;
139
      hold <= '0';
140
                irq  <= '0';
141
end process;
142
 
143
---------------------------------
144
--
145
-- Write I/O ports
146
--
147
---------------------------------
148
 
149
spp_write : process( clk, rst, addr, cs, rw, data_in,
150
                     spp_data_reg, spp_ctrl_reg )
151
begin
152
  if clk'event and clk = '0' then
153
    if rst = '1' then
154
      spp_data_reg <= "00000000";
155
      spp_ctrl_reg <= "0000";
156
    elsif cs = '1' and rw = '0' then
157
      case addr is
158
             when "000" =>
159
                    spp_data_reg <= data_in;
160
                  when "010" =>
161
                    spp_ctrl_reg <= data_in(3 downto 0);
162
                  when others =>
163
                    null;
164
                end case;
165
         end if;
166
  end if;
167
  spp_data    <=     spp_data_reg;
168
  spp_ctrl(0) <= not spp_ctrl_reg(0);
169
  spp_ctrl(1) <= not spp_ctrl_reg(1);
170
  spp_ctrl(2) <=     spp_ctrl_reg(2);
171
  spp_ctrl(3) <= not spp_ctrl_reg(3);
172
end process;
173
 
174
end rtl;
175
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.