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[/] [System09/] [trunk/] [rtl/] [VHDL/] [vdu8_hdmi.vhd] - Blame information for rev 214

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1 211 davidgb
--===========================================================================--
2
--                                                                           --
3
--  vdu8.vhd - Synthesizable Colour Video Display Unit for System09          --
4
--                                                                           --
5
--===========================================================================--
6
--
7
--  File name      : vdu8.vhd
8
--
9
--  Purpose        : Implements a text based Colour Video Display Unit for System09
10
--                   Supports 2KByte Text buffer and 2KByte Attribute memory
11
--                   Displays 80 characters across by 25 character rows
12
--                   Characters are 8 pixels across x 16 lines down.
13
--                   Character attribute bita for foreground and backgrond colour
14
--                   1 bit for each Blue Green and Red signal
15
--                   Supports 2 x 8 chunky graphics character mode.
16
--                   Uses Generic arguments for setting the video synchronization timing.
17
--                  
18
--  Dependencies   : ieee.std_logic_1164
19
--                   ieee.numeric_std
20
--
21
--  Uses           : ram_2k (ram2k_b16.vhd)             2KByte Character & Attribute buffer
22
--                   char_rom (char_rom2k_b16.vhd)      2KByte Character Generator ROM 
23
--
24
--  Author         : John E. Kent
25
--
26
--  Email          : dilbert57@opencores.org      
27
--
28
--  Web            : http://opencores.org/project,system09
29
--
30
--  Description    : Display Timing:
31
--                       800 pixels / line
32
--                       446 lines / frame
33
--                       None interlaced
34
--                       25MHz pixel clock implies 
35
--                       31.25 KHz line rate
36
--                       70.067 Hz frame rate   
37
--                       Timing settable by generics.
38
--
39
--                   Display Size:
40
--                       80 characters across
41
--                       25 characters down.
42
--
43
--                   Character Size:
44
--                        8 horizontal pixels across
45
--                       16 vertical scan lines down (2 scan lines/row)
46
--
47
--                   Registers:
48
--                   Base + 0 ASCII character register
49
--                            Writing to this register writes an 8 bit byte 
50
--                            into the text buffer at the specified cursor position
51
--                            Text Mode: ASCII Character (0 to 127)
52
--                            Chunky Graphics Mode: B0 B1 (0 to 255)
53
--                                                  B2 B3
54
--                                                  B4 B5
55
--                                                  B6 B7
56
--                   Base + 1 Attibute bit (0 to 255)
57
--                            Writing to the register writes an 8 bit byte 
58
--                            into the attribute buffer at the specified cursor position
59
--                            B7 - 0 => Text Mode / 1 => Chunky Graphics Mode
60
--                            B6 - 1 => Character Background Blue
61
--                            B5 - 1 => Character Background Green
62
--                            B4 - 1 => Character Background Red
63
--                            B3 - 1 => Character Background & Foreground Alternates
64
--                            B2 - 1 => Character Foreground Blue
65
--                            B1 - 1 => Character Foreground Green
66
--                            B0 - 1 => Character Foreground Red
67
--                   Base + 2 Cursor Horizontal Position (0 to 79)
68
--                   Base + 3 Cusror Vertical Position (0 to 24)
69
--                   Base + 4 Vertical Scroll Offset (0 to 24)
70
--                            Scrolls the display up by the specified number of character rows
71
--
72
--  Video Timing :
73
--
74
--  Horizontal 800 Pixels/ 25MHz Pixel Clock = 32usec Line period = 31.25 KHz Line Frequency
75
--  /--------------------------\_____________/---------------\______________/
76
--      640 Pixels Display       16 Pixel FP    96 Pixel HS     48 Pixel BP
77
--    
78
--      VGA_CLK_FREQ           : integer := 25000000; -- HZ
79
--           VGA_HOR_FRONT_PORCH    : integer := 16; -- PIXELS 0.64us (0.94us)
80
--           VGA_HOR_SYNC           : integer := 96; -- PIXELS 3.84us (3.77us)
81
--           VGA_HOR_BACK_PORCH     : integer := 48; -- PIXELS 1.92us (1.89us)
82
--           VGA_PIX_PER_CHAR       : integer := 8;  -- PIXELS 0.32us
83
--           VGA_HOR_CHARS          : integer := 80; -- CHARACTERS 25.6us
84
--
85
--  Vertical 446 Lines * 32 usec Line rate = 14.272ms Frame Period = 70.07Hz Frame frequency  
86
--  /---------------------------\____________/---------------\______________/
87
--      400 Line Display          10 Line FP     2 Line VS      34 Line BP
88
--
89
--           VGA_VER_FRONT_PORCH    : integer := 10; -- LINES 0.320ms
90
--           VGA_VER_SYNC           : integer := 2;  -- LINES 0.064ms
91
--           VGA_VER_BACK_PORCH     : integer := 34; -- LINES 1.088ms
92
--           VGA_LIN_PER_CHAR       : integer := 16; -- LINES 0.512ms
93
--           VGA_VER_CHARS          : integer := 25; -- CHARACTERS 12.8ms
94
--
95
--  Copyright (C) 2003 - 2010 John Kent
96
--
97
--  This program is free software: you can redistribute it and/or modify
98
--  it under the terms of the GNU General Public License as published by
99
--  the Free Software Foundation, either version 3 of the License, or
100
--  (at your option) any later version.
101
--
102
--  This program is distributed in the hope that it will be useful,
103
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
104
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
105
--  GNU General Public License for more details.
106
--
107
--  You should have received a copy of the GNU General Public License
108
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
109
--
110
--===========================================================================--
111
--                                                                           --
112
--                              Revision  History                            --
113
--                                                                           --
114
--===========================================================================--
115
--
116
-- Version Author      Date        Changes
117
--
118
-- 0.1     John Kent   2004-09-03  Initial release
119
--
120
-- 0.2     Bert Cuzeau 2007-01-16  Modified by for compliance and code cleanliness
121
--                                 The effort is not over.
122
--                                 There are still signal initialized, which is BAD.
123
--
124
-- 0.3     John Kent   2007-02-07  Added generics for VGA Timing
125
--
126
-- 0.4     John Kent   2010-07-03  Added GPL notice. 
127
--                                 Updated description.
128
--                                 Rearranged Video Timing
129
-- 
130
-- 0.5     David Burnette 2021-04-05  Removed VGA signalling and added HDMI support (640x480 only)
131
--                                    Still needs work to refactor the clock signals - ideally this would
132
--                                    be a generic VDU that had vendor-specific modules (i.e. clock generators
133
--                                    and serializers) in a separate file.
134
--                                    HDMI support is via code fragments from fpga4fun.com and
135
--                                    can be found in Verilog/rgb2hdmi_encoder.v.
136
 
137
Library IEEE;
138
  use IEEE.std_logic_1164.all;
139
  use IEEE.numeric_std.all;
140
--Library unisim;
141
--  use unisim.vcomponents.all;
142
 
143
Entity vdu8_hdmi is
144
  generic(
145
      VDU_CLK_FREQ           : integer := 25000000; -- HZ
146
        VGA_CLK_FREQ           : integer := 25000000; -- HZ
147
             VGA_HOR_CHARS          : integer := 80; -- CHARACTERS 25.6us
148
             VGA_HOR_CHAR_PIXELS    : integer := 8;  -- PIXELS 0.32us
149
             VGA_HOR_FRONT_PORCH    : integer := 16; -- PIXELS 0.64us
150
             VGA_HOR_SYNC           : integer := 96; -- PIXELS 3.84us
151
             VGA_HOR_BACK_PORCH     : integer := 48; -- PIXELS 1.92us
152
             VGA_VER_CHARS          : integer := 25; -- CHARACTERS 12.8ms
153
             VGA_VER_CHAR_LINES     : integer := 16; -- LINES 0.512ms
154
             VGA_VER_FRONT_PORCH    : integer := 10; -- LINES 0.320ms
155
             VGA_VER_SYNC           : integer := 2;  -- LINES 0.064ms
156
             VGA_VER_BACK_PORCH     : integer := 34  -- LINES 1.088ms
157
  );
158
  port(
159
    -- control register interface
160
    vdu_clk      : in  std_logic;       -- 12.5/25 MHz CPU Clock
161
    vdu_rst      : in  std_logic;
162
    vdu_cs       : in  std_logic;
163
    vdu_rw       : in  std_logic;
164
    vdu_addr     : in  std_logic_vector(2 downto 0);
165
    vdu_data_in  : in  std_logic_vector(7 downto 0);
166
    vdu_data_out : out std_logic_vector(7 downto 0);
167
    -- HDMI TMDS outputs
168
         hdmi_clk     : in std_logic; -- 25MHz 
169
    TMDSp_clock  : out std_logic;
170
    TMDSn_clock  : out std_logic;
171
    TMDSp        : out std_logic_vector(2 downto 0);
172
    TMDSn        : out std_logic_vector(2 downto 0)
173
    );
174
end vdu8_hdmi;
175
 
176
Architecture RTL of vdu8_hdmi is
177
  --
178
  -- Synchronisation constants
179
  --
180
  -- Displayed Characters per row
181
  constant HOR_DISP_CHR : integer := VGA_HOR_CHARS;
182
  -- Last horizontal pixel displayed
183
  constant HOR_DISP_END : integer := (HOR_DISP_CHR * VGA_HOR_CHAR_PIXELS) - 1;
184
  -- Start of horizontal synch pulse
185
  constant HOR_SYNC_BEG : integer := HOR_DISP_END + VGA_HOR_FRONT_PORCH;
186
  -- End of Horizontal Synch pulse
187
  constant HOR_SYNC_END : integer := HOR_SYNC_BEG + VGA_HOR_SYNC;
188
  -- Last pixel in scan line
189
  constant HOR_SCAN_END : integer := HOR_SYNC_END + VGA_HOR_BACK_PORCH;
190
 
191
  -- Displayed Characters per Column
192
  constant VER_DISP_CHR : integer := VGA_VER_CHARS;
193
  -- last row displayed
194
  constant VER_DISP_END : integer := (VER_DISP_CHR * VGA_VER_CHAR_LINES) - 1;
195
  -- start of vertical synch pulse
196
  constant VER_SYNC_BEG : integer := VER_DISP_END + VGA_VER_FRONT_PORCH;
197
  -- end of vertical synch pulse
198
  constant VER_SYNC_END : integer := VER_SYNC_BEG + VGA_VER_SYNC;
199
  -- Last scan row in the frame
200
  constant VER_SCAN_END : integer := VER_SYNC_END + VGA_VER_BACK_PORCH;
201
 
202
  signal horiz_sync    : std_logic := '1';
203
  signal vert_sync     : std_logic := '1';
204
  signal cursor_on_v   : std_logic;
205
  signal cursor_on_h   : std_logic;
206
  signal video_on_v    : std_logic := '0';
207
  signal video_on_h    : std_logic := '0';
208
  signal h_count       : std_logic_vector(9 downto 0) := (others=>'0');
209
  signal v_count       : std_logic_vector(8 downto 0) := (others=>'0');  -- 0 to VER_SCAN_END
210
  signal blink_count   : std_logic_vector(22 downto 0):= (others=>'1');
211
  --
212
  -- Character generator ROM
213
  --
214
  signal char_addr     : std_logic_vector(10 downto 0);
215
  signal char_data_out : std_logic_vector(7 downto 0);
216
 
217
  --
218
  -- Control Registers
219
  --
220
  signal reg_character : std_logic_vector(7 downto 0);
221
  signal reg_colour    : std_logic_vector(7 downto 0);
222
  signal reg_hcursor   : std_logic_vector(6 downto 0);   -- 80 columns
223
  signal reg_vcursor   : std_logic_vector(4 downto 0);   -- 25 rows
224
  signal reg_voffset   : std_logic_vector(4 downto 0);   -- 25 rows
225
  --
226
  -- Video Shift register
227
  --
228
  signal vga_shift     : std_logic_vector(7 downto 0);
229
  signal vga_fg_colour : std_logic_vector(2 downto 0);
230
  signal vga_bg_colour : std_logic_vector(2 downto 0);
231
  signal cursor_on     : std_logic;
232
  signal cursor_on1    : std_logic;
233
  signal video_on      : std_logic := '0';
234
  signal video_on1     : std_logic := '0';
235
  signal video_on2     : std_logic := '0';
236
 
237
  signal vga_red       : std_logic; -- RGB VGA signal (single bit for now)
238
  signal vga_green     : std_logic;
239
  signal vga_blue      : std_logic;
240
 
241
  signal HDMI_red      : std_logic_vector(7 downto 0); -- HDMI signalling
242
  signal HDMI_green    : std_logic_vector(7 downto 0);
243
  signal HDMI_blue     : std_logic_vector(7 downto 0);
244
 
245
  --
246
  -- vga character ram access bus
247
  --
248
  signal col_addr      : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 79
249
  signal row_addr      : unsigned(5 downto 0)         := (others=>'0'); -- 0 to 49 (25 * 2 -1)
250
  signal col1_addr     : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 79
251
  signal row1_addr     : unsigned(5 downto 0)         := (others=>'0'); -- 0 to 49 (25 * 2 - 1)
252
  signal hor_addr      : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 79
253
  signal ver_addr      : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 124
254
  signal vga0_cs       : std_logic;
255
  signal vga0_rw       : std_logic;
256
  signal vga1_cs       : std_logic;
257
  signal vga1_rw       : std_logic;
258
  signal vga2_cs       : std_logic;
259
  signal vga2_rw       : std_logic;
260
  signal vga_cs        : std_logic;
261
  signal vga_rw        : std_logic;
262
  signal vga_addr      : std_logic_vector(10 downto 0) := (others=>'0');  -- 2K byte character buffer
263
  signal vga_data_out  : std_logic_vector(7 downto 0);
264
  signal attr_data_out : std_logic_vector(7 downto 0);
265
  --
266
  -- Character write handshake signals
267
  --
268
  signal req_write     : std_logic;     -- request character write
269
  signal ack_write     : std_logic;
270
 
271
  --
272
  -- Block Ram Character gen
273
  --
274
  component char_rom
275
    port (
276
      clk      : in  std_logic;
277
      rst      : in  std_logic;
278
      cs       : in  std_logic;
279
      rw       : in  std_logic;
280
      addr     : in  std_logic_vector (10 downto 0);
281
      data_in  : in std_logic_vector (7 downto 0);
282
      data_out : out std_logic_vector (7 downto 0)
283
      );
284
  end component;
285
 
286 214 davidgb
  component block_spram
287
    generic (
288
      dwidth : integer := 8;     -- parameterized data width
289
           awidth : integer := 16     -- parameterized address width
290
         );
291
         port (
292
      clk         : in std_logic;
293
           cs          : in std_logic; -- chip-select/enable
294
           addr        : in std_logic_vector(awidth-1 downto 0);
295
           rw          : in std_logic;
296
           data_in     : in std_logic_vector(dwidth-1 downto 0);
297
           data_out    : out std_logic_vector(dwidth-1 downto 0)
298
         );
299 211 davidgb
  end component;
300
 
301
component RGB2HDMI_encoder
302
  port (
303
    pixclk      : in std_logic; -- 25 MHz
304
         vSync       : in std_logic;
305
         hSync       : in std_logic;
306
         DrawArea    : in std_logic;
307
         red         : in std_logic_vector(7 downto 0);
308
         green       : in std_logic_vector(7 downto 0);
309
         blue        : in std_logic_vector(7 downto 0);
310
         TMDSp       : out std_logic_vector(2 downto 0);
311
         TMDSn       : out std_logic_vector(2 downto 0);
312
         TMDSp_clock : out std_logic;
313
         TMDSn_clock : out std_logic
314
  );
315
  end component;
316
 
317
begin
318
 
319
--
320
-- instantiate Character generator ROM
321
--
322
vdu_char_rom : char_rom port map(
323
        clk      => hdmi_clk,
324
        rst      => vdu_rst,
325
        cs       => '1',
326
        rw       => '1',
327
        addr     => char_addr,
328
        data_in  => "00000000",
329
        data_out => char_data_out
330
    );
331
 
332
--
333
-- Character buffer RAM
334
--
335 214 davidgb
char_buff_ram : block_spram
336
  generic map( dwidth => 8, awidth => 11) -- 2k bytes
337
  port map(
338 211 davidgb
    clk      => hdmi_clk,
339
    cs       => vga_cs,
340
    rw       => vga_rw,
341
    addr     => vga_addr,
342
    data_in  => reg_character,
343
    data_out => vga_data_out
344
    );
345
 
346 214 davidgb
 
347 211 davidgb
--
348
-- Attribute buffer RAM
349
--
350 214 davidgb
attr_buff_ram : block_spram
351
  generic map( dwidth => 8, awidth => 11) -- 2k bytes
352
  port map(
353 211 davidgb
    clk      => hdmi_clk,
354
    cs       => vga_cs,
355
    rw       => vga_rw,
356
    addr     => vga_addr,
357
    data_in  => reg_colour,
358
    data_out => attr_data_out
359
    );
360
 
361
--
362
-- CPU Write interface
363
--
364
  vga_cpu_write : process(vdu_clk, vdu_rst)
365
  begin
366
    if vdu_rst = '1' then
367
      reg_character <= "00000000";
368
      reg_colour    <= "00000111";
369
      reg_hcursor   <= "0000000";
370
      reg_vcursor   <= "00000";
371
      reg_voffset   <= "00000";
372
      req_write     <= '0';
373
 
374
    elsif vdu_clk'event and vdu_clk = '0' then
375
      if (vdu_cs = '1') and (vdu_rw = '0') then
376
        case vdu_addr is
377
          when "000" =>
378
            reg_character <= vdu_data_in;
379
            req_write     <= '1';
380
          when "001" =>
381
            reg_colour    <= vdu_data_in;
382
          when "010" =>
383
            reg_hcursor   <= vdu_data_in(6 downto 0);
384
          when "011" =>
385
            reg_vcursor   <= vdu_data_in(4 downto 0);
386
          when others =>
387
            reg_voffset   <= vdu_data_in(4 downto 0);
388
        end case;
389
      else
390
 
391
        if (req_write = '1') and (ack_write = '1') then
392
          req_write <= '0';
393
        else
394
          req_write <= req_write;
395
        end if;
396
 
397
      end if;
398
    end if;
399
  end process;
400
--
401
-- CPU Read interface
402
--
403
  vga_cpu_read : process(vdu_addr, vdu_cs,
404
                          reg_character, reg_colour,
405
                          reg_hcursor, reg_vcursor, reg_voffset)
406
  begin
407
    case vdu_addr is
408
      when "000" =>
409
        vdu_data_out <= reg_character;
410
      when "001" =>
411
        vdu_data_out <= reg_colour;
412
      when "010" =>
413
        vdu_data_out <= "0" & reg_hcursor;
414
      when "011" =>
415
        vdu_data_out <= "000" & reg_vcursor;
416
      when others =>
417
        vdu_data_out <= "000" & reg_voffset;
418
    end case;
419
  end process;
420
 
421
--
422
-- Video memory access
423
--
424
  vga_addr_proc : process(hdmi_clk, vdu_rst)
425
  begin
426
 
427
    if vdu_rst = '1' then
428
      vga0_cs   <= '0';
429
      vga0_rw   <= '1';
430
      row_addr  <= "000000";
431
      col_addr  <= "0000000";
432
      --
433
      vga1_cs   <= '0';
434
      vga1_rw   <= '1';
435
      row1_addr <= "000000";
436
      col1_addr <= "0000000";
437
      --
438
      vga2_cs   <= '0';
439
      vga2_rw   <= '1';
440
      ver_addr  <= "0000000";
441
      hor_addr  <= "0000000";
442
      --
443
      vga_cs    <= '0';
444
      vga_rw    <= '1';
445
      vga_addr  <= "00000000000";
446
 
447
    elsif hdmi_clk'event and hdmi_clk = '0' then
448
      --
449
      -- on h_count = 0 initiate character write.
450
      -- all other cycles are reads.
451
      --
452
      case h_count(2 downto 0) is
453
        when "000" =>                   -- pipeline character write
454
          vga0_cs  <= req_write;
455
          vga0_rw  <= '0';
456
          col_addr <= reg_hcursor(6 downto 0);
457
          row_addr <= unsigned("0" & reg_vcursor(4 downto 0)) + unsigned("0" & reg_voffset(4 downto 0));
458
        when others =>                  -- other 6 cycles free
459
          vga0_cs  <= '1';
460
          vga0_rw  <= '1';
461
          col_addr <= h_count(9 downto 3);
462
          row_addr <= unsigned("0" & v_count(8 downto 4)) + unsigned("0" & reg_voffset(4 downto 0));
463
      end case;
464
      --
465
      -- on hdmi_clk + 1 round off row address
466
      --
467
      vga1_cs <= vga0_cs;
468
      vga1_rw <= vga0_rw;
469
      if row_addr < VER_DISP_CHR then
470
        row1_addr <= row_addr;
471
      else
472
        row1_addr <= row_addr - VER_DISP_CHR;
473
      end if;
474
      col1_addr <= col_addr;
475
      --
476
      -- on hdmi_clk + 2 calculate vertical address
477
      --
478
      vga2_cs   <= vga1_cs;
479
      vga2_rw   <= vga1_rw;
480
      ver_addr  <= std_logic_vector(unsigned("00" & row1_addr(4 downto 0)) + unsigned(row1_addr(4 downto 0) & "00"));
481
      hor_addr  <= col1_addr;
482
      --
483
      -- on hdmi_clk + 3 calculate memory address
484
      --
485
      vga_cs    <= vga2_cs;
486
      vga_rw    <= vga2_rw;
487
      vga_addr  <= std_logic_vector(unsigned("0000" & hor_addr) + unsigned(ver_addr & "0000"));
488
    end if;
489
  end process;
490
--
491
-- Video shift register
492
--
493
  vga_shift_proc : process( hdmi_clk, vdu_rst)
494
  begin
495
    if vdu_rst = '1' then
496
      ack_write     <= '0';
497
      video_on2     <= '0';
498
      video_on      <= '0';
499
      cursor_on     <= '0';
500
      vga_bg_colour <= "000";
501
      vga_fg_colour <= "111";
502
      vga_shift     <= "00000000";
503
      vga_red     <= '0';
504
      vga_green   <= '0';
505
      vga_blue    <= '0';
506
      -- Put all video signals through DFFs to elminate any delays that cause a blurry image
507
 
508
    elsif hdmi_clk'event and hdmi_clk = '0' then
509
      -- Character Data valid on 1 count
510
      if h_count(2 downto 0) = "000" then
511
        if (req_write = '1') and (ack_write = '0') then
512
          ack_write <= '1';
513
        elsif (req_write = '0') and (ack_write = '1') then
514
          ack_write <= '0';
515
        else
516
          ack_write <= ack_write;
517
        end if;
518
        video_on2     <= video_on1;
519
        video_on      <= video_on2;
520
        cursor_on     <= (cursor_on1 or attr_data_out(3)) and blink_count(22);
521
        vga_fg_colour <= attr_data_out(2 downto 0);
522
        vga_bg_colour <= attr_data_out(6 downto 4);
523
        if attr_data_out(7) = '0' then
524
          vga_shift <= char_data_out;
525
        else
526
          case v_count(3 downto 2) is
527
            when "00" =>
528
              vga_shift(7 downto 4) <= vga_data_out(0) & vga_data_out(0) & vga_data_out(0) & vga_data_out(0);
529
              vga_shift(3 downto 0) <= vga_data_out(1) & vga_data_out(1) & vga_data_out(1) & vga_data_out(1);
530
            when "01" =>
531
              vga_shift(7 downto 4) <= vga_data_out(2) & vga_data_out(2) & vga_data_out(2) & vga_data_out(2);
532
              vga_shift(3 downto 0) <= vga_data_out(3) & vga_data_out(3) & vga_data_out(3) & vga_data_out(3);
533
            when "10" =>
534
              vga_shift(7 downto 4) <= vga_data_out(4) & vga_data_out(4) & vga_data_out(4) & vga_data_out(4);
535
              vga_shift(3 downto 0) <= vga_data_out(5) & vga_data_out(5) & vga_data_out(5) & vga_data_out(5);
536
            when others =>
537
              vga_shift(7 downto 4) <= vga_data_out(6) & vga_data_out(6) & vga_data_out(6) & vga_data_out(6);
538
              vga_shift(3 downto 0) <= vga_data_out(7) & vga_data_out(7) & vga_data_out(7) & vga_data_out(7);
539
          end case;
540
        end if;
541
      else
542
        vga_shift <= vga_shift(6 downto 0) & '0';
543
      end if;
544
 
545
      --
546
      -- Colour mask is
547
      --  7  6  5  4  3  2  1  0
548
      --  X BG BB BR  X FG FB FR
549
      --
550
      if vga_shift(7) = (not cursor_on) then
551
        vga_red   <= video_on and vga_fg_colour(0);
552
        vga_green <= video_on and vga_fg_colour(1);
553
        vga_blue  <= video_on and vga_fg_colour(2);
554
      else
555
        vga_red   <= video_on and vga_bg_colour(0);
556
        vga_green <= video_on and vga_bg_colour(1);
557
        vga_blue  <= video_on and vga_bg_colour(2);
558
      end if;
559
    end if;
560
  end process;
561
 
562
--
563
-- Sync generator & timing process
564
-- Generate Horizontal and Vertical Timing Signals for Video Signal
565
--
566
  vga_sync : process(hdmi_clk)
567
  begin
568
    if hdmi_clk'event and hdmi_clk = '0' then
569
      --
570
      -- H_count counts pixels (640 + extra time for sync signals)
571
      --
572
      --  Horiz_sync  -----------------------------__________--------
573
      --  H_count       0                640      659       755    799
574
      --
575
      if unsigned(h_count) = HOR_SCAN_END then
576
        h_count <= (others=>'0');
577
      else
578
        h_count <= std_logic_vector(unsigned(h_count) + 1);
579
      end if;
580
--
581
-- Generate Horizontal Sync Signal using H_count
582
--
583
      if unsigned(h_count) = HOR_SYNC_BEG then
584
        horiz_sync <= '0';
585
      elsif unsigned(h_count) = HOR_SYNC_END then
586
        horiz_sync <= '1';
587
      else
588
        horiz_sync <= horiz_sync;
589
      end if;
590
--
591
-- V_count counts rows of pixels
592
-- 400 lines + extra time for sync signals
593
-- 25 rows * 16 scan lines
594
--
595
--  Vert_sync      ---------------------------------_______------------
596
--  V_count         0                       400    413     414        444
597
--
598
      if (unsigned(v_count) = VER_SCAN_END) and (unsigned(h_count) = HOR_SCAN_END) then
599
        v_count <= "000000000";
600
      elsif unsigned(h_count) = HOR_SYNC_END then
601
        v_count <= std_logic_vector(unsigned(v_count) + 1);
602
      end if;
603
--
604
-- Generate Vertical Sync Signal using V_count
605
--
606
      if unsigned(v_count) = VER_SYNC_BEG then
607
        vert_sync <= '0';
608
      elsif unsigned(v_count) = VER_SYNC_END then
609
        vert_sync <= '1';
610
      else
611
        vert_sync <= vert_sync;
612
      end if;
613
 
614
-- Generate Video on Screen Signals for Pixel Data
615
      if unsigned(h_count) = HOR_SCAN_END then
616
        video_on_h <= '1';
617
      elsif unsigned(h_count) = HOR_DISP_END then
618
        video_on_h <= '0';
619
      else
620
        video_on_h <= video_on_h;
621
      end if;
622
 
623
      if unsigned(v_count) = VER_SCAN_END then
624
        video_on_v <= '1';
625
      elsif unsigned(v_count) = VER_DISP_END then
626
        video_on_v <= '0';
627
      else
628
        video_on_v <= video_on_v;
629
      end if;
630
 
631
 
632
      if h_count(9 downto 3) = reg_hcursor(6 downto 0) then
633
        cursor_on_h <= '1';
634
      else
635
        cursor_on_h <= '0';
636
      end if;
637
 
638
      if (v_count(8 downto 4) = reg_vcursor(4 downto 0)) then
639
        cursor_on_v <= '1';
640
      else
641
        cursor_on_v <= '0';
642
      end if;
643
 
644
      -- cursor_on is only active when on selected character
645
      blink_count <= std_logic_vector(unsigned(blink_count) + 1);
646
    end if;
647
 
648
  end process;
649
 
650
  -- video_on is high only when RGB data is displayed
651
  video_on1   <= video_on_H and video_on_V;
652
  cursor_on1  <= cursor_on_h and cursor_on_v;
653
 
654
  -- HDMI video signalling
655
  my_hdmi_assignments : process( vga_red, vga_green, vga_blue )
656
  begin
657
    HDMI_red(0)   <= vga_red;
658
    HDMI_red(1)   <= vga_red;
659
    HDMI_red(2)   <= vga_red;
660
    HDMI_red(3)   <= vga_red;
661
    HDMI_red(4)   <= vga_red;
662
    HDMI_red(5)   <= vga_red;
663
    HDMI_red(6)   <= vga_red;
664
    HDMI_red(7)   <= vga_red;
665
 
666
    HDMI_green(0) <= vga_green;
667
    HDMI_green(1) <= vga_green;
668
    HDMI_green(2) <= vga_green;
669
    HDMI_green(3) <= vga_green;
670
    HDMI_green(4) <= vga_green;
671
    HDMI_green(5) <= vga_green;
672
    HDMI_green(6) <= vga_green;
673
    HDMI_green(7) <= vga_green;
674
 
675
    HDMI_blue(0)  <= vga_blue;
676
    HDMI_blue(1)  <= vga_blue;
677
    HDMI_blue(2)  <= vga_blue;
678
    HDMI_blue(3)  <= vga_blue;
679
    HDMI_blue(4)  <= vga_blue;
680
    HDMI_blue(5)  <= vga_blue;
681
    HDMI_blue(6)  <= vga_blue;
682
    HDMI_blue(7)  <= vga_blue;
683
  end process;
684
 
685
  my_hdmi : RGB2HDMI_encoder
686
  port map (
687
    pixclk      => hdmi_clk,
688
         vSync       => vert_sync,
689
         hSync       => horiz_sync,
690
         DrawArea    => video_on1,
691
         red         => HDMI_red,
692
         green       => HDMI_green,
693
         blue        => HDMI_blue,
694
         TMDSp       => TMDSp,
695
         TMDSn       => TMDSn,
696
         TMDSp_clock => TMDSp_clock,
697
         TMDSn_clock => TMDSn_clock
698
  );
699
 
700
 
701
--
702
-- Here to look up character ROM
703
-- This will take one clock cycle
704
-- and should be performed on h_count = "111"
705
--
706
  char_addr(10 downto 4) <= vga_data_out(6 downto 0);
707
  char_addr(3 downto 0)  <= v_count(3 downto 0);
708
 
709
end RTL;

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