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[/] [System09/] [trunk/] [rtl/] [VHDL/] [xula_ioport.vhd] - Blame information for rev 138

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1 122 dilbert57
--===========================================================================--
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--                                                                           --
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--  xula_ioport.vhd - Synthesizable Dual Bidirectionsal I/O Port             --
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--                                                                           --
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--===========================================================================--
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--
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--  File name      : xula_ioport.vhd
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--
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--  Purpose        : Implements a dual 8 bit bidirectional I/O port
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--                   modified for the XuLA implementation of System09
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--                   Port A supports a full 8 bit bidirectional port
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--                   Port B supports a 5 bit bidirectional port with 3 inputs 
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-- 
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--  Dependencies   : ieee.std_logic_1164
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--                   ieee.std_logic_unsigned
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--                   unisim.vcomponents
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--
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--  Author         : John E. Kent
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--
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--  Email          : dilbert57@opencores.org      
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--
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--  Web            : http://opencores.org/project,system09
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--
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--  xula_ioport.vhd is a dual bi-directional 8 bit I/O port written in VHDL.
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--
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--  address  function
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--  =======  ========
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--  base+0   port a data register
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--           bits 0 - 7 = i/o
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--  base+1   port b data register
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--           bits 0 - 4 = i/o
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--           bits 5 - 7 - inputs
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--  base+2   port a direction register 
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--           0 => port a bit = input
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--           1 => port a bit = output
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--  base+3   port b direction
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--           For bits 0 to 4:
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--           0 => port b bit = input
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--           1 => port b bit = output
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--           For bits 5 to 7:
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--           0 => port b bit = interrupt disable
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--           1 => port b bit = interrupt enable
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--           interrupt inputs on port b bits 5 to 7 are active high
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--
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--  Copyright (C) 2002 - 2011 John Kent
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--
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--  This program is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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--                                                                           --
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--                              Revision  History                            --
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--                                                                           --
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--===========================================================================--
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--
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-- Version  Author        Date               Description
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-- 0.1      John E. Kent  11 October 2002    Used a loop counter for 
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--                                           data direction & read port signals
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-- 0.2      John E. Kent  5 September 2003   Reduced to 2 x 8 bit ports
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-- 1.0      John E. Kent  6 September 2003   Changed Clock Edge
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-- 1.1      John E. Kent  25 Februrary 2007  Modified sensitivity lists
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-- 1.2      John E. Kent  30 May 2010        Updated Header, added unisim library
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-- 2.0      John E. Kent  30 April 2011      modified for XuLA System09 I/O
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--===========================================================================
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--
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library ieee;
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  use ieee.std_logic_1164.all;
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  use ieee.std_logic_unsigned.all;
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--library unisim;
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--  use unisim.vcomponents.all;
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entity xula_ioport is
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  port (
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    clk       : in    std_logic;
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    rst       : in    std_logic;
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    cs        : in    std_logic;
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    rw        : in    std_logic;
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    addr      : in    std_logic_vector(1 downto 0);
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    data_in   : in    std_logic_vector(7 downto 0);
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    data_out  : out   std_logic_vector(7 downto 0);
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    porta_io  : inout std_logic_vector(7 downto 0);
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    portb_io  : inout std_logic_vector(4 downto 0);
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    portc_in  : in    std_logic_vector(7 downto 5);
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    irq       : out   std_logic
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  );
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end;
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architecture rtl of xula_ioport is
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signal porta_ddr : std_logic_vector(7 downto 0);
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signal portb_ddr : std_logic_vector(7 downto 0);
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signal porta_data : std_logic_vector(7 downto 0);
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signal portb_data : std_logic_vector(7 downto 0);
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begin
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--------------------------------
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--
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-- read I/O port
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--
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--------------------------------
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ioport_read : process( addr,
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                     porta_ddr, portb_ddr,
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                                                        porta_data, portb_data,
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                                                   porta_io, portb_io )
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variable count : integer;
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begin
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  case addr is
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  when "00" =>
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    for count in 0 to 7 loop
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      if porta_ddr(count) = '1' then
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        data_out(count) <= porta_data(count);
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      else
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        data_out(count) <= porta_io(count);
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      end if;
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    end loop;
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  when "01" =>
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    for count in 0 to 7 loop
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      if portb_ddr(count) = '1' then
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        data_out(count) <= portb_data(count);
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      else
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                  if count < 5 then
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          data_out(count) <= portb_io(count);
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                  else
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          data_out(count) <= portc_in(count);
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                  end if;
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      end if;
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    end loop;
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  when "10" =>
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    data_out <= porta_ddr;
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  when "11" =>
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    data_out <= portb_ddr;
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  when others =>
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    null;
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  end case;
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end process;
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---------------------------------
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--
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-- Write I/O ports
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--
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---------------------------------
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ioport_write : process( clk, rst, addr, cs, rw, data_in,
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                        porta_data, portb_data,
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                                                                porta_ddr, portb_ddr )
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begin
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  if clk'event and clk = '0' then
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    if rst = '1' then
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      porta_data <= (others=>'0');
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      portb_data <= (others=>'0');
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      porta_ddr  <= (others=>'0');
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      portb_ddr  <= (others=>'0');
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    else
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      if cs = '1' and rw = '0' then
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        case addr is
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        when "00" =>
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           porta_data <= data_in;
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        when "01" =>
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           portb_data <= data_in;
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        when "10" =>
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           porta_ddr  <= data_in;
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        when "11" =>
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           portb_ddr  <= data_in;
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        when others =>
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           null;
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        end case;
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      end if;
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    end if;
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  end if;
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end process;
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---------------------------------
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--
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-- direction control port a
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--
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---------------------------------
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porta_direction : process ( porta_data, porta_ddr )
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variable count : integer;
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begin
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  for count in 0 to 7 loop
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    if porta_ddr(count) = '1' then
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      porta_io(count) <= porta_data(count);
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    else
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      porta_io(count) <= 'Z';
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    end if;
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  end loop;
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end process;
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---------------------------------
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--
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-- direction control port b
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--
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---------------------------------
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portb_direction : process ( portb_data, portb_ddr, portb_io )
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variable count : integer;
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variable irq_temp : std_logic;
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begin
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  --
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  -- For bit 0 to 4 DDR determines the direction of the port
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  --
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  for count in 0 to 4 loop
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    if portb_ddr(count) = '1' then
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      portb_io(count) <= portb_data(count);
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    else
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      portb_io(count) <= 'Z';
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    end if;
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  end loop;
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  --
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  -- For bit 5 to 7 DDR is an interrupt enable
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  --
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  irq_temp := '0';
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  for count in 5 to 7 loop
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    irq_temp := (portc_in(count) AND portb_ddr(count)) OR irq_temp;
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  end loop;
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  irq <= irq_temp;
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end process;
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---------------------------------
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end rtl;
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