1 |
218 |
davidgb |
library IEEE;
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2 |
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use IEEE.std_logic_1164.all;
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3 |
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use IEEE.std_logic_arith.all;
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4 |
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library unisim;
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5 |
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use unisim.vcomponents.all;
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6 |
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7 |
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entity SYS09BUG_F000 is
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8 |
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port(
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9 |
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clk : in std_logic;
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10 |
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rst : in std_logic;
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11 |
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cs : in std_logic;
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12 |
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rw : in std_logic;
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13 |
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addr : in std_logic_vector(10 downto 0);
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14 |
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data_out : out std_logic_vector(7 downto 0);
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15 |
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data_in : in std_logic_vector(7 downto 0)
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16 |
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);
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17 |
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end SYS09BUG_F000;
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18 |
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19 |
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architecture rtl of SYS09BUG_F000 is
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20 |
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21 |
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type data_array is array(0 to 0) of std_logic_vector(7 downto 0);
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22 |
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signal xdata : data_array;
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23 |
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signal en : std_logic_vector(0 downto 0);
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24 |
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signal dp : std_logic_vector(0 downto 0);
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25 |
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signal we : std_logic;
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begin
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28 |
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ROM00: RAMB16_S9
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30 |
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generic map (
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31 |
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INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
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32 |
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INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
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33 |
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INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
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34 |
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INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
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35 |
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INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
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37 |
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INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
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38 |
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INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
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40 |
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INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
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44 |
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INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
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45 |
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INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000",
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47 |
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INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000",
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48 |
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INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000",
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49 |
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INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000",
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50 |
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INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000",
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51 |
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INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000",
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54 |
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INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000",
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55 |
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INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000",
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56 |
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INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000",
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57 |
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INIT_1a => x"0000000000000000000000000000000000000000000000000000000000000000",
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58 |
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INIT_1b => x"0000000000000000000000000000000000000000000000000000000000000000",
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59 |
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INIT_1c => x"0000000000000000000000000000000000000000000000000000000000000000",
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60 |
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INIT_1d => x"0000000000000000000000000000000000000000000000000000000000000000",
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61 |
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INIT_1e => x"0000000000000000000000000000000000000000000000000000000000000000",
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62 |
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INIT_1f => x"0000000000000000000000000000000000000000000000000000000000000000",
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63 |
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INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000",
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64 |
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INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000",
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65 |
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INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000",
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66 |
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INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000",
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67 |
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INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000",
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68 |
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INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000",
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69 |
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INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000",
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70 |
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INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000",
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71 |
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INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2a => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2b => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2c => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2d => x"0000000000000000000000000000000000000000000000000000000000000000",
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77 |
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INIT_2e => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2f => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
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87 |
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INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",
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89 |
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INIT_3a => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3b => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3c => x"0000000000000000000000000000000000000000000000000000000000000000",
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92 |
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INIT_3d => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3e => x"0000000000000000000000000000000000000000000000000000000000000000",
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94 |
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INIT_3f => x"0000000000000000000000000000000000000000000000000000000000000000"
|
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)
|
96 |
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port map (
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97 |
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CLK => clk,
|
98 |
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SSR => rst,
|
99 |
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EN => en(0),
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100 |
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WE => we,
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101 |
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ADDR => addr(10 downto 0),
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102 |
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DI => data_in,
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103 |
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DIP(0) => dp(0),
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104 |
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DO => xdata(0),
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105 |
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DOP(0) => dp(0)
|
106 |
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);
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107 |
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rom_glue: process (cs, rw, addr, xdata)
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108 |
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begin
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109 |
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en(0) <= cs;
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110 |
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data_out <= xdata(0);
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111 |
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we <= not rw;
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112 |
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end process;
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113 |
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end architecture rtl;
|
114 |
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|
115 |
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library IEEE;
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116 |
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use IEEE.std_logic_1164.all;
|
117 |
|
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use IEEE.std_logic_arith.all;
|
118 |
|
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library unisim;
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119 |
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use unisim.vcomponents.all;
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120 |
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121 |
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entity SYS09BUG_F800 is
|
122 |
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port(
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123 |
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clk : in std_logic;
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124 |
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rst : in std_logic;
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125 |
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cs : in std_logic;
|
126 |
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rw : in std_logic;
|
127 |
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addr : in std_logic_vector(10 downto 0);
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128 |
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data_out : out std_logic_vector(7 downto 0);
|
129 |
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data_in : in std_logic_vector(7 downto 0)
|
130 |
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);
|
131 |
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end SYS09BUG_F800;
|
132 |
|
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|
133 |
|
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architecture rtl of SYS09BUG_F800 is
|
134 |
|
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|
135 |
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type data_array is array(0 to 0) of std_logic_vector(7 downto 0);
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136 |
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signal xdata : data_array;
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137 |
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signal en : std_logic_vector(0 downto 0);
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138 |
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signal dp : std_logic_vector(0 downto 0);
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139 |
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signal we : std_logic;
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140 |
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141 |
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begin
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142 |
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|
143 |
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ROM00: RAMB16_S9
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144 |
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generic map (
|
145 |
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INIT_00 => x"A780A610C6C0DF8E107CFC8EF9FC81FA85FAF6FA21FC13FCFEFB04FC48F814F8",
|
146 |
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INIT_01 => x"17431FE4A7D0866AAFDD8C30FB265AE26F0CC6420117D0DFBF00008EF9265AA0",
|
147 |
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INIT_02 => x"175E86092C2081891FF1270D817F84B30317330217ADFC8EAE02178CFC8EF403",
|
148 |
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INIT_03 => x"F5267CFC8C02300F2780E149FC8E20C0022F60C1B30317B80317408B981FBF03",
|
149 |
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INIT_04 => x"0317211FE50117B5FC8E121F2D29EB02173B341FBC2094ADC020700217AFFC8E",
|
150 |
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INIT_05 => x"260D8117275E81DD271881E12708811128DE0217730317250317A4A67B031725",
|
151 |
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INIT_06 => x"C0DF8E321F220217BE203F31C22021315103173F865403170827A4A1A4A7390F",
|
152 |
|
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INIT_07 => x"AC011FF0C4201F0634F0C41000C3101F390124E1AC203406298B021705201F30",
|
153 |
|
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INIT_08 => x"1780A610C6020317AE0217E4AE6E0117B5FC8E103439623203270D03170527E4",
|
154 |
|
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INIT_09 => x"265AE302172E8602237E810425208180A610C6E1AEF20217F5265AFA0217AC02",
|
155 |
|
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INIT_0a => x"A0A709273F8184A60F271035558DFFFF8E10341A24C0DF8C1E29370217BC20EE",
|
156 |
|
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INIT_0b => x"304AAE431F39FB265A188D08C6D3DF8E10B202163F86B502173984A73F86A4AF",
|
157 |
|
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INIT_0c => x"84A7A4A604263F8184A60A24C0DF8C21AEB9FE16C80117068D4AAF0427268D1F",
|
158 |
|
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INIT_0d => x"20C60434393D3139F7265A0427A1ACA0A608C6D3DF8E1039A0A7A0A7A0A7FF86",
|
159 |
|
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INIT_0e => x"31813D2739811F0217F9265381260217D2DF7F540217118636FCBD8435FD265A",
|
160 |
|
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INIT_0f => x"358E01170434E46AE46AE4EBE0EBE0E61034212991011726290234A80117F126",
|
161 |
|
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INIT_10 => x"1386D2DF730602173F86BA27FFC102355FEB2080A70527E46AE0EB02340C2904",
|
162 |
|
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INIT_11 => x"62A3E4ECE50117128636FCBDE4AF0130492562AC4D2930344A0117E26FFE0116",
|
163 |
|
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INIT_12 => x"62EB68011762AE750117981F03CB2F0017F6FC8E64E720C60223200083100627",
|
164 |
|
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INIT_13 => x"6532A301171486C326E4AC62AF5B0117981F53F526646A65011780A684EB63EB",
|
165 |
|
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INIT_14 => x"29F68DF28D910017E50016F800168D01169035690017A7FC8E10347120028D39",
|
166 |
|
|
INIT_15 => x"D58DD18D5E8D3946AF0229E08DDC8D728D3948AF0229EB8DE78D618D394AAF02",
|
167 |
|
|
INIT_16 => x"8DB08D588D3942A70229BC8DBB8D6C8D3943A70229C78DC68D498D3944AF0229",
|
168 |
|
|
INIT_17 => x"B9FC8E39F726048180A62B011739C4A7808A0429A68DA58D5F8D3941A70229B1",
|
169 |
|
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INIT_18 => x"AED78DD1FC8EB4001643A6E18DD7FC8EF42048AEEA8DC5FC8EBF0016311FF48D",
|
170 |
|
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INIT_19 => x"FC8ED92041A6BC8DDDFC8ECF204AAEC58DBFFC8ED82046AECE8DCBFC8EE12044",
|
171 |
|
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INIT_1a => x"B08DA98DA18D27FF17B5FC8E900016EEFC8EC4A6AA8DE7FC8ED02042A6B38DE2",
|
172 |
|
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INIT_1b => x"290E8DA400172D86121F4D29098DD520CE8DC78DC08D17FF17B5FC8EBF8DB88D",
|
173 |
|
|
INIT_1c => x"39E0AB04342829078D891F484848483229118D903561A710343C29088D011F42",
|
174 |
|
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INIT_1d => x"03226681072561813937800322468112254181393080032239811D253081578D",
|
175 |
|
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INIT_1e => x"022F3981308B0F840235048D4444444402340235028D0235103439021A395780",
|
176 |
|
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INIT_1f => x"048D0627D2DF7D8235F1265A2B8D2F8D2D860225E46880A608C602343D20078B",
|
177 |
|
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INIT_20 => x"86008D82350185D0DF9FA60234903501A6F727018584A6D0DFBE10341D207F84",
|
178 |
|
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INIT_21 => x"A7518684A70386D0DFBE903501A70235F6260885FA27028584A6D0DFBE123420",
|
179 |
|
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INIT_22 => x"FA19BAFA18A4FA1598FA10C5FA04E6FA03D0FA02DBFA0139D2DFB7FF86016D84",
|
180 |
|
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INIT_23 => x"8EF87BF96FF958D8F85354FB528FF84D23FA50C5F94C8CF847E4F84543F942AF",
|
181 |
|
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INIT_24 => x"4F4620372E312067754239307379530000000A0DFFFFFFFF7BF98EF88EF88EF8",
|
182 |
|
|
INIT_25 => x"20043D5053202004202D20043F54414857043E040000000A0D4B04202D202052",
|
183 |
|
|
INIT_26 => x"412020043D50442020043D58492020043D59492020043D53552020043D435020",
|
184 |
|
|
INIT_27 => x"535FC0DFCE103904315343565A4E4948464504203A43432020043D422020043D",
|
185 |
|
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INIT_28 => x"80E64AAE431FCADF9F6EC8DF9F6EC6DF9F6EC4DF9F6EC0DF9F6E0EFB16D2DFF7",
|
186 |
|
|
INIT_29 => x"42EE1F37F16E44AEC4EC10340822CEDFBC8B300F27FFFF8CCCDFBE49584F4AAF",
|
187 |
|
|
INIT_2a => x"00000000000000000000000000000000000000000000000000000000C2DF9F6E",
|
188 |
|
|
INIT_2b => x"0000000000000000000000000000000000000000000000000000000000000000",
|
189 |
|
|
INIT_2c => x"0000000000000000000000000000000000000000000000000000000000000000",
|
190 |
|
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INIT_2d => x"0000000000000000000000000000000000000000000000000000000000000000",
|
191 |
|
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INIT_2e => x"0000000000000000000000000000000000000000000000000000000000000000",
|
192 |
|
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INIT_2f => x"0000000000000000000000000000000000000000000000000000000000000000",
|
193 |
|
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INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000",
|
194 |
|
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INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000",
|
195 |
|
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INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
|
196 |
|
|
INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
|
197 |
|
|
INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
|
198 |
|
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INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
|
199 |
|
|
INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
|
200 |
|
|
INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
|
201 |
|
|
INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000",
|
202 |
|
|
INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",
|
203 |
|
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INIT_3a => x"0000000000000000000000000000000000000000000000000000000000000000",
|
204 |
|
|
INIT_3b => x"0000000000000000000000000000000000000000000000000000000000000000",
|
205 |
|
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INIT_3c => x"0000000000000000000000000000000000000000000000000000000000000000",
|
206 |
|
|
INIT_3d => x"0000000000000000000000000000000000000000000000000000000000000000",
|
207 |
|
|
INIT_3e => x"0000000000000000000000000000000000000000000000000000000000000000",
|
208 |
|
|
INIT_3f => x"FAFC06FD16FD12FD0EFD0AFD1AFD06FD00000000000000000000000000000000"
|
209 |
|
|
)
|
210 |
|
|
port map (
|
211 |
|
|
CLK => clk,
|
212 |
|
|
SSR => rst,
|
213 |
|
|
EN => en(0),
|
214 |
|
|
WE => we,
|
215 |
|
|
ADDR => addr(10 downto 0),
|
216 |
|
|
DI => data_in,
|
217 |
|
|
DIP(0) => dp(0),
|
218 |
|
|
DO => xdata(0),
|
219 |
|
|
DOP(0) => dp(0)
|
220 |
|
|
);
|
221 |
|
|
rom_glue: process (cs, rw, addr, xdata)
|
222 |
|
|
begin
|
223 |
|
|
en(0) <= cs;
|
224 |
|
|
data_out <= xdata(0);
|
225 |
|
|
we <= not rw;
|
226 |
|
|
end process;
|
227 |
|
|
end architecture rtl;
|
228 |
|
|
|
229 |
|
|
--
|
230 |
|
|
-- SYS09BUG Monitor Program
|
231 |
|
|
-- v1.0 - 21 November 2006 - John Knet
|
232 |
|
|
--
|
233 |
|
|
-- v1.1 - 22 december 2006 - John Kent
|
234 |
|
|
-- made into 4K ROM/RAM.
|
235 |
|
|
--
|
236 |
|
|
library IEEE;
|
237 |
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
238 |
|
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
239 |
|
|
library unisim;
|
240 |
|
|
use unisim.vcomponents.all;
|
241 |
|
|
|
242 |
|
|
entity mon_rom is
|
243 |
|
|
Port (
|
244 |
|
|
clk : in std_logic;
|
245 |
|
|
rst : in std_logic;
|
246 |
|
|
cs : in std_logic;
|
247 |
|
|
rw : in std_logic;
|
248 |
|
|
addr : in std_logic_vector (11 downto 0);
|
249 |
|
|
data_out : out std_logic_vector (7 downto 0);
|
250 |
|
|
data_in : in std_logic_vector (7 downto 0)
|
251 |
|
|
);
|
252 |
|
|
end mon_rom;
|
253 |
|
|
|
254 |
|
|
architecture rtl of mon_rom is
|
255 |
|
|
|
256 |
|
|
signal we : std_logic;
|
257 |
|
|
signal cs0 : std_logic;
|
258 |
|
|
signal cs1 : std_logic;
|
259 |
|
|
signal dp0 : std_logic;
|
260 |
|
|
signal dp1 : std_logic;
|
261 |
|
|
signal rdata0 : std_logic_vector(7 downto 0);
|
262 |
|
|
signal rdata1 : std_logic_vector(7 downto 0);
|
263 |
|
|
|
264 |
|
|
component SYS09BUG_F000
|
265 |
|
|
Port (
|
266 |
|
|
clk : in std_logic;
|
267 |
|
|
rst : in std_logic;
|
268 |
|
|
cs : in std_logic;
|
269 |
|
|
rw : in std_logic;
|
270 |
|
|
addr : in std_logic_vector (10 downto 0);
|
271 |
|
|
data_out : out std_logic_vector (7 downto 0);
|
272 |
|
|
data_in : in std_logic_vector (7 downto 0)
|
273 |
|
|
);
|
274 |
|
|
end component;
|
275 |
|
|
|
276 |
|
|
component SYS09BUG_F800
|
277 |
|
|
Port (
|
278 |
|
|
clk : in std_logic;
|
279 |
|
|
rst : in std_logic;
|
280 |
|
|
cs : in std_logic;
|
281 |
|
|
rw : in std_logic;
|
282 |
|
|
addr : in std_logic_vector (10 downto 0);
|
283 |
|
|
data_out : out std_logic_vector (7 downto 0);
|
284 |
|
|
data_in : in std_logic_vector (7 downto 0)
|
285 |
|
|
);
|
286 |
|
|
end component;
|
287 |
|
|
|
288 |
|
|
begin
|
289 |
|
|
|
290 |
|
|
addr_f000 : SYS09BUG_F000 port map (
|
291 |
|
|
clk => clk,
|
292 |
|
|
rst => rst,
|
293 |
|
|
cs => cs0,
|
294 |
|
|
rw => rw,
|
295 |
|
|
addr => addr(10 downto 0),
|
296 |
|
|
data_in => data_in,
|
297 |
|
|
data_out => rdata0
|
298 |
|
|
);
|
299 |
|
|
|
300 |
|
|
addr_f800 : SYS09BUG_F800 port map (
|
301 |
|
|
clk => clk,
|
302 |
|
|
rst => rst,
|
303 |
|
|
cs => cs1,
|
304 |
|
|
rw => rw,
|
305 |
|
|
addr => addr(10 downto 0),
|
306 |
|
|
data_in => data_in,
|
307 |
|
|
data_out => rdata1
|
308 |
|
|
);
|
309 |
|
|
|
310 |
|
|
my_mon : process ( rw, addr, cs, rdata0, rdata1 )
|
311 |
|
|
begin
|
312 |
|
|
we <= not rw;
|
313 |
|
|
case addr(11) is
|
314 |
|
|
when '0' =>
|
315 |
|
|
cs0 <= cs;
|
316 |
|
|
cs1 <= '0';
|
317 |
|
|
data_out <= rdata0;
|
318 |
|
|
when '1' =>
|
319 |
|
|
cs0 <= '0';
|
320 |
|
|
cs1 <= cs;
|
321 |
|
|
data_out <= rdata1;
|
322 |
|
|
when others =>
|
323 |
|
|
null;
|
324 |
|
|
end case;
|
325 |
|
|
end process;
|
326 |
|
|
|
327 |
|
|
end architecture rtl;
|
328 |
|
|
|