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[/] [a-z80/] [trunk/] [cpu/] [control/] [clk_delay.bdf] - Blame information for rev 8

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1 3 gdevic 
/*
2 
WARNING: Do NOT edit the input and output ports in this file in a text
3 
editor if you plan to continue editing the block that represents it in
4 
the Block Editor! File corruption is VERY likely to occur.
5 
*/
6 
/*
7 
Copyright (C) 1991-2013 Altera Corporation
8 
Your use of Altera Corporation's design tools, logic functions
9 
and other software and tools, and its AMPP partner logic
10 
functions, and any output files from any of the foregoing
11 
(including device programming or simulation files), and any
12 
associated documentation or information are expressly subject
13 
to the terms and conditions of the Altera Program License
14 
Subscription Agreement, Altera MegaCore Function License
15 
Agreement, or other applicable license agreement, including,
16 
without limitation, that your use is for the sole purpose of
17 
programming logic devices manufactured by Altera and sold by
18 
Altera or its authorized distributors.  Please refer to the
19 
applicable agreement for further details.
20 
*/
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