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[/] [a-z80/] [trunk/] [cpu/] [control/] [exec_matrix.vh] - Blame information for rev 8

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Line No. Rev Author Line
1 6 gdevic 
// Automatically generated by genmatrix.py
2 8 gdevic 
 
3 6 gdevic 
// 8-bit Load Group
4 8 gdevic 
if (pla[17] & ~pla[50]) begin
5 
    if (M1 & T1) begin
6 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
7 6 gdevic 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
8 
                    ctl_sw_2d=1;
9 
                    ctl_sw_1d=1;
10 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
11 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
12 
    if (M2 & T1) begin fMRead=1;
13 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
14 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
15 8 gdevic 
    if (M2 & T2) begin fMRead=1;
16 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
17 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
18 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
19 8 gdevic 
    if (M2 & T3) begin fMRead=1; setM1=1; end
20 6 gdevic 
end
21 
 
22 8 gdevic 
if (pla[61] & ~pla[58] & ~pla[59]) begin
23 
    if (M1 & T1) begin
24 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
25 6 gdevic 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
26 
                    ctl_sw_2u=1;
27 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
28 
                    ctl_alu_op1_oe=1; /* OP1 latch */ end
29 8 gdevic 
    if (M1 & T4) begin validPLA=1; setM1=1;
30 
                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
31 
                    ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
32 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
33 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end
34 
end
35 
 
36 8 gdevic 
if (use_ixiy & pla[58]) begin
37 
    if (M1 & T1) begin
38 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
39 6 gdevic 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
40 
                    ctl_sw_2d=1;
41 
                    ctl_sw_1d=1;
42 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
43 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
44 
    if (M2 & T1) begin fMRead=1;
45 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
46 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
47 8 gdevic 
    if (M2 & T2) begin fMRead=1;
48 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
49 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
50 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
51 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; end
52 
    if (M3 & T1) begin ixy_d=1; /* Compute WZ=IX+d */ end
53 
    if (M3 & T2) begin ixy_d=1; /* Compute WZ=IX+d */ end
54 
    if (M3 & T3) begin ixy_d=1; /* Compute WZ=IX+d */ end
55 
    if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
56 
    if (M3 & T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
57 6 gdevic 
end
58 
 
59 8 gdevic 
if (~use_ixiy & pla[58]) begin
60 
    if (M1 & T1) begin
61 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
62 6 gdevic 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
63 
                    ctl_sw_2d=1;
64 
                    ctl_sw_1d=1;
65 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
66 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
67 
    if (M2 & T1) begin fMRead=1;
68 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
69 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
70 8 gdevic 
    if (M2 & T2) begin fMRead=1; end
71 
    if (M2 & T3) begin fMRead=1; setM1=1; end
72 
    if (M4 & T1) begin fMRead=1;
73 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
74 8 gdevic 
    if (M4 & T2) begin fMRead=1; end
75 
    if (M4 & T3) begin fMRead=1; setM1=1; end
76 6 gdevic 
end
77 
 
78 8 gdevic 
if (use_ixiy & pla[59]) begin
79 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
80 
    if (M2 & T1) begin fMRead=1;
81 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
82 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
83 8 gdevic 
    if (M2 & T2) begin fMRead=1;
84 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
85 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
86 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
87 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; end
88 
    if (M3 & T1) begin ixy_d=1; /* Compute WZ=IX+d */ end
89 
    if (M3 & T2) begin ixy_d=1; /* Compute WZ=IX+d */ end
90 
    if (M3 & T3) begin ixy_d=1; /* Compute WZ=IX+d */ end
91 
    if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
92 
    if (M3 & T5) begin nextM=1; ctl_mWrite=1; ixy_d=1; /* Compute WZ=IX+d */ end
93 6 gdevic 
end
94 
 
95 8 gdevic 
if (~use_ixiy & pla[59]) begin
96 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mWrite=1;
97 
                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
98 
                    ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
99 6 gdevic 
                    ctl_sw_1u=1;
100 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
101 8 gdevic 
    if (M2 & T1) begin fMWrite=1;
102 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
103 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
104 8 gdevic 
    if (M2 & T2) begin fMWrite=1; end
105 
    if (M2 & T3) begin fMWrite=1; setM1=1; end
106 
    if (M4 & T1) begin fMWrite=1;
107 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
108 8 gdevic 
                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
109 
                    ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
110 6 gdevic 
                    ctl_sw_1u=1;
111 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
112 8 gdevic 
    if (M4 & T2) begin fMWrite=1; end
113 
    if (M4 & T3) begin fMWrite=1; setM1=1; end
114 6 gdevic 
end
115 
 
116 
if (pla[40]) begin
117 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
118 
    if (M2 & T1) begin fMRead=1;
119 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
120 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
121 8 gdevic 
    if (M2 & T2) begin fMRead=1;
122 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
123 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
124 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
125 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1; end
126 
    if (M3 & T1) begin fMRead=1;
127 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
128 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ ixy_d=1; /* Compute WZ=IX+d */ end
129 8 gdevic 
    if (M3 & T2) begin fMRead=1;
130 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
131 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
132 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ ixy_d=1; /* Compute WZ=IX+d */ end
133 8 gdevic 
    if (M3 & T3) begin fMRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
134 
    if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
135 
    if (M3 & T5) begin nextM=1; ctl_mWrite=1; ixy_d=1; /* Compute WZ=IX+d */ end
136 6 gdevic 
end
137 
 
138 8 gdevic 
if (pla[50] & ~pla[40]) begin
139 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
140 
    if (M2 & T1) begin fMRead=1;
141 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
142 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
143 8 gdevic 
    if (M2 & T2) begin fMRead=1;
144 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
145 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
146 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
147 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1; end
148 
    if (M3 & T1) begin fMWrite=1;
149 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
150 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
151 8 gdevic 
    if (M3 & T2) begin fMWrite=1; end
152 
    if (M3 & T3) begin fMWrite=1; setM1=1; end
153 
    if (M4 & T1) begin fMWrite=1;
154 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
155 8 gdevic 
    if (M4 & T2) begin fMWrite=1; end
156 
    if (M4 & T3) begin fMWrite=1; setM1=1; end
157 6 gdevic 
end
158 
 
159 8 gdevic 
if (pla[8] & pla[13]) begin
160 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mWrite=1;
161 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
162 8 gdevic 
                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
163 6 gdevic 
                    ctl_sw_2u=1;
164 
                    ctl_sw_1u=1;
165 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
166 8 gdevic 
    if (M2 & T1) begin fMWrite=1;
167 6 gdevic 
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */
168 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
169 8 gdevic 
    if (M2 & T2) begin fMWrite=1;
170 6 gdevic 
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
171 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
172 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
173 8 gdevic 
    if (M2 & T3) begin fMWrite=1; setM1=1; end
174 6 gdevic 
end
175 
 
176 8 gdevic 
if (pla[8] & ~pla[13]) begin
177 
    if (M1 & T1) begin
178 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
179 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
180 
                    ctl_sw_2d=1;
181 
                    ctl_sw_1d=1;
182 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
183 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
184 
    if (M2 & T1) begin fMRead=1;
185 6 gdevic 
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */
186 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
187 8 gdevic 
    if (M2 & T2) begin fMRead=1;
188 6 gdevic 
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
189 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
190 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
191 8 gdevic 
    if (M2 & T3) begin fMRead=1; setM1=1; end
192 6 gdevic 
end
193 
 
194 8 gdevic 
if (pla[38] & pla[13]) begin
195 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
196 
    if (M2 & T1) begin fMRead=1;
197 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
198 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
199 8 gdevic 
    if (M2 & T2) begin fMRead=1;
200 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
201 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
202 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
203 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
204 
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
205 6 gdevic 
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
206 
                    ctl_sw_2d=1;
207 
                    ctl_sw_1d=1;
208 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
209 8 gdevic 
    if (M3 & T1) begin fMRead=1;
210 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
211 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
212 8 gdevic 
    if (M3 & T2) begin fMRead=1;
213 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
214 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
215 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
216 8 gdevic 
    if (M3 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
217 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
218 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
219 8 gdevic 
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
220 6 gdevic 
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
221 
                    ctl_sw_2d=1;
222 
                    ctl_sw_1d=1;
223 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
224 8 gdevic 
    if (M4 & T1) begin fMWrite=1;
225 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
226 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
227 8 gdevic 
                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
228 6 gdevic 
                    ctl_sw_2u=1;
229 
                    ctl_sw_1u=1;
230 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
231 8 gdevic 
    if (M4 & T2) begin fMWrite=1;
232 6 gdevic 
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
233 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
234 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
235 8 gdevic 
    if (M4 & T3) begin fMWrite=1; setM1=1; end
236 6 gdevic 
end
237 
 
238 8 gdevic 
if (pla[38] & ~pla[13]) begin
239 
    if (M1 & T1) begin
240 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
241 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
242 
                    ctl_sw_2d=1;
243 
                    ctl_sw_1d=1;
244 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
245 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
246 
    if (M2 & T1) begin fMRead=1;
247 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
248 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
249 8 gdevic 
    if (M2 & T2) begin fMRead=1;
250 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
251 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
252 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
253 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
254 
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
255 6 gdevic 
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
256 
                    ctl_sw_2d=1;
257 
                    ctl_sw_1d=1;
258 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
259 8 gdevic 
    if (M3 & T1) begin fMRead=1;
260 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
261 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
262 8 gdevic 
    if (M3 & T2) begin fMRead=1;
263 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
264 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
265 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
266 8 gdevic 
    if (M3 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
267 
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
268 6 gdevic 
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
269 
                    ctl_sw_2d=1;
270 
                    ctl_sw_1d=1;
271 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
272 8 gdevic 
    if (M4 & T1) begin fMRead=1;
273 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
274 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
275 8 gdevic 
    if (M4 & T2) begin fMRead=1;
276 6 gdevic 
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
277 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
278 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
279 8 gdevic 
    if (M4 & T3) begin fMRead=1; setM1=1; end
280 6 gdevic 
end
281 
 
282 
if (pla[83]) begin
283 8 gdevic 
    if (M1 & T1) begin
284 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
285 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
286 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
287 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
288 
                    ctl_alu_res_oe=1; /* Result latch */
289 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
290 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
291 
                    ctl_flags_sz_we=1;
292 
                    ctl_flags_xy_we=1;
293 
                    ctl_flags_hf_we=1;
294 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_IFF2;
295 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
296 8 gdevic 
    if (M1 & T2) begin
297 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
298 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
299 
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
300 8 gdevic 
    if (M1 & T3) begin
301 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
302 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
303 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
304 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
305 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
306 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
307 
                    ctl_flags_sz_we=1;
308 
                    ctl_flags_xy_we=1;
309 
                    ctl_flags_hf_we=1;
310 
                    ctl_flags_pf_we=1;
311 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
312 
                    ctl_flags_cf_we=1; end
313 8 gdevic 
    if (M1 & T4) begin validPLA=1;
314 
                    ctl_reg_sel_ir=1; ctl_reg_sys_hilo={~op3,op3}; ctl_sw_4u=1; /* Read either I or R based on op3 (0 or 1) */
315 
                    ctl_reg_out_hi=~rsel3; ctl_reg_out_lo=rsel3; ctl_sw_2u=~rsel3; ctl_sw_2d=rsel3; /* Enable register gate based on the rsel3 */ /* Controlled by register gate */
316 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
317 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
318 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
319 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
320 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
321 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
322 
                    ctl_flags_sz_we=1;
323 
                    ctl_flags_xy_we=1;
324 
                    ctl_flags_hf_we=1;
325 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
326 8 gdevic 
    if (M1 & T5) begin setM1=1; end
327 6 gdevic 
end
328 
 
329 
if (pla[57]) begin
330 8 gdevic 
    if (M1 & T3) begin
331 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
332 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
333 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
334 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
335 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
336 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
337 
                    ctl_flags_sz_we=1;
338 
                    ctl_flags_xy_we=1;
339 
                    ctl_flags_hf_we=1;
340 
                    ctl_flags_pf_we=1;
341 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
342 
                    ctl_flags_cf_we=1; end
343 8 gdevic 
    if (M1 & T4) begin validPLA=1;
344 
                    ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo={~op3,op3}; ctl_sw_4d=1; /* Write either I or R based on op3 (0 or 1) */
345 6 gdevic 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
346 
                    ctl_sw_2u=1;
347 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
348 
                    ctl_alu_op1_oe=1; /* OP1 latch */ end
349 8 gdevic 
    if (M1 & T5) begin setM1=1; end
350 6 gdevic 
end
351 
 
352 
// 16-bit Load Group
353 
if (pla[7]) begin
354 8 gdevic 
    if (M1 & T1) begin
355 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
356 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
357 
                    ctl_sw_2d=1;
358 
                    ctl_sw_1d=1;
359 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
360 
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
361 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
362 
    if (M2 & T1) begin fMRead=1;
363 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
364 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
365 8 gdevic 
    if (M2 & T2) begin fMRead=1;
366 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
367 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
368 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
369 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1; end
370 
    if (M3 & T1) begin fMRead=1;
371 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
372 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
373 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
374 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
375 
                    ctl_sw_2d=1;
376 
                    ctl_sw_1d=1;
377 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
378 
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
379 8 gdevic 
    if (M3 & T2) begin fMRead=1;
380 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
381 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
382 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
383 8 gdevic 
    if (M3 & T3) begin fMRead=1; setM1=1; end
384 6 gdevic 
end
385 
 
386 8 gdevic 
if (pla[30] & pla[13]) begin
387 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
388 
    if (M2 & T1) begin fMRead=1;
389 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
390 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
391 8 gdevic 
    if (M2 & T2) begin fMRead=1;
392 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
393 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
394 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
395 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
396 
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
397 6 gdevic 
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
398 
                    ctl_sw_2d=1;
399 
                    ctl_sw_1d=1;
400 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
401 8 gdevic 
    if (M3 & T1) begin fMRead=1;
402 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
403 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
404 8 gdevic 
    if (M3 & T2) begin fMRead=1;
405 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
406 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
407 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
408 8 gdevic 
    if (M3 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
409 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
410 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
411 8 gdevic 
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
412 6 gdevic 
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
413 
                    ctl_sw_2d=1;
414 
                    ctl_sw_1d=1;
415 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
416 8 gdevic 
    if (M4 & T1) begin fMWrite=1;
417 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
418 
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
419 8 gdevic 
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
420 6 gdevic 
                    ctl_sw_1u=1;
421 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
422 8 gdevic 
    if (M4 & T2) begin fMWrite=1;
423 6 gdevic 
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
424 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
425 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
426 8 gdevic 
    if (M4 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
427 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
428 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
429 8 gdevic 
    if (M5 & T1) begin fMWrite=1;
430 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
431 
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
432 8 gdevic 
                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
433 6 gdevic 
                    ctl_sw_2u=1;
434 
                    ctl_sw_1u=1;
435 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
436 8 gdevic 
    if (M5 & T2) begin fMWrite=1;
437 6 gdevic 
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
438 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
439 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
440 8 gdevic 
    if (M5 & T3) begin fMWrite=1; setM1=1; end
441 6 gdevic 
end
442 
 
443 8 gdevic 
if (pla[30] & ~pla[13]) begin
444 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
445 
    if (M2 & T1) begin fMRead=1;
446 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
447 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
448 8 gdevic 
    if (M2 & T2) begin fMRead=1;
449 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
450 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
451 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
452 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
453 
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
454 6 gdevic 
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
455 
                    ctl_sw_2d=1;
456 
                    ctl_sw_1d=1;
457 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
458 8 gdevic 
    if (M3 & T1) begin fMRead=1;
459 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
460 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
461 8 gdevic 
    if (M3 & T2) begin fMRead=1;
462 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
463 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
464 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
465 8 gdevic 
    if (M3 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
466 
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
467 6 gdevic 
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
468 
                    ctl_sw_2d=1;
469 
                    ctl_sw_1d=1;
470 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
471 8 gdevic 
    if (M4 & T1) begin fMRead=1;
472 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
473 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
474 8 gdevic 
    if (M4 & T2) begin fMRead=1;
475 6 gdevic 
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
476 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
477 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
478 8 gdevic 
    if (M4 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
479 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
480 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
481 
                    ctl_sw_2d=1;
482 
                    ctl_sw_1d=1;
483 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
484 8 gdevic 
    if (M5 & T1) begin fMRead=1;
485 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
486 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
487 8 gdevic 
    if (M5 & T2) begin fMRead=1;
488 6 gdevic 
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
489 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
490 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
491 8 gdevic 
    if (M5 & T3) begin fMRead=1; setM1=1;
492 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
493 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
494 
                    ctl_sw_2d=1;
495 
                    ctl_sw_1d=1;
496 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
497 
end
498 
 
499 8 gdevic 
if (pla[31] & pla[33]) begin
500 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
501 
    if (M2 & T1) begin fMRead=1;
502 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
503 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
504 8 gdevic 
    if (M2 & T2) begin fMRead=1;
505 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
506 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
507 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
508 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
509 
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
510 6 gdevic 
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
511 
                    ctl_sw_2d=1;
512 
                    ctl_sw_1d=1;
513 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
514 8 gdevic 
    if (M3 & T1) begin fMRead=1;
515 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
516 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
517 8 gdevic 
    if (M3 & T2) begin fMRead=1;
518 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
519 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
520 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
521 8 gdevic 
    if (M3 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
522 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
523 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
524 8 gdevic 
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
525 6 gdevic 
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
526 
                    ctl_sw_2d=1;
527 
                    ctl_sw_1d=1;
528 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
529 8 gdevic 
    if (M4 & T1) begin fMWrite=1;
530 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
531 
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
532 8 gdevic 
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
533 6 gdevic 
                    ctl_sw_1u=1;
534 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
535 
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
536 8 gdevic 
    if (M4 & T2) begin fMWrite=1;
537 6 gdevic 
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
538 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
539 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
540 8 gdevic 
    if (M4 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
541 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
542 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
543 8 gdevic 
    if (M5 & T1) begin fMWrite=1;
544 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
545 
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
546 8 gdevic 
                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
547 6 gdevic 
                    ctl_sw_2u=1;
548 
                    ctl_sw_1u=1;
549 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
550 
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
551 8 gdevic 
    if (M5 & T2) begin fMWrite=1;
552 6 gdevic 
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
553 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
554 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
555 8 gdevic 
    if (M5 & T3) begin fMWrite=1; setM1=1; end
556 6 gdevic 
end
557 
 
558 8 gdevic 
if (pla[31] & ~pla[33]) begin
559 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
560 
    if (M2 & T1) begin fMRead=1;
561 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
562 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
563 8 gdevic 
    if (M2 & T2) begin fMRead=1;
564 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
565 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
566 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
567 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
568 
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
569 6 gdevic 
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
570 
                    ctl_sw_2d=1;
571 
                    ctl_sw_1d=1;
572 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
573 8 gdevic 
    if (M3 & T1) begin fMRead=1;
574 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
575 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
576 8 gdevic 
    if (M3 & T2) begin fMRead=1;
577 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
578 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
579 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
580 8 gdevic 
    if (M3 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
581 
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
582 6 gdevic 
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
583 
                    ctl_sw_2d=1;
584 
                    ctl_sw_1d=1;
585 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
586 8 gdevic 
    if (M4 & T1) begin fMRead=1;
587 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
588 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
589 8 gdevic 
    if (M4 & T2) begin fMRead=1;
590 6 gdevic 
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
591 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
592 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
593 8 gdevic 
    if (M4 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
594 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
595 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
596 
                    ctl_sw_2d=1;
597 
                    ctl_sw_1d=1;
598 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
599 
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
600 8 gdevic 
    if (M5 & T1) begin fMRead=1;
601 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
602 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
603 8 gdevic 
    if (M5 & T2) begin fMRead=1;
604 6 gdevic 
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
605 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
606 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
607 8 gdevic 
    if (M5 & T3) begin fMRead=1; setM1=1;
608 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
609 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
610 
                    ctl_sw_2d=1;
611 
                    ctl_sw_1d=1;
612 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
613 
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
614 
end
615 
 
616 
if (pla[5]) begin
617 8 gdevic 
    if (M1 & T4) begin validPLA=1;
618 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
619 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
620 8 gdevic 
    if (M1 & T5) begin
621 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
622 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
623 8 gdevic 
    if (M1 & T6) begin setM1=1; end
624 6 gdevic 
end
625 
 
626 8 gdevic 
if (pla[23] & pla[16]) begin
627 
    if (M1 & T4) begin validPLA=1; end
628 
    if (M1 & T5) begin nextM=1; ctl_mWrite=1;
629 6 gdevic 
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
630 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
631 6 gdevic 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
632 8 gdevic 
    if (M2 & T1) begin fMWrite=1;
633 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
634 6 gdevic 
                    ctl_apin_mux=1; /* Apin sourced from incrementer */
635 
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
636 8 gdevic 
                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
637 6 gdevic 
                    ctl_sw_2u=1;
638 
                    ctl_sw_1u=1;
639 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
640 8 gdevic 
    if (M2 & T2) begin fMWrite=1;
641 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
642 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
643 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
644 8 gdevic 
    if (M2 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
645 6 gdevic 
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
646 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
647 6 gdevic 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
648 8 gdevic 
    if (M3 & T1) begin fMWrite=1;
649 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
650 6 gdevic 
                    ctl_apin_mux=1; /* Apin sourced from incrementer */
651 
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
652 8 gdevic 
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
653 6 gdevic 
                    ctl_sw_1u=1;
654 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
655 8 gdevic 
    if (M3 & T2) begin fMWrite=1;
656 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
657 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
658 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
659 8 gdevic 
    if (M3 & T3) begin fMWrite=1; setM1=1; end
660 6 gdevic 
end
661 
 
662 8 gdevic 
if (pla[23] & ~pla[16]) begin
663 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
664 
    if (M2 & T1) begin fMRead=1;
665 6 gdevic 
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
666 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
667 8 gdevic 
    if (M2 & T2) begin fMRead=1;
668 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
669 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
670 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
671 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
672 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
673 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
674 
                    ctl_sw_2d=1;
675 
                    ctl_sw_1d=1;
676 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
677 8 gdevic 
    if (M3 & T1) begin fMRead=1;
678 6 gdevic 
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
679 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
680 8 gdevic 
    if (M3 & T2) begin fMRead=1;
681 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
682 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
683 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
684 8 gdevic 
    if (M3 & T3) begin fMRead=1; setM1=1;
685 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
686 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
687 
                    ctl_sw_2d=1;
688 
                    ctl_sw_1d=1;
689 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
690 
end
691 
 
692 
// Exchange, Block Transfer and Search Groups
693 
if (pla[2]) begin
694 8 gdevic 
    if (M1 & T2) begin
695 6 gdevic 
                    ctl_reg_ex_de_hl=1; /* EX DE,HL */ end
696 8 gdevic 
    if (M1 & T4) begin validPLA=1; setM1=1; end
697 6 gdevic 
end
698 
 
699 
if (pla[39]) begin
700 8 gdevic 
    if (M1 & T2) begin
701 6 gdevic 
                    ctl_reg_ex_af=1; /* EX AF,AF' */ end
702 8 gdevic 
    if (M1 & T4) begin validPLA=1; setM1=1; end
703 6 gdevic 
end
704 
 
705 
if (pla[1]) begin
706 8 gdevic 
    if (M1 & T2) begin
707 6 gdevic 
                    ctl_reg_exx=1; /* EXX */ end
708 8 gdevic 
    if (M1 & T4) begin validPLA=1; setM1=1; end
709 6 gdevic 
end
710 
 
711 
if (pla[10]) begin
712 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
713 
    if (M2 & T1) begin fMRead=1;
714 6 gdevic 
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
715 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
716 8 gdevic 
    if (M2 & T2) begin fMRead=1;
717 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
718 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
719 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
720 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
721 
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
722 6 gdevic 
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
723 
                    ctl_sw_2d=1;
724 
                    ctl_sw_1d=1;
725 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
726 8 gdevic 
    if (M3 & T1) begin fMRead=1;
727 6 gdevic 
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
728 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
729 8 gdevic 
    if (M3 & T2) begin fMRead=1;
730 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
731 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
732 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
733 8 gdevic 
    if (M3 & T3) begin fMRead=1;
734 
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
735 6 gdevic 
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
736 
                    ctl_sw_2d=1;
737 
                    ctl_sw_1d=1;
738 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
739 8 gdevic 
    if (M3 & T4) begin nextM=1; ctl_mWrite=1;
740 6 gdevic 
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
741 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
742 6 gdevic 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
743 8 gdevic 
    if (M4 & T1) begin fMWrite=1;
744 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
745 6 gdevic 
                    ctl_apin_mux=1; /* Apin sourced from incrementer */
746 
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
747 8 gdevic 
                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
748 6 gdevic 
                    ctl_sw_2u=1;
749 
                    ctl_sw_1u=1;
750 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
751 8 gdevic 
    if (M4 & T2) begin fMWrite=1;
752 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
753 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
754 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
755 8 gdevic 
    if (M4 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
756 6 gdevic 
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
757 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
758 6 gdevic 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
759 8 gdevic 
    if (M5 & T1) begin fMWrite=1;
760 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
761 6 gdevic 
                    ctl_apin_mux=1; /* Apin sourced from incrementer */
762 
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
763 8 gdevic 
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
764 6 gdevic 
                    ctl_sw_1u=1;
765 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
766 8 gdevic 
    if (M5 & T2) begin fMWrite=1;
767 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
768 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
769 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
770 8 gdevic 
    if (M5 & T3) begin fMWrite=1;
771 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
772 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
773 8 gdevic 
    if (M5 & T4) begin
774 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
775 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
776 8 gdevic 
    if (M5 & T5) begin setM1=1; end
777 6 gdevic 
end
778 
 
779 
if (pla[0]) begin
780 8 gdevic 
    begin nonRep=1; /* Non-repeating block instruction */ end
781 6 gdevic 
end
782 
 
783 
if (pla[12]) begin
784 8 gdevic 
    if (M1 & T1) begin
785 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
786 
                    ctl_alu_res_oe=1; /* Result latch */
787 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
788 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
789 
                    ctl_flags_xy_we=1;
790 
                    ctl_flags_hf_we=1;
791 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_REP;
792 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
793 
                    ctl_flags_use_cf2=1; end
794 8 gdevic 
    if (M1 & T2) begin
795 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
796 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
797 
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
798 8 gdevic 
    if (M1 & T3) begin
799 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
800 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
801 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
802 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
803 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
804 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
805 
                    ctl_flags_sz_we=1;
806 
                    ctl_flags_xy_we=1;
807 
                    ctl_flags_hf_we=1;
808 
                    ctl_flags_pf_we=1;
809 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
810 
                    ctl_flags_cf_we=1; end
811 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
812 
    if (M2 & T1) begin fMRead=1;
813 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
814 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
815 8 gdevic 
    if (M2 & T2) begin fMRead=1;
816 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
817 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
818 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
819 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
820 6 gdevic 
                    ctl_sw_2d=1;
821 
                    ctl_sw_1d=1;
822 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
823 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
824 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
825 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
826 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
827 8 gdevic 
                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
828 6 gdevic 
                    ctl_flags_hf_we=1;
829 8 gdevic 
                    ctl_flags_cf2_we=1; end
830 
    if (M3 & T1) begin fMWrite=1;
831 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_DE; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit DE, enable SW4 downstream */
832 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
833 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
834 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
835 
                    ctl_alu_res_oe=1; /* Result latch */
836 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
837 8 gdevic 
                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
838 6 gdevic 
                    ctl_flags_use_cf2=1; end
839 8 gdevic 
    if (M3 & T2) begin fMWrite=1;
840 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_DE; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */
841 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
842 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
843 8 gdevic 
    if (M3 & T3) begin fMWrite=1;
844 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */
845 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
846 8 gdevic 
    if (M3 & T4) begin
847 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */
848 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
849 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
850 
                    ctl_repeat_we=1; /* Update repeating flag latch with BC=1 status */ end
851 8 gdevic 
    if (M3 & T5) begin nextM=1; setM1=nonRep | ~repeat_en; end
852 
    if (M4 & T1) begin
853 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
854 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
855 8 gdevic 
    if (M4 & T2) begin
856 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
857 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
858 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
859 8 gdevic 
    if (M4 & T3) begin
860 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
861 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
862 8 gdevic 
    if (M4 & T4) begin
863 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
864 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
865 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
866 8 gdevic 
    if (M4 & T5) begin setM1=1; end
867 6 gdevic 
end
868 
 
869 
if (pla[11]) begin
870 8 gdevic 
    if (M1 & T1) begin
871 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
872 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
873 
                    ctl_alu_res_oe=1; /* Result latch */
874 
                    ctl_alu_op1_sel_zero=1; /* Zero */
875 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
876 8 gdevic 
                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
877 6 gdevic 
                    ctl_flags_xy_we=1;
878 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_REP;
879 
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
880 
                    ctl_flags_use_cf2=1; end
881 8 gdevic 
    if (M1 & T2) begin
882 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
883 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
884 
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
885 
                    ctl_flags_hf_cpl=flags_nf; end
886 8 gdevic 
    if (M1 & T3) begin
887 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
888 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
889 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
890 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
891 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
892 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
893 
                    ctl_flags_sz_we=1;
894 
                    ctl_flags_xy_we=1;
895 
                    ctl_flags_hf_we=1;
896 
                    ctl_flags_pf_we=1;
897 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
898 
                    ctl_flags_cf_we=1; end
899 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
900 
    if (M2 & T1) begin fMRead=1;
901 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
902 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
903 8 gdevic 
    if (M2 & T2) begin fMRead=1;
904 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
905 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
906 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
907 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1;
908 6 gdevic 
                    ctl_sw_2d=1;
909 
                    ctl_sw_1d=1;
910 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
911 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
912 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
913 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
914 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
915 8 gdevic 
                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
916 6 gdevic 
                    ctl_flags_hf_we=1;
917 8 gdevic 
                    ctl_flags_cf2_we=1; end
918 
    if (M3 & T1) begin
919 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
920 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
921 
                    ctl_alu_res_oe=1; /* Result latch */
922 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
923 8 gdevic 
                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
924 6 gdevic 
                    ctl_flags_sz_we=1;
925 
                    ctl_flags_use_cf2=1; end
926 8 gdevic 
    if (M3 & T3) begin
927 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */
928 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
929 8 gdevic 
    if (M3 & T4) begin
930 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */
931 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
932 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
933 
                    ctl_repeat_we=1; /* Update repeating flag latch with BC=1 status */ end
934 8 gdevic 
    if (M3 & T5) begin nextM=1; setM1=nonRep | ~repeat_en | flags_zf; end
935 
    if (M4 & T1) begin
936 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
937 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
938 8 gdevic 
    if (M4 & T2) begin
939 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
940 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
941 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
942 8 gdevic 
    if (M4 & T3) begin
943 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
944 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
945 8 gdevic 
    if (M4 & T4) begin
946 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
947 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
948 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
949 8 gdevic 
    if (M4 & T5) begin setM1=1; end
950 6 gdevic 
end
951 
 
952 
// 8-bit Arithmetic and Logic Group
953 8 gdevic 
if (pla[65] & ~pla[52]) begin
954 
    if (M1 & T1) begin /* Which register to be written is decided elsewhere */
955 6 gdevic 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
956 
                    ctl_sw_2u=1;
957 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
958 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
959 
                    ctl_alu_res_oe=1; /* Result latch */
960 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
961 
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
962 
                    ctl_flags_sz_we=1;
963 
                    ctl_flags_cf_we=1; end
964 8 gdevic 
    if (M1 & T2) begin
965 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
966 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
967 
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
968 
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
969 
                    ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
970 8 gdevic 
    if (M1 & T3) begin
971 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
972 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
973 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
974 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
975 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
976 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
977 
                    ctl_flags_sz_we=1;
978 
                    ctl_flags_xy_we=1;
979 
                    ctl_flags_hf_we=1;
980 
                    ctl_flags_pf_we=1;
981 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
982 
                    ctl_flags_cf_we=1; end
983 8 gdevic 
    if (M1 & T4) begin validPLA=1; setM1=1;
984 
                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
985 
                    ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
986 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
987 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
988 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
989 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
990 
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
991 
                    ctl_flags_sz_we=1;
992 
                    ctl_flags_xy_we=1;
993 
                    ctl_flags_hf_we=1; end
994 
end
995 
 
996 
if (pla[64]) begin
997 8 gdevic 
    if (M1 & T1) begin /* Which register to be written is decided elsewhere */
998 6 gdevic 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
999 
                    ctl_sw_2u=1;
1000 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1001 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1002 
                    ctl_alu_res_oe=1; /* Result latch */
1003 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1004 
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1005 
                    ctl_flags_sz_we=1;
1006 
                    ctl_flags_cf_we=1; end
1007 8 gdevic 
    if (M1 & T2) begin
1008 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1009 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1010 
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1011 
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1012 
                    ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
1013 8 gdevic 
    if (M1 & T3) begin
1014 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1015 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1016 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1017 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1018 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1019 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1020 
                    ctl_flags_sz_we=1;
1021 
                    ctl_flags_xy_we=1;
1022 
                    ctl_flags_hf_we=1;
1023 
                    ctl_flags_pf_we=1;
1024 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1025 
                    ctl_flags_cf_we=1; end
1026 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1;
1027 
                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
1028 
                    ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
1029 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1030 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1031 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1032 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1033 
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1034 
                    ctl_flags_sz_we=1;
1035 
                    ctl_flags_xy_we=1;
1036 
                    ctl_flags_hf_we=1; end
1037 8 gdevic 
    if (M2 & T1) begin fMRead=1;
1038 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
1039 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
1040 
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ end
1041 8 gdevic 
    if (M2 & T2) begin fMRead=1;
1042 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
1043 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
1044 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1045 8 gdevic 
    if (M2 & T3) begin fMRead=1; setM1=1;
1046 6 gdevic 
                    ctl_sw_2d=1;
1047 
                    ctl_sw_1d=1;
1048 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
1049 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1050 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1051 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1052 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1053 
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1054 
                    ctl_flags_sz_we=1;
1055 
                    ctl_flags_xy_we=1;
1056 
                    ctl_flags_hf_we=1; end
1057 
end
1058 
 
1059 8 gdevic 
if (use_ixiy & pla[52]) begin
1060 
    if (M1 & T3) begin
1061 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1062 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1063 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1064 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1065 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1066 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1067 
                    ctl_flags_sz_we=1;
1068 
                    ctl_flags_xy_we=1;
1069 
                    ctl_flags_hf_we=1;
1070 
                    ctl_flags_pf_we=1;
1071 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1072 
                    ctl_flags_cf_we=1; end
1073 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
1074 
    if (M2 & T1) begin fMRead=1;
1075 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
1076 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
1077 8 gdevic 
    if (M2 & T2) begin fMRead=1;
1078 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
1079 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
1080 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1081 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; end
1082 
    if (M3 & T1) begin ixy_d=1; /* Compute WZ=IX+d */ end
1083 
    if (M3 & T2) begin ixy_d=1; /* Compute WZ=IX+d */ end
1084 
    if (M3 & T3) begin ixy_d=1; /* Compute WZ=IX+d */ end
1085 
    if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
1086 
    if (M3 & T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
1087 6 gdevic 
end
1088 
 
1089 8 gdevic 
if (~use_ixiy & pla[52]) begin
1090 
    if (M1 & T1) begin /* Which register to be written is decided elsewhere */
1091 6 gdevic 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1092 
                    ctl_sw_2u=1;
1093 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1094 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1095 
                    ctl_alu_res_oe=1; /* Result latch */
1096 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1097 
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1098 
                    ctl_flags_sz_we=1;
1099 
                    ctl_flags_cf_we=1; end
1100 8 gdevic 
    if (M1 & T2) begin
1101 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1102 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1103 
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1104 
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1105 
                    ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
1106 8 gdevic 
    if (M1 & T3) begin
1107 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1108 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1109 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1110 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1111 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1112 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1113 
                    ctl_flags_sz_we=1;
1114 
                    ctl_flags_xy_we=1;
1115 
                    ctl_flags_hf_we=1;
1116 
                    ctl_flags_pf_we=1;
1117 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1118 
                    ctl_flags_cf_we=1; end
1119 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
1120 
    if (M2 & T1) begin fMRead=1;
1121 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
1122 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
1123 8 gdevic 
    if (M2 & T2) begin fMRead=1;
1124 6 gdevic 
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
1125 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
1126 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1127 8 gdevic 
    if (M2 & T3) begin fMRead=1; setM1=1;
1128 6 gdevic 
                    ctl_sw_2d=1;
1129 
                    ctl_sw_1d=1;
1130 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
1131 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1132 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1133 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1134 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1135 
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1136 
                    ctl_flags_sz_we=1;
1137 
                    ctl_flags_xy_we=1;
1138 
                    ctl_flags_hf_we=1; end
1139 8 gdevic 
    if (M4 & T1) begin fMRead=1;
1140 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1141 8 gdevic 
    if (M4 & T2) begin fMRead=1;
1142 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1143 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1144 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1145 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1146 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1147 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1148 
                    ctl_flags_sz_we=1;
1149 
                    ctl_flags_xy_we=1;
1150 
                    ctl_flags_hf_we=1;
1151 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1152 
                    ctl_flags_cf_we=1; end
1153 8 gdevic 
    if (M4 & T3) begin fMRead=1; setM1=1;
1154 6 gdevic 
                    ctl_sw_2d=1;
1155 
                    ctl_sw_1d=1;
1156 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
1157 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1158 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1159 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1160 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1161 
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1162 
                    ctl_flags_sz_we=1;
1163 
                    ctl_flags_xy_we=1;
1164 
                    ctl_flags_hf_we=1; end
1165 
end
1166 
 
1167 8 gdevic 
if (pla[66] & ~pla[53]) begin
1168 
    if (M1 & T1) begin
1169 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
1170 6 gdevic 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1171 
                    ctl_sw_2u=1;
1172 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1173 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1174 
                    ctl_alu_res_oe=1; /* Result latch */
1175 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1176 8 gdevic 
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1177 6 gdevic 
                    ctl_flags_sz_we=1;
1178 
                    ctl_flags_xy_we=1;
1179 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
1180 
                    ctl_flags_use_cf2=1; end
1181 8 gdevic 
    if (M1 & T2) begin
1182 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1183 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1184 
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1185 
                    ctl_flags_hf_cpl=flags_nf; end
1186 8 gdevic 
    if (M1 & T3) begin
1187 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1188 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1189 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1190 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1191 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1192 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1193 
                    ctl_flags_sz_we=1;
1194 
                    ctl_flags_xy_we=1;
1195 
                    ctl_flags_hf_we=1;
1196 
                    ctl_flags_pf_we=1;
1197 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1198 
                    ctl_flags_cf_we=1; end
1199 8 gdevic 
    if (M1 & T4) begin validPLA=1; setM1=1;
1200 
        if (op4 & op5 & ~op3) begin ctl_bus_zero_oe=1; end  /* Trying to read flags? Put 0 on the bus instead. */
1201 
        if (~(op4 & op5 & ~op3)) begin ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; end /* Read 8-bit GP register */
1202 
                    ctl_reg_out_hi=~rsel3; ctl_reg_out_lo=rsel3; ctl_sw_2u=~rsel3; ctl_sw_2d=rsel3; /* Enable register gate based on the rsel3 */ /* Controlled by register gate */
1203 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1204 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1205 6 gdevic 
                    ctl_alu_op2_sel_zero=1; /* Zero */
1206 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1207 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1208 8 gdevic 
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1209 6 gdevic 
                    ctl_flags_sz_we=1;
1210 
                    ctl_flags_xy_we=1;
1211 
                    ctl_flags_hf_we=1;
1212 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
1213 
                    ctl_flags_cf_set=1; /* Set CF going into the ALU core */
1214 8 gdevic 
                    ctl_flags_cf2_we=1; end
1215 6 gdevic 
end
1216 
 
1217 
if (pla[75]) begin
1218 8 gdevic 
    if (M1 & T1) begin
1219 6 gdevic 
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
1220 
                    ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */
1221 
                    ctl_alu_sel_op2_neg=1; end
1222 8 gdevic 
    if (M1 & T4) begin
1223 6 gdevic 
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
1224 
                    ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */
1225 
                    ctl_alu_sel_op2_neg=1; end
1226 
end
1227 
 
1228 8 gdevic 
if ((M2 | M4) & pla[75]) begin
1229 
    begin
1230 6 gdevic 
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
1231 
                    ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */
1232 
                    ctl_alu_sel_op2_neg=1; end
1233 
end
1234 
 
1235 8 gdevic 
if (use_ixiy & pla[53]) begin
1236 
    if (M1 & T3) begin
1237 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1238 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1239 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1240 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1241 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1242 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1243 
                    ctl_flags_sz_we=1;
1244 
                    ctl_flags_xy_we=1;
1245 
                    ctl_flags_hf_we=1;
1246 
                    ctl_flags_pf_we=1;
1247 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1248 
                    ctl_flags_cf_we=1; end
1249 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
1250 
    if (M2 & T1) begin fMRead=1;
1251 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
1252 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
1253 8 gdevic 
    if (M2 & T2) begin fMRead=1;
1254 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
1255 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
1256 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1257 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; end
1258 
    if (M3 & T1) begin ixy_d=1; /* Compute WZ=IX+d */ end
1259 
    if (M3 & T2) begin ixy_d=1; /* Compute WZ=IX+d */ end
1260 
    if (M3 & T3) begin ixy_d=1; /* Compute WZ=IX+d */ end
1261 
    if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
1262 
    if (M3 & T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
1263 6 gdevic 
end
1264 
 
1265 8 gdevic 
if (~use_ixiy & pla[53]) begin
1266 
    if (M1 & T2) begin
1267 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1268 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1269 
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1270 
                    ctl_flags_hf_cpl=flags_nf; end
1271 8 gdevic 
    if (M1 & T3) begin
1272 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1273 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1274 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1275 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1276 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1277 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1278 
                    ctl_flags_sz_we=1;
1279 
                    ctl_flags_xy_we=1;
1280 
                    ctl_flags_hf_we=1;
1281 
                    ctl_flags_pf_we=1;
1282 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1283 
                    ctl_flags_cf_we=1; end
1284 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
1285 
    if (M2 & T1) begin fMRead=1;
1286 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
1287 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
1288 8 gdevic 
    if (M2 & T2) begin fMRead=1; end
1289 
    if (M2 & T3) begin fMRead=1;
1290 6 gdevic 
                    ctl_sw_2d=1;
1291 
                    ctl_sw_1d=1;
1292 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
1293 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1294 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1295 6 gdevic 
                    ctl_alu_op2_sel_zero=1; /* Zero */
1296 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1297 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1298 8 gdevic 
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1299 6 gdevic 
                    ctl_flags_hf_we=1;
1300 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
1301 
                    ctl_flags_cf_set=1; /* Set CF going into the ALU core */
1302 8 gdevic 
                    ctl_flags_cf2_we=1; end
1303 
    if (M2 & T4) begin nextM=1; ctl_mWrite=1;
1304 6 gdevic 
                    ctl_sw_2u=1;
1305 
                    ctl_sw_1u=1;
1306 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
1307 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1308 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1309 
                    ctl_alu_res_oe=1; /* Result latch */
1310 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1311 8 gdevic 
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1312 6 gdevic 
                    ctl_flags_sz_we=1;
1313 
                    ctl_flags_xy_we=1;
1314 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
1315 
                    ctl_flags_use_cf2=1; end
1316 8 gdevic 
    if (M3 & T1) begin fMWrite=1;
1317 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1318 8 gdevic 
    if (M3 & T2) begin fMWrite=1; end
1319 
    if (M3 & T3) begin fMWrite=1; setM1=1; end
1320 
    if (M4 & T1) begin fMRead=1;
1321 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1322 8 gdevic 
    if (M4 & T2) begin fMRead=1; end
1323 
    if (M4 & T3) begin fMRead=1;
1324 6 gdevic 
                    ctl_sw_2d=1;
1325 
                    ctl_sw_1d=1;
1326 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
1327 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1328 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1329 6 gdevic 
                    ctl_alu_op2_sel_zero=1; /* Zero */
1330 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1331 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1332 8 gdevic 
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1333 6 gdevic 
                    ctl_flags_hf_we=1;
1334 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
1335 
                    ctl_flags_cf_set=1; /* Set CF going into the ALU core */
1336 8 gdevic 
                    ctl_flags_cf2_we=1; end
1337 
    if (M4 & T4) begin nextM=1; ctl_mWrite=1;
1338 6 gdevic 
                    ctl_sw_2u=1;
1339 
                    ctl_sw_1u=1;
1340 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
1341 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1342 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1343 
                    ctl_alu_res_oe=1; /* Result latch */
1344 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1345 8 gdevic 
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1346 6 gdevic 
                    ctl_flags_sz_we=1;
1347 
                    ctl_flags_xy_we=1;
1348 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
1349 
                    ctl_flags_use_cf2=1; end
1350 8 gdevic 
    if (M5 & T1) begin fMWrite=1;
1351 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1352 8 gdevic 
    if (M5 & T2) begin fMWrite=1; end
1353 
    if (M5 & T3) begin fMWrite=1; setM1=1; end
1354 6 gdevic 
end
1355 
 
1356 
// 16-bit Arithmetic Group
1357 
if (pla[69]) begin
1358 8 gdevic 
    if (M1 & T2) begin
1359 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1360 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1361 
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
1362 8 gdevic 
    if (M1 & T3) begin
1363 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1364 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1365 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1366 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1367 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1368 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1369 
                    ctl_flags_sz_we=1;
1370 
                    ctl_flags_xy_we=1;
1371 
                    ctl_flags_hf_we=1;
1372 
                    ctl_flags_pf_we=1;
1373 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
1374 
                    ctl_flags_cf_we=1; end
1375 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1;
1376 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;
1377 8 gdevic 
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
1378 6 gdevic 
                    ctl_sw_2d=1;
1379 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1380 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end
1381 8 gdevic 
    if (M2 & T1) begin
1382 6 gdevic 
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
1383 8 gdevic 
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
1384 6 gdevic 
                    ctl_sw_2d=1;
1385 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1386 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1387 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1388 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1389 8 gdevic 
                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
1390 6 gdevic 
                    ctl_flags_hf_we=1;
1391 
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
1392 8 gdevic 
    if (M2 & T2) begin
1393 
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
1394 6 gdevic 
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
1395 
                    ctl_sw_2u=1;
1396 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1397 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1398 
                    ctl_alu_res_oe=1; /* Result latch */
1399 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1400 8 gdevic 
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1401 6 gdevic 
                    ctl_flags_xy_we=1;
1402 
                    ctl_flags_cf_we=1; end
1403 8 gdevic 
    if (M2 & T3) begin
1404 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;
1405 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1406 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1407 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end
1408 8 gdevic 
    if (M2 & T4) begin nextM=1;
1409 6 gdevic 
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
1410 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1411 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1412 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1413 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1414 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1415 8 gdevic 
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1416 6 gdevic 
                    ctl_flags_hf_we=1;
1417 
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
1418 8 gdevic 
    if (M3 & T1) begin
1419 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
1420 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
1421 8 gdevic 
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
1422 6 gdevic 
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
1423 
                    ctl_sw_2u=1;
1424 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1425 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1426 
                    ctl_alu_res_oe=1; /* Result latch */
1427 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1428 8 gdevic 
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1429 6 gdevic 
                    ctl_flags_xy_we=1;
1430 
                    ctl_flags_cf_we=1; end
1431 8 gdevic 
    if (M3 & T2) begin
1432 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
1433 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1434 8 gdevic 
    if (M3 & T3) begin setM1=1; end
1435 6 gdevic 
end
1436 
 
1437 8 gdevic 
if (op3 & pla[68]) begin
1438 
    if (M1 & T2) begin
1439 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1440 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1441 
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
1442 8 gdevic 
    if (M1 & T3) begin
1443 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1444 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1445 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1446 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1447 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1448 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1449 
                    ctl_flags_sz_we=1;
1450 
                    ctl_flags_xy_we=1;
1451 
                    ctl_flags_hf_we=1;
1452 
                    ctl_flags_pf_we=1;
1453 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
1454 
                    ctl_flags_cf_we=1; end
1455 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1;
1456 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;
1457 8 gdevic 
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
1458 6 gdevic 
                    ctl_sw_2d=1;
1459 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1460 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end
1461 8 gdevic 
    if (M2 & T1) begin
1462 6 gdevic 
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
1463 8 gdevic 
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
1464 6 gdevic 
                    ctl_sw_2d=1;
1465 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1466 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1467 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1468 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1469 8 gdevic 
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1470 6 gdevic 
                    ctl_flags_hf_we=1;
1471 
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
1472 8 gdevic 
    if (M2 & T2) begin
1473 
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
1474 6 gdevic 
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
1475 
                    ctl_sw_2u=1;
1476 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1477 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1478 
                    ctl_alu_res_oe=1; /* Result latch */
1479 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1480 8 gdevic 
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1481 6 gdevic 
                    ctl_flags_sz_we=1;
1482 
                    ctl_flags_xy_we=1;
1483 
                    ctl_flags_cf_we=1; end
1484 8 gdevic 
    if (M2 & T3) begin
1485 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;
1486 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1487 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1488 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end
1489 8 gdevic 
    if (M2 & T4) begin nextM=1;
1490 6 gdevic 
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
1491 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1492 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1493 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1494 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1495 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1496 8 gdevic 
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1497 6 gdevic 
                    ctl_flags_hf_we=1;
1498 
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
1499 8 gdevic 
    if (M3 & T1) begin
1500 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
1501 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
1502 8 gdevic 
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
1503 6 gdevic 
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
1504 
                    ctl_sw_2u=1;
1505 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1506 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1507 
                    ctl_alu_res_oe=1; /* Result latch */
1508 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1509 8 gdevic 
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1510 6 gdevic 
                    ctl_flags_sz_we=1;
1511 
                    ctl_flags_xy_we=1;
1512 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
1513 
                    ctl_flags_cf_we=1;
1514 
                    ctl_alu_zero_16bit=1; /* 16-bit arithmetic operation uses ZF calculated over 2 bytes */ end
1515 8 gdevic 
    if (M3 & T2) begin
1516 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
1517 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1518 8 gdevic 
    if (M3 & T3) begin setM1=1; end
1519 6 gdevic 
end
1520 
 
1521 8 gdevic 
if (~op3 & pla[68]) begin
1522 
    if (M1 & T2) begin
1523 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1524 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1525 
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1526 
                    ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
1527 8 gdevic 
    if (M1 & T3) begin
1528 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1529 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1530 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1531 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1532 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1533 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1534 
                    ctl_flags_sz_we=1;
1535 
                    ctl_flags_xy_we=1;
1536 
                    ctl_flags_hf_we=1;
1537 
                    ctl_flags_pf_we=1;
1538 
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
1539 
                    ctl_flags_cf_we=1; end
1540 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1;
1541 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;
1542 8 gdevic 
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
1543 6 gdevic 
                    ctl_sw_2d=1;
1544 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1545 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end
1546 8 gdevic 
    if (M2 & T1) begin
1547 6 gdevic 
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
1548 8 gdevic 
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
1549 6 gdevic 
                    ctl_sw_2d=1;
1550 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1551 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1552 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1553 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1554 8 gdevic 
                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
1555 6 gdevic 
                    ctl_flags_hf_we=1;
1556 
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
1557 8 gdevic 
    if (M2 & T2) begin
1558 
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
1559 6 gdevic 
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
1560 
                    ctl_sw_2u=1;
1561 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1562 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1563 
                    ctl_alu_res_oe=1; /* Result latch */
1564 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1565 8 gdevic 
                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
1566 6 gdevic 
                    ctl_flags_sz_we=1;
1567 
                    ctl_flags_xy_we=1;
1568 
                    ctl_flags_cf_we=1; end
1569 8 gdevic 
    if (M2 & T3) begin
1570 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;
1571 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1572 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1573 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end
1574 8 gdevic 
    if (M2 & T4) begin nextM=1;
1575 6 gdevic 
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
1576 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1577 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1578 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1579 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1580 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1581 8 gdevic 
                    ctl_alu_sel_op2_neg=1; ctl_alu_core_hf|=~ctl_alu_op_low;
1582 6 gdevic 
                    ctl_flags_hf_we=1;
1583 
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
1584 8 gdevic 
    if (M3 & T1) begin
1585 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
1586 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
1587 8 gdevic 
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
1588 6 gdevic 
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
1589 
                    ctl_sw_2u=1;
1590 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1591 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1592 
                    ctl_alu_res_oe=1; /* Result latch */
1593 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1594 8 gdevic 
                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
1595 6 gdevic 
                    ctl_flags_sz_we=1;
1596 
                    ctl_flags_xy_we=1;
1597 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
1598 
                    ctl_flags_cf_we=1;
1599 
                    ctl_alu_zero_16bit=1; /* 16-bit arithmetic operation uses ZF calculated over 2 bytes */ end
1600 8 gdevic 
    if (M3 & T2) begin
1601 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
1602 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1603 8 gdevic 
    if (M3 & T3) begin setM1=1; end
1604 6 gdevic 
end
1605 
 
1606 
if (pla[9]) begin
1607 8 gdevic 
    if (M1 & T4) begin validPLA=1;
1608 6 gdevic 
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */
1609 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
1610 
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
1611 8 gdevic 
    if (M1 & T5) begin
1612 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit general purpose register, enable SW4 upstream */
1613 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
1614 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
1615 
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
1616 8 gdevic 
    if (M1 & T6) begin setM1=1; end
1617 6 gdevic 
end
1618 
 
1619 
// General Purpose Arithmetic and CPU Control Groups
1620 
if (pla[77]) begin
1621 8 gdevic 
    if (M1 & T1) begin
1622 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
1623 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1624 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1625 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1626 
                    ctl_alu_res_oe=1; /* Result latch */
1627 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1628 8 gdevic 
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1629 6 gdevic 
                    ctl_flags_sz_we=1;
1630 
                    ctl_flags_xy_we=1;
1631 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
1632 
                    ctl_flags_cf_we=1;
1633 8 gdevic 
                    ctl_alu_sel_op2_neg=flags_nf; ctl_flags_cf_cpl=~flags_nf; end
1634 
    if (M1 & T2) begin
1635 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1636 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1637 
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1638 
                    ctl_flags_use_cf2=1;
1639 
                    ctl_flags_hf_cpl=flags_nf; end
1640 8 gdevic 
    if (M1 & T3) begin
1641 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1642 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1643 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1644 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1645 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1646 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1647 
                    ctl_flags_sz_we=1;
1648 
                    ctl_flags_xy_we=1;
1649 
                    ctl_flags_hf2_we=1; /* Write HF2 flag (DAA only) */
1650 
                    ctl_flags_pf_we=1;
1651 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1652 
                    ctl_flags_cf_we=1; end
1653 8 gdevic 
    if (M1 & T4) begin validPLA=1; setM1=1;
1654 6 gdevic 
                    ctl_sw_2d=1;
1655 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1656 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1657 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1658 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1659 8 gdevic 
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1660 6 gdevic 
                    ctl_flags_sz_we=1;
1661 
                    ctl_flags_xy_we=1;
1662 
                    ctl_flags_hf_we=1;
1663 8 gdevic 
                    ctl_flags_cf_set=1; /* Set CF going into the ALU core */
1664 
                    ctl_flags_cf2_we=1; ctl_flags_cf2_sel_daa=1;
1665 6 gdevic 
                    ctl_daa_oe=1; /* Write DAA correction factor to the bus */
1666 8 gdevic 
                    ctl_alu_sel_op2_neg=flags_nf; ctl_flags_cf_cpl=~flags_nf; end
1667 6 gdevic 
end
1668 
 
1669 
if (pla[81]) begin
1670 8 gdevic 
    if (M1 & T1) begin
1671 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
1672 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1673 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1674 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1675 
                    ctl_alu_res_oe=1; /* Result latch */
1676 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1677 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
1678 
                    ctl_flags_xy_we=1;
1679 
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
1680 
                    ctl_alu_sel_op2_neg=1; end
1681 8 gdevic 
    if (M1 & T2) begin
1682 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1683 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1684 
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1685 
                    ctl_flags_hf_cpl=flags_nf; end
1686 8 gdevic 
    if (M1 & T3) begin
1687 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1688 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1689 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1690 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1691 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1692 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1693 
                    ctl_flags_sz_we=1;
1694 
                    ctl_flags_xy_we=1;
1695 
                    ctl_flags_hf_we=1;
1696 
                    ctl_flags_pf_we=1;
1697 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1698 
                    ctl_flags_cf_we=1; end
1699 8 gdevic 
    if (M1 & T4) begin validPLA=1; setM1=1;
1700 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1701 
                    ctl_alu_op1_sel_zero=1; /* Zero */
1702 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1703 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
1704 
                    ctl_flags_xy_we=1;
1705 
                    ctl_flags_hf_we=1;
1706 
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
1707 
                    ctl_alu_sel_op2_neg=1; end
1708 
end
1709 
 
1710 
if (pla[82]) begin
1711 8 gdevic 
    if (M1 & T1) begin
1712 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
1713 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1714 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1715 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1716 
                    ctl_alu_res_oe=1; /* Result latch */
1717 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1718 8 gdevic 
                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
1719 6 gdevic 
                    ctl_flags_sz_we=1;
1720 
                    ctl_flags_xy_we=1;
1721 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
1722 
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
1723 
                    ctl_flags_cf_we=1; end
1724 8 gdevic 
    if (M1 & T2) begin
1725 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1726 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1727 
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1728 
                    ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
1729 8 gdevic 
    if (M1 & T3) begin
1730 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1731 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1732 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1733 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1734 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1735 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1736 
                    ctl_flags_sz_we=1;
1737 
                    ctl_flags_xy_we=1;
1738 
                    ctl_flags_hf_we=1;
1739 
                    ctl_flags_pf_we=1;
1740 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1741 
                    ctl_flags_cf_we=1; end
1742 8 gdevic 
    if (M1 & T4) begin validPLA=1; setM1=1;
1743 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1744 
                    ctl_alu_op1_sel_zero=1; /* Zero */
1745 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1746 8 gdevic 
                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
1747 6 gdevic 
                    ctl_flags_sz_we=1;
1748 
                    ctl_flags_xy_we=1;
1749 
                    ctl_flags_hf_we=1;
1750 
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
1751 
                    ctl_flags_cf_we=1; end
1752 
end
1753 
 
1754 
if (pla[89]) begin
1755 8 gdevic 
    if (M1 & T1) begin
1756 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1757 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1758 
                    ctl_alu_res_oe=1; /* Result latch */
1759 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1760 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
1761 
                    ctl_flags_xy_we=1;
1762 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
1763 8 gdevic 
    if (M1 & T2) begin
1764 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1765 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1766 
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1767 
                    ctl_flags_cf_we=1; ctl_flags_cf_cpl=1; /* CCF */
1768 8 gdevic 
                    ctl_flags_hf_cpl=~flags_cf; /* Used for CCF */ end
1769 
    if (M1 & T3) begin
1770 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1771 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1772 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1773 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1774 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1775 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1776 
                    ctl_flags_sz_we=1;
1777 
                    ctl_flags_xy_we=1;
1778 
                    ctl_flags_hf_we=1;
1779 
                    ctl_flags_pf_we=1;
1780 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1781 
                    ctl_flags_cf_we=1; end
1782 8 gdevic 
    if (M1 & T4) begin validPLA=1; setM1=1;
1783 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1784 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1785 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
1786 
                    ctl_flags_xy_we=1;
1787 
                    ctl_flags_hf_we=1;
1788 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
1789 
end
1790 
 
1791 
if (pla[92]) begin
1792 8 gdevic 
    if (M1 & T1) begin
1793 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1794 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1795 
                    ctl_alu_res_oe=1; /* Result latch */
1796 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1797 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
1798 
                    ctl_flags_xy_we=1;
1799 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
1800 8 gdevic 
    if (M1 & T2) begin
1801 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1802 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1803 
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1804 
                    ctl_flags_cf_set=1; /* Set CF going into the ALU core */ end
1805 8 gdevic 
    if (M1 & T3) begin
1806 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1807 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1808 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1809 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1810 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1811 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1812 
                    ctl_flags_sz_we=1;
1813 
                    ctl_flags_xy_we=1;
1814 
                    ctl_flags_hf_we=1;
1815 
                    ctl_flags_pf_we=1;
1816 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1817 
                    ctl_flags_cf_we=1; end
1818 8 gdevic 
    if (M1 & T4) begin validPLA=1; setM1=1;
1819 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1820 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1821 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
1822 
                    ctl_flags_xy_we=1;
1823 
                    ctl_flags_hf_we=1;
1824 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
1825 
end
1826 
 
1827 
if (pla[95]) begin
1828 8 gdevic 
    if (M1 & T3) begin
1829 6 gdevic 
                    ctl_state_halt_set=1; /* Enter HALT state */ end
1830 8 gdevic 
    if (M1 & T4) begin validPLA=1; setM1=1; end
1831 6 gdevic 
end
1832 
 
1833 
if (pla[97]) begin
1834 8 gdevic 
    if (M1 & T3) begin
1835 6 gdevic 
                    ctl_iffx_bit=op3; ctl_iffx_we=1; /* DI/EI */ end
1836 8 gdevic 
    if (M1 & T4) begin validPLA=1; setM1=1;
1837 6 gdevic 
                    ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end
1838 
end
1839 
 
1840 
if (pla[96]) begin
1841 8 gdevic 
    if (M1 & T3) begin
1842 6 gdevic 
                    ctl_sw_1d=1;
1843 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
1844 
                    ctl_im_we=1; /* IM n ('n' is read by opcode[4:3]) */ end
1845 8 gdevic 
    if (M1 & T4) begin validPLA=1; setM1=1; end
1846 6 gdevic 
end
1847 
 
1848 
// Rotate and Shift Group
1849 
if (pla[25]) begin
1850 8 gdevic 
    if (M1 & T1) begin
1851 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
1852 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1853 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1854 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1855 
                    ctl_alu_res_oe=1; /* Result latch */
1856 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1857 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
1858 
                    ctl_flags_xy_we=1;
1859 
                    ctl_flags_hf_we=1;
1860 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
1861 
                    ctl_flags_cf_we=1; end
1862 8 gdevic 
    if (M1 & T2) begin
1863 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1864 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1865 
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1866 
                    ctl_flags_use_cf2=1; end
1867 8 gdevic 
    if (M1 & T3) begin
1868 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1869 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1870 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1871 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1872 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1873 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1874 
                    ctl_flags_sz_we=1;
1875 
                    ctl_flags_xy_we=1;
1876 
                    ctl_flags_hf_we=1;
1877 
                    ctl_flags_pf_we=1;
1878 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1879 
                    ctl_flags_cf_we=1; end
1880 8 gdevic 
    if (M1 & T4) begin validPLA=1; setM1=1;
1881 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
1882 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1883 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1884 
                    ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */
1885 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1886 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1887 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1888 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
1889 
                    ctl_flags_xy_we=1;
1890 
                    ctl_flags_hf_we=1;
1891 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
1892 8 gdevic 
                    ctl_flags_cf2_we=1; ctl_flags_cf2_sel_shift=1; end
1893 6 gdevic 
end
1894 
 
1895 8 gdevic 
if (~use_ixiy & pla[70] & ~pla[55]) begin
1896 
    if (M1 & T1) begin
1897 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0}; /* Write 8-bit GP register selected by op[2:0] */
1898 6 gdevic 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1899 
                    ctl_sw_2u=1;
1900 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1901 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1902 
                    ctl_alu_res_oe=1; /* Result latch */
1903 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1904 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
1905 
                    ctl_flags_sz_we=1;
1906 
                    ctl_flags_xy_we=1;
1907 
                    ctl_flags_hf_we=1;
1908 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
1909 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
1910 
                    ctl_flags_cf_we=1; end
1911 8 gdevic 
    if (M1 & T2) begin
1912 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1913 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1914 
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1915 
                    ctl_flags_use_cf2=1; end
1916 8 gdevic 
    if (M1 & T3) begin
1917 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1918 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1919 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1920 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1921 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1922 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1923 
                    ctl_flags_sz_we=1;
1924 
                    ctl_flags_xy_we=1;
1925 
                    ctl_flags_hf_we=1;
1926 
                    ctl_flags_pf_we=1;
1927 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1928 
                    ctl_flags_cf_we=1; end
1929 8 gdevic 
    if (M1 & T4) begin validPLA=1; setM1=1;
1930 
                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
1931 
                    ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
1932 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1933 
                    ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */
1934 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1935 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1936 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1937 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
1938 
                    ctl_flags_sz_we=1;
1939 
                    ctl_flags_xy_we=1;
1940 
                    ctl_flags_hf_we=1;
1941 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
1942 8 gdevic 
                    ctl_flags_cf2_we=1; ctl_flags_cf2_sel_shift=1; end
1943 
    if (M4 & T1) begin fMRead=1;
1944 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
1945 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
1946 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
1947 
                    ctl_ir_we=1; end
1948 8 gdevic 
    if (M4 & T2) begin fMRead=1; end
1949 
    if (M4 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
1950 6 gdevic 
                    ctl_sw_2d=1;
1951 
                    ctl_sw_1d=1;
1952 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
1953 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1954 
                    ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */
1955 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1956 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1957 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1958 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
1959 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
1960 8 gdevic 
                    ctl_flags_cf2_we=1; ctl_flags_cf2_sel_shift=1; end
1961 
    if (M5 & T1) begin fMWrite=1;
1962 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
1963 
                    ctl_sw_2u=1;
1964 
                    ctl_sw_1u=1;
1965 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
1966 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1967 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1968 
                    ctl_alu_res_oe=1; /* Result latch */
1969 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1970 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
1971 
                    ctl_flags_sz_we=1;
1972 
                    ctl_flags_xy_we=1;
1973 
                    ctl_flags_hf_we=1;
1974 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
1975 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
1976 
                    ctl_flags_cf_we=1; end
1977 8 gdevic 
    if (M5 & T2) begin fMWrite=1; end
1978 
    if (M5 & T3) begin fMWrite=1; setM1=1; end
1979 6 gdevic 
end
1980 
 
1981 8 gdevic 
if (~use_ixiy & pla[70] & pla[55]) begin
1982 
    if (M1 & T2) begin
1983 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1984 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1985 
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1986 
                    ctl_flags_use_cf2=1; end
1987 8 gdevic 
    if (M1 & T3) begin
1988 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1989 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1990 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1991 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1992 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1993 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1994 
                    ctl_flags_sz_we=1;
1995 
                    ctl_flags_xy_we=1;
1996 
                    ctl_flags_hf_we=1;
1997 
                    ctl_flags_pf_we=1;
1998 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1999 
                    ctl_flags_cf_we=1; end
2000 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
2001 
    if (M2 & T1) begin fMRead=1;
2002 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
2003 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
2004 8 gdevic 
    if (M2 & T2) begin fMRead=1; end
2005 
    if (M2 & T3) begin fMRead=1; end
2006 
    if (M2 & T4) begin nextM=1; ctl_mWrite=1;
2007 6 gdevic 
                    ctl_sw_2d=1;
2008 
                    ctl_sw_1d=1;
2009 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2010 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2011 
                    ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */
2012 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2013 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2014 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
2015 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
2016 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
2017 8 gdevic 
                    ctl_flags_cf2_we=1; ctl_flags_cf2_sel_shift=1; end
2018 
    if (M3 & T1) begin fMWrite=1;
2019 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
2020 
                    ctl_sw_2u=1;
2021 
                    ctl_sw_1u=1;
2022 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
2023 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2024 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
2025 
                    ctl_alu_res_oe=1; /* Result latch */
2026 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
2027 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
2028 
                    ctl_flags_sz_we=1;
2029 
                    ctl_flags_xy_we=1;
2030 
                    ctl_flags_hf_we=1;
2031 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
2032 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
2033 
                    ctl_flags_cf_we=1; end
2034 8 gdevic 
    if (M3 & T2) begin fMWrite=1; end
2035 
    if (M3 & T3) begin fMWrite=1; setM1=1; end
2036 
    if (M4 & T1) begin fMRead=1;
2037 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
2038 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
2039 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2040 
                    ctl_ir_we=1; end
2041 8 gdevic 
    if (M4 & T2) begin fMRead=1; end
2042 
    if (M4 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
2043 6 gdevic 
                    ctl_sw_2d=1;
2044 
                    ctl_sw_1d=1;
2045 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2046 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2047 
                    ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */
2048 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2049 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2050 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
2051 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
2052 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
2053 8 gdevic 
                    ctl_flags_cf2_we=1; ctl_flags_cf2_sel_shift=1; end
2054 
    if (M5 & T1) begin fMWrite=1;
2055 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
2056 
                    ctl_sw_2u=1;
2057 
                    ctl_sw_1u=1;
2058 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
2059 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2060 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
2061 
                    ctl_alu_res_oe=1; /* Result latch */
2062 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
2063 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
2064 
                    ctl_flags_sz_we=1;
2065 
                    ctl_flags_xy_we=1;
2066 
                    ctl_flags_hf_we=1;
2067 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
2068 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
2069 
                    ctl_flags_cf_we=1; end
2070 8 gdevic 
    if (M5 & T2) begin fMWrite=1; end
2071 
    if (M5 & T3) begin fMWrite=1; setM1=1; end
2072 6 gdevic 
end
2073 
 
2074 8 gdevic 
if (pla[15] & op3) begin
2075 
    if (M1 & T1) begin
2076 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
2077 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
2078 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2079 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
2080 
                    ctl_alu_res_oe=1; /* Result latch */
2081 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
2082 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
2083 
                    ctl_flags_sz_we=1;
2084 
                    ctl_flags_xy_we=1;
2085 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
2086 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
2087 8 gdevic 
    if (M1 & T2) begin
2088 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
2089 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
2090 
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
2091 8 gdevic 
    if (M1 & T3) begin
2092 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
2093 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
2094 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
2095 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2096 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2097 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2098 
                    ctl_flags_sz_we=1;
2099 
                    ctl_flags_xy_we=1;
2100 
                    ctl_flags_hf_we=1;
2101 
                    ctl_flags_pf_we=1;
2102 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
2103 
                    ctl_flags_cf_we=1; end
2104 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
2105 
    if (M2 & T1) begin fMRead=1;
2106 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
2107 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
2108 8 gdevic 
    if (M2 & T2) begin fMRead=1;
2109 6 gdevic 
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
2110 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
2111 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
2112 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; end
2113 
    if (M3 & T1) begin
2114 6 gdevic 
                    ctl_sw_2d=1;
2115 
                    ctl_sw_1d=1;
2116 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2117 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2118 6 gdevic 
                    ctl_alu_op2_sel_lq=1; /* Cross-bus wire (see schematic) */
2119 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ end
2120 8 gdevic 
    if (M3 & T4) begin nextM=1; ctl_mWrite=1;
2121 6 gdevic 
                    ctl_sw_2d=1;
2122 
                    ctl_sw_1d=1;
2123 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2124 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2125 6 gdevic 
                    ctl_alu_op1_sel_low=1; /* Write low nibble with a high nibble */
2126 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ end
2127 8 gdevic 
    if (M4 & T1) begin fMWrite=1;
2128 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
2129 
                    ctl_sw_2u=1;
2130 
                    ctl_sw_1u=1;
2131 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
2132 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
2133 
                    ctl_alu_op2_oe=1; /* OP2 latch */ end
2134 8 gdevic 
    if (M4 & T2) begin fMWrite=1;
2135 6 gdevic 
                    ctl_alu_op1_oe=1; /* OP1 latch */
2136 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */ end
2137 8 gdevic 
    if (M4 & T3) begin fMWrite=1; setM1=1;
2138 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2139 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
2140 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
2141 
                    ctl_flags_sz_we=1;
2142 
                    ctl_flags_xy_we=1;
2143 
                    ctl_flags_hf_we=1;
2144 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
2145 
end
2146 
 
2147 8 gdevic 
if (pla[15] & ~op3) begin
2148 
    if (M1 & T1) begin
2149 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
2150 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
2151 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2152 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
2153 
                    ctl_alu_res_oe=1; /* Result latch */
2154 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
2155 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
2156 
                    ctl_flags_sz_we=1;
2157 
                    ctl_flags_xy_we=1;
2158 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
2159 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
2160 8 gdevic 
    if (M1 & T2) begin
2161 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
2162 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
2163 
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
2164 8 gdevic 
    if (M1 & T3) begin
2165 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
2166 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
2167 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
2168 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2169 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2170 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2171 
                    ctl_flags_sz_we=1;
2172 
                    ctl_flags_xy_we=1;
2173 
                    ctl_flags_hf_we=1;
2174 
                    ctl_flags_pf_we=1;
2175 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
2176 
                    ctl_flags_cf_we=1; end
2177 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
2178 
    if (M2 & T1) begin fMRead=1;
2179 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
2180 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
2181 8 gdevic 
    if (M2 & T2) begin fMRead=1;
2182 6 gdevic 
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
2183 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
2184 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
2185 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; end
2186 
    if (M3 & T1) begin
2187 6 gdevic 
                    ctl_sw_2d=1;
2188 
                    ctl_sw_1d=1;
2189 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2190 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2191 6 gdevic 
                    ctl_alu_op2_sel_lq=1; /* Cross-bus wire (see schematic) */
2192 
                    ctl_alu_op1_sel_low=1; /* Write low nibble with a high nibble */
2193 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ end
2194 8 gdevic 
    if (M3 & T2) begin
2195 6 gdevic 
                    ctl_sw_2u=1;
2196 
                    ctl_sw_1u=1;
2197 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
2198 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
2199 
                    ctl_alu_op2_oe=1; /* OP2 latch */ end
2200 8 gdevic 
    if (M3 & T3) begin
2201 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
2202 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
2203 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2204 6 gdevic 
                    ctl_alu_op2_sel_lq=1; /* Cross-bus wire (see schematic) */
2205 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ end
2206 8 gdevic 
    if (M3 & T4) begin nextM=1; ctl_mWrite=1;
2207 6 gdevic 
                    ctl_sw_2d=1;
2208 
                    ctl_sw_1d=1;
2209 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2210 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2211 6 gdevic 
                    ctl_alu_op1_sel_low=1; /* Write low nibble with a high nibble */
2212 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ end
2213 8 gdevic 
    if (M4 & T1) begin fMWrite=1;
2214 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
2215 
                    ctl_sw_2u=1;
2216 
                    ctl_sw_1u=1;
2217 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
2218 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
2219 
                    ctl_alu_op2_oe=1; /* OP2 latch */ end
2220 8 gdevic 
    if (M4 & T2) begin fMWrite=1;
2221 6 gdevic 
                    ctl_alu_op1_oe=1; /* OP1 latch */
2222 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */ end
2223 8 gdevic 
    if (M4 & T3) begin fMWrite=1; setM1=1;
2224 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2225 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
2226 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
2227 
                    ctl_flags_sz_we=1;
2228 
                    ctl_flags_xy_we=1;
2229 
                    ctl_flags_hf_we=1;
2230 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
2231 
end
2232 
 
2233 
// Bit Manipulation Group
2234 8 gdevic 
if (~use_ixiy & pla[72] & ~pla[55]) begin
2235 
    if (M1 & T1) begin
2236 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2237 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
2238 
                    ctl_alu_res_oe=1; /* Result latch */
2239 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
2240 8 gdevic 
                    ctl_alu_core_S=1; ctl_flags_cf_set=1;
2241 6 gdevic 
                    ctl_flags_sz_we=1;
2242 
                    ctl_flags_hf_we=1;
2243 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
2244 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
2245 8 gdevic 
    if (M1 & T2) begin
2246 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
2247 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
2248 
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
2249 8 gdevic 
    if (M1 & T3) begin
2250 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
2251 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
2252 6 gdevic 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2253 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
2254 
                    ctl_alu_bs_oe=1; /* Bit-selector unit */
2255 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2256 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2257 
                    ctl_flags_sz_we=1;
2258 
                    ctl_flags_xy_we=1;
2259 
                    ctl_flags_hf_we=1;
2260 
                    ctl_flags_pf_we=1;
2261 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
2262 
                    ctl_flags_cf_we=1; end
2263 8 gdevic 
    if (M1 & T4) begin validPLA=1; setM1=1;
2264 
                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
2265 
                    ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
2266 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2267 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2268 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2269 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
2270 8 gdevic 
                    ctl_alu_core_S=1; ctl_flags_cf_set=1;
2271 6 gdevic 
                    ctl_flags_sz_we=1;
2272 
                    ctl_flags_xy_we=1;
2273 
                    ctl_flags_hf_we=1;
2274 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
2275 8 gdevic 
    if (M4 & T1) begin fMRead=1;
2276 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
2277 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2278 
                    ctl_alu_bs_oe=1; /* Bit-selector unit */
2279 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2280 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2281 
                    ctl_ir_we=1; end
2282 8 gdevic 
    if (M4 & T2) begin fMRead=1; end
2283 
    if (M4 & T3) begin fMRead=1; end
2284 
    if (M4 & T4) begin setM1=1;
2285 6 gdevic 
                    ctl_sw_2d=1;
2286 
                    ctl_sw_1d=1;
2287 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2288 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2289 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2290 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2291 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
2292 8 gdevic 
                    ctl_alu_core_S=1; ctl_flags_cf_set=1;
2293 6 gdevic 
                    ctl_flags_sz_we=1;
2294 
                    ctl_flags_hf_we=1;
2295 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
2296 
end
2297 
 
2298 8 gdevic 
if (~use_ixiy & pla[72] & pla[55]) begin
2299 
    if (M1 & T1) begin
2300 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2301 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
2302 
                    ctl_alu_res_oe=1; /* Result latch */
2303 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
2304 8 gdevic 
                    ctl_alu_core_S=1; ctl_flags_cf_set=1;
2305 6 gdevic 
                    ctl_flags_sz_we=1;
2306 
                    ctl_flags_hf_we=1;
2307 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
2308 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
2309 8 gdevic 
    if (M1 & T2) begin
2310 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
2311 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
2312 
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
2313 8 gdevic 
    if (M1 & T3) begin
2314 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
2315 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
2316 6 gdevic 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2317 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
2318 
                    ctl_alu_bs_oe=1; /* Bit-selector unit */
2319 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2320 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2321 
                    ctl_flags_sz_we=1;
2322 
                    ctl_flags_xy_we=1;
2323 
                    ctl_flags_hf_we=1;
2324 
                    ctl_flags_pf_we=1;
2325 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
2326 
                    ctl_flags_cf_we=1; end
2327 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
2328 
    if (M2 & T1) begin fMRead=1;
2329 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
2330 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
2331 8 gdevic 
    if (M2 & T2) begin fMRead=1; end
2332 
    if (M2 & T3) begin fMRead=1;
2333 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1;
2334 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
2335 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
2336 
                    ctl_flags_xy_we=1; end
2337 8 gdevic 
    if (M2 & T4) begin setM1=1;
2338 6 gdevic 
                    ctl_sw_2d=1;
2339 
                    ctl_sw_1d=1;
2340 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2341 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2342 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2343 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2344 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
2345 8 gdevic 
                    ctl_alu_core_S=1; ctl_flags_cf_set=1;
2346 6 gdevic 
                    ctl_flags_sz_we=1;
2347 
                    ctl_flags_hf_we=1;
2348 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
2349 8 gdevic 
    if (M4 & T1) begin fMRead=1;
2350 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
2351 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
2352 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2353 
                    ctl_alu_bs_oe=1; /* Bit-selector unit */
2354 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2355 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2356 
                    ctl_ir_we=1; end
2357 8 gdevic 
    if (M4 & T2) begin fMRead=1; end
2358 
    if (M4 & T3) begin fMRead=1; end
2359 
    if (M4 & T4) begin setM1=1;
2360 6 gdevic 
                    ctl_sw_2d=1;
2361 
                    ctl_sw_1d=1;
2362 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2363 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2364 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2365 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2366 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
2367 8 gdevic 
                    ctl_alu_core_S=1; ctl_flags_cf_set=1;
2368 6 gdevic 
                    ctl_flags_sz_we=1;
2369 
                    ctl_flags_hf_we=1;
2370 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
2371 
end
2372 
 
2373 8 gdevic 
if (~use_ixiy & pla[74] & ~pla[55]) begin
2374 
    if (M1 & T1) begin
2375 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0}; /* Write 8-bit GP register selected by op[2:0] */
2376 6 gdevic 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
2377 
                    ctl_sw_2u=1;
2378 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
2379 
                    ctl_alu_res_oe=1; /* Result latch */
2380 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
2381 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
2382 8 gdevic 
    if (M1 & T3) begin
2383 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
2384 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
2385 6 gdevic 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2386 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
2387 
                    ctl_alu_bs_oe=1; /* Bit-selector unit */
2388 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2389 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2390 
                    ctl_flags_sz_we=1;
2391 
                    ctl_flags_xy_we=1;
2392 
                    ctl_flags_hf_we=1;
2393 
                    ctl_flags_pf_we=1;
2394 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
2395 
                    ctl_flags_cf_we=1; end
2396 8 gdevic 
    if (M1 & T4) begin validPLA=1; setM1=1;
2397 
                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
2398 
                    ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
2399 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2400 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2401 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
2402 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
2403 8 gdevic 
    if (M4 & T1) begin fMRead=1;
2404 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
2405 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
2406 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2407 
                    ctl_alu_bs_oe=1; /* Bit-selector unit */
2408 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2409 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2410 
                    ctl_ir_we=1; end
2411 8 gdevic 
    if (M4 & T2) begin fMRead=1; end
2412 
    if (M4 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
2413 6 gdevic 
                    ctl_sw_2d=1;
2414 
                    ctl_sw_1d=1;
2415 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2416 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2417 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2418 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2419 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
2420 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
2421 8 gdevic 
    if (M5 & T1) begin fMWrite=1;
2422 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
2423 
                    ctl_sw_2u=1;
2424 
                    ctl_sw_1u=1;
2425 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
2426 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
2427 
                    ctl_alu_res_oe=1; /* Result latch */
2428 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
2429 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
2430 8 gdevic 
    if (M5 & T2) begin fMWrite=1; end
2431 
    if (M5 & T3) begin fMWrite=1; setM1=1; end
2432 6 gdevic 
end
2433 
 
2434 8 gdevic 
if (~use_ixiy & pla[74] & pla[55]) begin
2435 
    if (M1 & T3) begin
2436 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
2437 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
2438 6 gdevic 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2439 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
2440 
                    ctl_alu_bs_oe=1; /* Bit-selector unit */
2441 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2442 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2443 
                    ctl_flags_sz_we=1;
2444 
                    ctl_flags_xy_we=1;
2445 
                    ctl_flags_hf_we=1;
2446 
                    ctl_flags_pf_we=1;
2447 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
2448 
                    ctl_flags_cf_we=1; end
2449 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
2450 
    if (M2 & T1) begin fMRead=1;
2451 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
2452 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
2453 8 gdevic 
    if (M2 & T2) begin fMRead=1; end
2454 
    if (M2 & T3) begin fMRead=1;
2455 6 gdevic 
                    ctl_sw_2d=1;
2456 
                    ctl_sw_1d=1;
2457 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2458 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2459 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2460 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
2461 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
2462 8 gdevic 
    if (M2 & T4) begin nextM=1; ctl_mWrite=1;
2463 6 gdevic 
                    ctl_sw_2u=1;
2464 
                    ctl_sw_1u=1;
2465 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
2466 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
2467 
                    ctl_alu_res_oe=1; /* Result latch */
2468 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
2469 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
2470 8 gdevic 
    if (M3 & T1) begin fMWrite=1;
2471 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
2472 8 gdevic 
    if (M3 & T2) begin fMWrite=1; end
2473 
    if (M3 & T3) begin fMWrite=1; setM1=1; end
2474 
    if (M4 & T1) begin fMRead=1;
2475 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
2476 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
2477 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2478 
                    ctl_alu_bs_oe=1; /* Bit-selector unit */
2479 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2480 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2481 
                    ctl_ir_we=1; end
2482 8 gdevic 
    if (M4 & T2) begin fMRead=1; end
2483 
    if (M4 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
2484 6 gdevic 
                    ctl_sw_2d=1;
2485 
                    ctl_sw_1d=1;
2486 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2487 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2488 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2489 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2490 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
2491 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
2492 8 gdevic 
    if (M5 & T1) begin fMWrite=1;
2493 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
2494 
                    ctl_sw_2u=1;
2495 
                    ctl_sw_1u=1;
2496 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
2497 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
2498 
                    ctl_alu_res_oe=1; /* Result latch */
2499 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
2500 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
2501 8 gdevic 
    if (M5 & T2) begin fMWrite=1; end
2502 
    if (M5 & T3) begin fMWrite=1; setM1=1; end
2503 6 gdevic 
end
2504 
 
2505 8 gdevic 
if (~use_ixiy & pla[73] & ~pla[55]) begin
2506 
    if (M1 & T1) begin
2507 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0}; /* Write 8-bit GP register selected by op[2:0] */
2508 6 gdevic 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
2509 
                    ctl_sw_2u=1;
2510 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
2511 
                    ctl_alu_res_oe=1; /* Result latch */
2512 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
2513 8 gdevic 
                    ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
2514 
    if (M1 & T3) begin
2515 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
2516 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
2517 6 gdevic 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2518 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
2519 
                    ctl_alu_bs_oe=1; /* Bit-selector unit */
2520 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2521 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2522 
                    ctl_flags_sz_we=1;
2523 
                    ctl_flags_xy_we=1;
2524 
                    ctl_flags_hf_we=1;
2525 
                    ctl_flags_pf_we=1;
2526 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
2527 
                    ctl_flags_cf_we=1; end
2528 8 gdevic 
    if (M1 & T4) begin validPLA=1; setM1=1;
2529 
                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
2530 
                    ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
2531 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2532 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2533 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
2534 8 gdevic 
                    ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
2535 
    if (M4 & T1) begin fMRead=1;
2536 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
2537 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
2538 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2539 
                    ctl_alu_bs_oe=1; /* Bit-selector unit */
2540 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2541 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2542 
                    ctl_ir_we=1; end
2543 8 gdevic 
    if (M4 & T2) begin fMRead=1; end
2544 
    if (M4 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
2545 6 gdevic 
                    ctl_sw_2d=1;
2546 
                    ctl_sw_1d=1;
2547 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2548 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2549 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2550 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2551 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
2552 8 gdevic 
                    ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
2553 
    if (M5 & T1) begin fMWrite=1;
2554 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
2555 
                    ctl_sw_2u=1;
2556 
                    ctl_sw_1u=1;
2557 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
2558 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
2559 
                    ctl_alu_res_oe=1; /* Result latch */
2560 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
2561 8 gdevic 
                    ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
2562 
    if (M5 & T2) begin fMWrite=1; end
2563 
    if (M5 & T3) begin fMWrite=1; setM1=1; end
2564 6 gdevic 
end
2565 
 
2566 8 gdevic 
if (~use_ixiy & pla[73] & pla[55]) begin
2567 
    if (M1 & T3) begin
2568 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
2569 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
2570 6 gdevic 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2571 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
2572 
                    ctl_alu_bs_oe=1; /* Bit-selector unit */
2573 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2574 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2575 
                    ctl_flags_sz_we=1;
2576 
                    ctl_flags_xy_we=1;
2577 
                    ctl_flags_hf_we=1;
2578 
                    ctl_flags_pf_we=1;
2579 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
2580 
                    ctl_flags_cf_we=1; end
2581 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
2582 
    if (M2 & T1) begin fMRead=1;
2583 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
2584 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
2585 8 gdevic 
    if (M2 & T2) begin fMRead=1; end
2586 
    if (M2 & T3) begin fMRead=1;
2587 6 gdevic 
                    ctl_sw_2d=1;
2588 
                    ctl_sw_1d=1;
2589 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2590 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2591 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2592 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
2593 8 gdevic 
                    ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
2594 
    if (M2 & T4) begin nextM=1; ctl_mWrite=1;
2595 6 gdevic 
                    ctl_sw_2u=1;
2596 
                    ctl_sw_1u=1;
2597 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
2598 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
2599 
                    ctl_alu_res_oe=1; /* Result latch */
2600 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
2601 8 gdevic 
                    ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
2602 
    if (M3 & T1) begin fMWrite=1;
2603 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
2604 8 gdevic 
    if (M3 & T2) begin fMWrite=1; end
2605 
    if (M3 & T3) begin fMWrite=1; setM1=1; end
2606 
    if (M4 & T1) begin fMRead=1;
2607 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
2608 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
2609 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2610 
                    ctl_alu_bs_oe=1; /* Bit-selector unit */
2611 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2612 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2613 
                    ctl_ir_we=1; end
2614 8 gdevic 
    if (M4 & T2) begin fMRead=1; end
2615 
    if (M4 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
2616 6 gdevic 
                    ctl_sw_2d=1;
2617 
                    ctl_sw_1d=1;
2618 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2619 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2620 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2621 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2622 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
2623 8 gdevic 
                    ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
2624 
    if (M5 & T1) begin fMWrite=1;
2625 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
2626 
                    ctl_sw_2u=1;
2627 
                    ctl_sw_1u=1;
2628 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
2629 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
2630 
                    ctl_alu_res_oe=1; /* Result latch */
2631 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
2632 8 gdevic 
                    ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
2633 
    if (M5 & T2) begin fMWrite=1; end
2634 
    if (M5 & T3) begin fMWrite=1; setM1=1; end
2635 6 gdevic 
end
2636 
 
2637 
// Input and Output Groups
2638 8 gdevic 
if (pla[37] & ~pla[28]) begin
2639 
    if (M1 & T1) begin
2640 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
2641 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
2642 
                    ctl_sw_2d=1;
2643 
                    ctl_sw_1d=1;
2644 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
2645 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
2646 
    if (M2 & T1) begin fMRead=1;
2647 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
2648 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
2649 8 gdevic 
    if (M2 & T2) begin fMRead=1;
2650 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
2651 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
2652 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
2653 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_iorw=1; end
2654 
    if (M3 & T1) begin fIORead=1;
2655 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; ctl_sw_4d=1; /* Read 8-bit general purpose A register, enable SW4 downstream */
2656 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ /* Which register to be written is decided elsewhere */
2657 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
2658 
                    ctl_sw_1d=1;
2659 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
2660 8 gdevic 
    if (M3 & T2) begin fIORead=1; end
2661 
    if (M3 & T3) begin fIORead=1; end
2662 
    if (M3 & T4) begin fIORead=1; setM1=1; end
2663 6 gdevic 
end
2664 
 
2665 8 gdevic 
if (pla[27] & ~pla[34]) begin
2666 
    if (M1 & T1) begin
2667 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
2668 6 gdevic 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
2669 
                    ctl_sw_2d=1;
2670 
                    ctl_sw_1d=1;
2671 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2672 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2673 
                    ctl_alu_res_oe=1; /* Result latch */
2674 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
2675 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
2676 
                    ctl_flags_sz_we=1;
2677 
                    ctl_flags_xy_we=1;
2678 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
2679 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
2680 8 gdevic 
    if (M1 & T2) begin
2681 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
2682 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
2683 
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
2684 8 gdevic 
    if (M1 & T3) begin
2685 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
2686 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
2687 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
2688 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2689 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2690 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2691 
                    ctl_flags_sz_we=1;
2692 
                    ctl_flags_xy_we=1;
2693 
                    ctl_flags_hf_we=1;
2694 
                    ctl_flags_pf_we=1;
2695 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
2696 
                    ctl_flags_cf_we=1; end
2697 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_iorw=1; end
2698 
    if (M2 & T1) begin fIORead=1;
2699 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */
2700 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
2701 8 gdevic 
    if (M2 & T2) begin fIORead=1; end
2702 
    if (M2 & T3) begin fIORead=1; end
2703 
    if (M2 & T4) begin fIORead=1; setM1=1;
2704 6 gdevic 
                    ctl_sw_2d=1;
2705 
                    ctl_sw_1d=1;
2706 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2707 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2708 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2709 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2710 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2711 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
2712 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
2713 
                    ctl_flags_sz_we=1;
2714 
                    ctl_flags_xy_we=1;
2715 
                    ctl_flags_hf_we=1;
2716 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
2717 
end
2718 
 
2719 8 gdevic 
if (pla[37] & pla[28]) begin
2720 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
2721 
    if (M2 & T1) begin fMRead=1;
2722 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
2723 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
2724 8 gdevic 
    if (M2 & T2) begin fMRead=1;
2725 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
2726 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
2727 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
2728 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_iorw=1;
2729 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; ctl_sw_4d=1; /* Read 8-bit general purpose A register, enable SW4 downstream */
2730 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
2731 
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
2732 
                    ctl_sw_1d=1;
2733 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
2734 8 gdevic 
    if (M3 & T1) begin fIOWrite=1;
2735 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
2736 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
2737 8 gdevic 
                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
2738 6 gdevic 
                    ctl_sw_2u=1;
2739 
                    ctl_sw_1u=1;
2740 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
2741 8 gdevic 
    if (M3 & T2) begin fIOWrite=1; end
2742 
    if (M3 & T3) begin fIOWrite=1; end
2743 
    if (M3 & T4) begin fIOWrite=1; setM1=1; end
2744 6 gdevic 
end
2745 
 
2746 8 gdevic 
if (pla[27] & pla[34]) begin
2747 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_iorw=1;
2748 
        if (op4 & op5 & ~op3) begin ctl_bus_zero_oe=1; end  /* Trying to read flags? Put 0 on the bus instead. */
2749 
        if (~(op4 & op5 & ~op3)) begin ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; end /* Read 8-bit GP register */
2750 
                    ctl_reg_out_hi=~rsel3; ctl_reg_out_lo=rsel3; ctl_sw_2u=~rsel3; ctl_sw_2d=rsel3; /* Enable register gate based on the rsel3 */ /* Controlled by register gate */
2751 6 gdevic 
                    ctl_sw_1u=1;
2752 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
2753 8 gdevic 
    if (M2 & T1) begin fIOWrite=1;
2754 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */
2755 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
2756 8 gdevic 
    if (M2 & T2) begin fIOWrite=1; end
2757 
    if (M2 & T3) begin fIOWrite=1; end
2758 
    if (M2 & T4) begin fIOWrite=1; setM1=1; end
2759 6 gdevic 
end
2760 
 
2761 8 gdevic 
if (pla[91] & pla[21]) begin
2762 
    if (M1 & T1) begin
2763 6 gdevic 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
2764 
                    ctl_alu_res_oe=1; /* Result latch */
2765 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
2766 8 gdevic 
                    ctl_alu_core_R=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
2767 6 gdevic 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end
2768 8 gdevic 
    if (M1 & T2) begin
2769 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
2770 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
2771 
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
2772 8 gdevic 
    if (M1 & T3) begin
2773 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
2774 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
2775 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
2776 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2777 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2778 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2779 
                    ctl_flags_sz_we=1;
2780 
                    ctl_flags_xy_we=1;
2781 
                    ctl_flags_hf_we=1;
2782 
                    ctl_flags_pf_we=1;
2783 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
2784 
                    ctl_flags_cf_we=1; end
2785 8 gdevic 
    if (M1 & T4) begin validPLA=1; end
2786 
    if (M1 & T5) begin nextM=1; ctl_iorw=1; end
2787 
    if (M2 & T1) begin fIORead=1;
2788 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */
2789 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
2790 8 gdevic 
    if (M2 & T2) begin fIORead=1;
2791 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
2792 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
2793 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2794 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2795 6 gdevic 
                    ctl_alu_op2_sel_zero=1; /* Zero */
2796 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2797 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
2798 8 gdevic 
                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
2799 6 gdevic 
                    ctl_flags_hf_we=1;
2800 
                    ctl_alu_sel_op2_neg=1; end
2801 8 gdevic 
    if (M2 & T3) begin fIORead=1;
2802 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
2803 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
2804 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2805 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
2806 
                    ctl_alu_res_oe=1; /* Result latch */
2807 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
2808 8 gdevic 
                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
2809 6 gdevic 
                    ctl_flags_sz_we=1;
2810 
                    ctl_flags_xy_we=1;
2811 
                    ctl_flags_cf_we=1;
2812 
                    ctl_alu_sel_op2_neg=1; end
2813 8 gdevic 
    if (M2 & T4) begin fIORead=1; nextM=1; ctl_mWrite=1;
2814 6 gdevic 
                    ctl_sw_2d=1;
2815 
                    ctl_sw_1d=1;
2816 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2817 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2818 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2819 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2820 
                    ctl_flags_nf_we=1; /* Sign bit, to be used with FLAGT source set to "alu" */
2821 
                    ctl_alu_sel_op2_neg=1; end
2822 8 gdevic 
    if (M3 & T1) begin fMWrite=1;
2823 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
2824 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
2825 8 gdevic 
    if (M3 & T2) begin fMWrite=1;
2826 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
2827 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
2828 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
2829 8 gdevic 
    if (M3 & T3) begin fMWrite=1; nextM=1; setM1=nonRep | flags_zf; end
2830 
    if (M4 & T1) begin
2831 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
2832 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
2833 8 gdevic 
    if (M4 & T2) begin
2834 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
2835 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
2836 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
2837 8 gdevic 
    if (M4 & T3) begin
2838 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
2839 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
2840 8 gdevic 
    if (M4 & T4) begin
2841 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
2842 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
2843 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
2844 8 gdevic 
    if (M4 & T5) begin setM1=1; end
2845 6 gdevic 
end
2846 
 
2847 8 gdevic 
if (pla[91] & pla[20]) begin
2848 
    if (M1 & T1) begin
2849 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2850 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
2851 
                    ctl_alu_res_oe=1; /* Result latch */
2852 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
2853 8 gdevic 
                    ctl_alu_core_R=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
2854 6 gdevic 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end
2855 8 gdevic 
    if (M1 & T2) begin
2856 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
2857 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
2858 
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
2859 8 gdevic 
    if (M1 & T3) begin
2860 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
2861 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
2862 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
2863 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2864 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2865 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2866 
                    ctl_flags_sz_we=1;
2867 
                    ctl_flags_xy_we=1;
2868 
                    ctl_flags_hf_we=1;
2869 
                    ctl_flags_pf_we=1;
2870 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
2871 
                    ctl_flags_cf_we=1; end
2872 8 gdevic 
    if (M1 & T4) begin validPLA=1;
2873 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
2874 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
2875 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2876 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2877 6 gdevic 
                    ctl_alu_op2_sel_zero=1; /* Zero */
2878 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2879 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
2880 8 gdevic 
                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
2881 6 gdevic 
                    ctl_flags_hf_we=1;
2882 
                    ctl_alu_sel_op2_neg=1; end
2883 8 gdevic 
    if (M1 & T5) begin nextM=1; ctl_mRead=1;
2884 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
2885 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
2886 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2887 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
2888 
                    ctl_alu_res_oe=1; /* Result latch */
2889 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
2890 8 gdevic 
                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
2891 6 gdevic 
                    ctl_flags_sz_we=1;
2892 
                    ctl_flags_xy_we=1;
2893 
                    ctl_alu_sel_op2_neg=1; end
2894 8 gdevic 
    if (M2 & T1) begin fMRead=1;
2895 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
2896 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
2897 8 gdevic 
    if (M2 & T2) begin fMRead=1;
2898 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
2899 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
2900 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
2901 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_iorw=1;
2902 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;
2903 8 gdevic 
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
2904 6 gdevic 
                    ctl_sw_2d=1;
2905 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2906 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end
2907 8 gdevic 
    if (M3 & T1) begin fIOWrite=1;
2908 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */
2909 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
2910 8 gdevic 
    if (M3 & T2) begin fIOWrite=1;
2911 6 gdevic 
                    ctl_sw_2d=1;
2912 
                    ctl_sw_1d=1;
2913 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2914 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2915 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2916 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2917 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
2918 8 gdevic 
                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
2919 6 gdevic 
                    ctl_flags_hf_we=1;
2920 
                    ctl_flags_nf_we=1; /* Sign bit, to be used with FLAGT source set to "alu" */ end
2921 8 gdevic 
    if (M3 & T3) begin fIOWrite=1;
2922 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2923 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
2924 
                    ctl_alu_res_oe=1; /* Result latch */
2925 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
2926 8 gdevic 
                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
2927 6 gdevic 
                    ctl_flags_cf_we=1; end
2928 8 gdevic 
    if (M3 & T4) begin fIOWrite=1; nextM=1; setM1=nonRep | flags_zf; end
2929 
    if (M4 & T1) begin
2930 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
2931 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
2932 8 gdevic 
    if (M4 & T2) begin
2933 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
2934 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
2935 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
2936 8 gdevic 
    if (M4 & T3) begin
2937 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
2938 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
2939 8 gdevic 
    if (M4 & T4) begin
2940 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
2941 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
2942 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
2943 8 gdevic 
    if (M4 & T5) begin setM1=1; end
2944 6 gdevic 
end
2945 
 
2946 
// Jump Group
2947 
if (pla[29]) begin
2948 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
2949 
    if (M2 & T1) begin fMRead=1;
2950 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
2951 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
2952 8 gdevic 
    if (M2 & T2) begin fMRead=1;
2953 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
2954 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
2955 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
2956 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
2957 
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
2958 6 gdevic 
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
2959 
                    ctl_sw_2d=1;
2960 
                    ctl_sw_1d=1;
2961 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
2962 8 gdevic 
    if (M3 & T1) begin fMRead=1;
2963 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
2964 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
2965 8 gdevic 
    if (M3 & T2) begin fMRead=1;
2966 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
2967 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
2968 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
2969 8 gdevic 
    if (M3 & T3) begin fMRead=1; setM1=1;
2970 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
2971 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
2972 8 gdevic 
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
2973 6 gdevic 
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
2974 
                    ctl_sw_2d=1;
2975 
                    ctl_sw_1d=1;
2976 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2977 
                    ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
2978 
end
2979 
 
2980 
if (pla[43]) begin
2981 8 gdevic 
    if (M1 & T3) begin
2982 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
2983 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
2984 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
2985 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2986 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2987 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2988 
                    ctl_flags_sz_we=1;
2989 
                    ctl_flags_xy_we=1;
2990 
                    ctl_flags_hf_we=1;
2991 
                    ctl_flags_pf_we=1;
2992 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
2993 
                    ctl_flags_cf_we=1; end
2994 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
2995 
    if (M2 & T1) begin fMRead=1;
2996 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
2997 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
2998 8 gdevic 
    if (M2 & T2) begin fMRead=1;
2999 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
3000 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
3001 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
3002 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
3003 
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
3004 6 gdevic 
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
3005 
                    ctl_sw_2d=1;
3006 
                    ctl_sw_1d=1;
3007 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
3008 8 gdevic 
    if (M3 & T1) begin fMRead=1;
3009 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
3010 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
3011 8 gdevic 
    if (M3 & T2) begin fMRead=1;
3012 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
3013 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
3014 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
3015 8 gdevic 
    if (M3 & T3) begin fMRead=1; setM1=1;
3016 
                    ctl_reg_not_pc|=flags_cond_true; ctl_reg_sel_wz|=flags_cond_true; ctl_reg_sys_hilo|={flags_cond_true,flags_cond_true}; ctl_sw_4d|=flags_cond_true;
3017 6 gdevic 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
3018 8 gdevic 
                    ctl_reg_sys_we_hi=flags_cond_true; ctl_reg_sel_wz=flags_cond_true; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Conditionally selecting only W */
3019 6 gdevic 
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
3020 
                    ctl_sw_2d=1;
3021 
                    ctl_sw_1d=1;
3022 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
3023 
end
3024 
 
3025 
if (pla[47]) begin
3026 8 gdevic 
    if (M1 & T3) begin
3027 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
3028 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
3029 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
3030 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
3031 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
3032 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
3033 
                    ctl_flags_sz_we=1;
3034 
                    ctl_flags_xy_we=1;
3035 
                    ctl_flags_hf_we=1;
3036 
                    ctl_flags_pf_we=1;
3037 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
3038 
                    ctl_flags_cf_we=1; end
3039 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
3040 
    if (M2 & T1) begin fMRead=1;
3041 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
3042 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
3043 8 gdevic 
    if (M2 & T2) begin fMRead=1;
3044 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
3045 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
3046 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
3047 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; end
3048 
    if (M3 & T1) begin
3049 6 gdevic 
                    ctl_sw_2d=1;
3050 
                    ctl_sw_1d=1;
3051 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
3052 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
3053 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
3054 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
3055 
                    ctl_flags_sz_we=1; end
3056 8 gdevic 
    if (M3 & T2) begin
3057 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;
3058 8 gdevic 
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
3059 6 gdevic 
                    ctl_sw_2d=1;
3060 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
3061 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
3062 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
3063 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
3064 8 gdevic 
                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
3065 6 gdevic 
                    ctl_flags_hf_we=1; end
3066 8 gdevic 
    if (M3 & T3) begin
3067 
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
3068 6 gdevic 
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
3069 
                    ctl_sw_2u=1;
3070 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
3071 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
3072 
                    ctl_alu_res_oe=1; /* Result latch */
3073 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
3074 8 gdevic 
                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
3075 6 gdevic 
                    ctl_flags_cf_we=1; end
3076 8 gdevic 
    if (M3 & T4) begin
3077 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;
3078 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
3079 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
3080 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
3081 6 gdevic 
                    ctl_alu_op2_sel_zero=1; /* Zero */
3082 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
3083 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
3084 8 gdevic 
                    ctl_alu_core_hf|=~ctl_alu_op_low;
3085 6 gdevic 
                    ctl_flags_hf_we=1;
3086 
                    ctl_alu_sel_op2_neg=flags_sf; end
3087 8 gdevic 
    if (M3 & T5) begin setM1=1;
3088 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
3089 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
3090 8 gdevic 
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
3091 6 gdevic 
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
3092 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
3093 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
3094 
                    ctl_alu_res_oe=1; /* Result latch */
3095 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
3096 8 gdevic 
                    ctl_alu_core_hf|=~ctl_alu_op_low;
3097 6 gdevic 
                    ctl_alu_sel_op2_neg=flags_sf;
3098 
                    ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
3099 
end
3100 
 
3101 
if (pla[48]) begin
3102 8 gdevic 
    if (M1 & T3) begin
3103 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
3104 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
3105 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
3106 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
3107 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
3108 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
3109 
                    ctl_flags_sz_we=1;
3110 
                    ctl_flags_xy_we=1;
3111 
                    ctl_flags_hf_we=1;
3112 
                    ctl_flags_pf_we=1;
3113 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
3114 
                    ctl_flags_cf_we=1; end
3115 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1;
3116 6 gdevic 
                    ctl_cond_short=1; /* M1/T3 only: force a short flags condition (SS) */ end
3117 8 gdevic 
    if (M2 & T1) begin fMRead=1;
3118 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
3119 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
3120 8 gdevic 
    if (M2 & T2) begin fMRead=1;
3121 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
3122 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
3123 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
3124 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; setM1=~flags_cond_true; end
3125 
    if (M3 & T1) begin
3126 6 gdevic 
                    ctl_sw_2d=1;
3127 
                    ctl_sw_1d=1;
3128 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
3129 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
3130 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
3131 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
3132 
                    ctl_flags_sz_we=1; end
3133 8 gdevic 
    if (M3 & T2) begin
3134 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;
3135 8 gdevic 
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
3136 6 gdevic 
                    ctl_sw_2d=1;
3137 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
3138 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
3139 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
3140 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
3141 8 gdevic 
                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
3142 6 gdevic 
                    ctl_flags_hf_we=1; end
3143 8 gdevic 
    if (M3 & T3) begin
3144 
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
3145 6 gdevic 
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
3146 
                    ctl_sw_2u=1;
3147 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
3148 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
3149 
                    ctl_alu_res_oe=1; /* Result latch */
3150 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
3151 8 gdevic 
                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
3152 6 gdevic 
                    ctl_flags_cf_we=1; end
3153 8 gdevic 
    if (M3 & T4) begin
3154 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;
3155 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
3156 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
3157 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
3158 6 gdevic 
                    ctl_alu_op2_sel_zero=1; /* Zero */
3159 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
3160 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
3161 8 gdevic 
                    ctl_alu_core_hf|=~ctl_alu_op_low;
3162 6 gdevic 
                    ctl_flags_hf_we=1;
3163 
                    ctl_alu_sel_op2_neg=flags_sf; end
3164 8 gdevic 
    if (M3 & T5) begin setM1=1;
3165 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
3166 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
3167 8 gdevic 
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
3168 6 gdevic 
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
3169 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
3170 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
3171 
                    ctl_alu_res_oe=1; /* Result latch */
3172 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
3173 8 gdevic 
                    ctl_alu_core_hf|=~ctl_alu_op_low;
3174 6 gdevic 
                    ctl_alu_sel_op2_neg=flags_sf;
3175 
                    ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
3176 
end
3177 
 
3178 
if (pla[6]) begin
3179 8 gdevic 
    if (M1 & T4) begin validPLA=1; setM1=1;
3180 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
3181 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
3182 
                    ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
3183 
end
3184 
 
3185 
if (pla[26]) begin
3186 8 gdevic 
    if (M1 & T3) begin
3187 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
3188 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
3189 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
3190 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
3191 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
3192 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
3193 
                    ctl_flags_sz_we=1;
3194 
                    ctl_flags_xy_we=1;
3195 
                    ctl_flags_hf_we=1;
3196 
                    ctl_flags_pf_we=1;
3197 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
3198 
                    ctl_flags_cf_we=1; end
3199 8 gdevic 
    if (M1 & T4) begin validPLA=1;
3200 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
3201 8 gdevic 
                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
3202 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
3203 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
3204 6 gdevic 
                    ctl_alu_op2_sel_zero=1; /* Zero */
3205 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
3206 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
3207 8 gdevic 
                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
3208 6 gdevic 
                    ctl_flags_hf_we=1;
3209 
                    ctl_alu_sel_op2_neg=1; end
3210 8 gdevic 
    if (M1 & T5) begin nextM=1; ctl_mRead=1;
3211 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
3212 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
3213 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
3214 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
3215 
                    ctl_alu_res_oe=1; /* Result latch */
3216 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
3217 8 gdevic 
                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
3218 6 gdevic 
                    ctl_flags_sz_we=1;
3219 
                    ctl_alu_sel_op2_neg=1; end
3220 8 gdevic 
    if (M2 & T1) begin fMRead=1;
3221 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
3222 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
3223 8 gdevic 
    if (M2 & T2) begin fMRead=1;
3224 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
3225 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
3226 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
3227 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; setM1=flags_zf; /* Used in DJNZ */ end
3228 
    if (M3 & T1) begin
3229 6 gdevic 
                    ctl_sw_2d=1;
3230 
                    ctl_sw_1d=1;
3231 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
3232 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
3233 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
3234 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
3235 
                    ctl_flags_sz_we=1; end
3236 8 gdevic 
    if (M3 & T2) begin
3237 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;
3238 8 gdevic 
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
3239 6 gdevic 
                    ctl_sw_2d=1;
3240 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
3241 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
3242 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
3243 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
3244 8 gdevic 
                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
3245 6 gdevic 
                    ctl_flags_hf_we=1; end
3246 8 gdevic 
    if (M3 & T3) begin
3247 
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
3248 6 gdevic 
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
3249 
                    ctl_sw_2u=1;
3250 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
3251 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
3252 
                    ctl_alu_res_oe=1; /* Result latch */
3253 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
3254 8 gdevic 
                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
3255 6 gdevic 
                    ctl_flags_cf_we=1; end
3256 8 gdevic 
    if (M3 & T4) begin
3257 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;
3258 8 gdevic 
                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
3259 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
3260 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
3261 6 gdevic 
                    ctl_alu_op2_sel_zero=1; /* Zero */
3262 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
3263 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
3264 8 gdevic 
                    ctl_alu_core_hf|=~ctl_alu_op_low;
3265 6 gdevic 
                    ctl_flags_hf_we=1;
3266 
                    ctl_alu_sel_op2_neg=flags_sf; end
3267 8 gdevic 
    if (M3 & T5) begin setM1=1;
3268 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
3269 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
3270 8 gdevic 
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
3271 6 gdevic 
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
3272 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
3273 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
3274 
                    ctl_alu_res_oe=1; /* Result latch */
3275 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
3276 8 gdevic 
                    ctl_alu_core_hf|=~ctl_alu_op_low;
3277 6 gdevic 
                    ctl_alu_sel_op2_neg=flags_sf;
3278 
                    ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
3279 
end
3280 
 
3281 
// Call and Return Group
3282 
if (pla[24]) begin
3283 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
3284 
    if (M2 & T1) begin fMRead=1;
3285 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
3286 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
3287 8 gdevic 
    if (M2 & T2) begin fMRead=1;
3288 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
3289 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
3290 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
3291 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
3292 
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
3293 6 gdevic 
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
3294 
                    ctl_sw_2d=1;
3295 
                    ctl_sw_1d=1;
3296 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
3297 8 gdevic 
    if (M3 & T1) begin fMRead=1;
3298 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
3299 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
3300 8 gdevic 
    if (M3 & T2) begin fMRead=1;
3301 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
3302 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
3303 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
3304 8 gdevic 
    if (M3 & T3) begin fMRead=1;
3305 
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
3306 6 gdevic 
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
3307 
                    ctl_sw_2d=1;
3308 
                    ctl_sw_1d=1;
3309 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
3310 8 gdevic 
    if (M3 & T4) begin nextM=1; ctl_mWrite=1;
3311 6 gdevic 
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
3312 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
3313 6 gdevic 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
3314 8 gdevic 
    if (M4 & T1) begin fMWrite=1;
3315 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
3316 6 gdevic 
                    ctl_apin_mux=1; /* Apin sourced from incrementer */
3317 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;
3318 8 gdevic 
                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
3319 6 gdevic 
                    ctl_sw_2u=1;
3320 
                    ctl_sw_1u=1;
3321 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
3322 8 gdevic 
    if (M4 & T2) begin fMWrite=1;
3323 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
3324 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
3325 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
3326 8 gdevic 
    if (M4 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
3327 6 gdevic 
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
3328 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
3329 6 gdevic 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
3330 8 gdevic 
    if (M5 & T1) begin fMWrite=1;
3331 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
3332 6 gdevic 
                    ctl_apin_mux=1; /* Apin sourced from incrementer */
3333 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;
3334 8 gdevic 
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
3335 6 gdevic 
                    ctl_sw_1u=1;
3336 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
3337 8 gdevic 
    if (M5 & T2) begin fMWrite=1;
3338 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
3339 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
3340 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
3341 8 gdevic 
    if (M5 & T3) begin fMWrite=1; setM1=1;
3342 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
3343 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
3344 
                    ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
3345 
end
3346 
 
3347 
if (pla[42]) begin
3348 8 gdevic 
    if (M1 & T3) begin
3349 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
3350 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
3351 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
3352 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
3353 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
3354 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
3355 
                    ctl_flags_sz_we=1;
3356 
                    ctl_flags_xy_we=1;
3357 
                    ctl_flags_hf_we=1;
3358 
                    ctl_flags_pf_we=1;
3359 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
3360 
                    ctl_flags_cf_we=1; end
3361 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
3362 
    if (M2 & T1) begin fMRead=1;
3363 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
3364 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
3365 8 gdevic 
    if (M2 & T2) begin fMRead=1;
3366 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
3367 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
3368 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
3369 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
3370 
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
3371 6 gdevic 
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
3372 
                    ctl_sw_2d=1;
3373 
                    ctl_sw_1d=1;
3374 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
3375 8 gdevic 
    if (M3 & T1) begin fMRead=1;
3376 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
3377 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
3378 8 gdevic 
    if (M3 & T2) begin fMRead=1;
3379 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
3380 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
3381 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
3382 8 gdevic 
    if (M3 & T3) begin fMRead=1; nextM=~flags_cond_true; setM1=~flags_cond_true;
3383 
                    ctl_reg_sys_we_hi=flags_cond_true; ctl_reg_sel_wz=flags_cond_true; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Conditionally selecting only W */
3384 6 gdevic 
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
3385 
                    ctl_sw_2d=1;
3386 
                    ctl_sw_1d=1;
3387 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
3388 8 gdevic 
    if (M3 & T4) begin nextM=1; ctl_mWrite=1;
3389 6 gdevic 
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
3390 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
3391 6 gdevic 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
3392 8 gdevic 
    if (M4 & T1) begin fMWrite=1;
3393 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
3394 6 gdevic 
                    ctl_apin_mux=1; /* Apin sourced from incrementer */
3395 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;
3396 8 gdevic 
                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
3397 6 gdevic 
                    ctl_sw_2u=1;
3398 
                    ctl_sw_1u=1;
3399 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
3400 8 gdevic 
    if (M4 & T2) begin fMWrite=1;
3401 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
3402 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
3403 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
3404 8 gdevic 
    if (M4 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
3405 6 gdevic 
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
3406 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
3407 6 gdevic 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
3408 8 gdevic 
    if (M5 & T1) begin fMWrite=1;
3409 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
3410 6 gdevic 
                    ctl_apin_mux=1; /* Apin sourced from incrementer */
3411 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;
3412 8 gdevic 
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
3413 6 gdevic 
                    ctl_sw_1u=1;
3414 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
3415 8 gdevic 
    if (M5 & T2) begin fMWrite=1;
3416 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
3417 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
3418 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
3419 8 gdevic 
    if (M5 & T3) begin fMWrite=1; setM1=1;
3420 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
3421 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
3422 
                    ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
3423 
end
3424 
 
3425 
if (pla[35]) begin
3426 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
3427 
    if (M2 & T1) begin fMRead=1;
3428 6 gdevic 
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
3429 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
3430 8 gdevic 
    if (M2 & T2) begin fMRead=1;
3431 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
3432 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
3433 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
3434 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
3435 
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
3436 6 gdevic 
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
3437 
                    ctl_sw_2d=1;
3438 
                    ctl_sw_1d=1;
3439 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
3440 8 gdevic 
    if (M3 & T1) begin fMRead=1;
3441 6 gdevic 
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
3442 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
3443 8 gdevic 
    if (M3 & T2) begin fMRead=1;
3444 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
3445 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
3446 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
3447 8 gdevic 
    if (M3 & T3) begin fMRead=1; setM1=1;
3448 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
3449 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
3450 8 gdevic 
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
3451 6 gdevic 
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
3452 
                    ctl_sw_2d=1;
3453 
                    ctl_sw_1d=1;
3454 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
3455 
                    ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
3456 
end
3457 
 
3458 
if (pla[45]) begin
3459 8 gdevic 
    if (M1 & T3) begin
3460 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
3461 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
3462 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
3463 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
3464 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
3465 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
3466 
                    ctl_flags_sz_we=1;
3467 
                    ctl_flags_xy_we=1;
3468 
                    ctl_flags_hf_we=1;
3469 
                    ctl_flags_pf_we=1;
3470 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
3471 
                    ctl_flags_cf_we=1; end
3472 8 gdevic 
    if (M1 & T4) begin validPLA=1; end
3473 
    if (M1 & T5) begin nextM=1; ctl_mRead=1; setM1=~flags_cond_true; end
3474 
    if (M2 & T1) begin fMRead=1;
3475 6 gdevic 
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
3476 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
3477 8 gdevic 
    if (M2 & T2) begin fMRead=1;
3478 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
3479 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
3480 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
3481 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
3482 
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
3483 6 gdevic 
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
3484 
                    ctl_sw_2d=1;
3485 
                    ctl_sw_1d=1;
3486 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
3487 8 gdevic 
    if (M3 & T1) begin fMRead=1;
3488 6 gdevic 
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
3489 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
3490 8 gdevic 
    if (M3 & T2) begin fMRead=1;
3491 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
3492 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
3493 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
3494 8 gdevic 
    if (M3 & T3) begin fMRead=1; setM1=1;
3495 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
3496 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
3497 8 gdevic 
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
3498 6 gdevic 
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
3499 
                    ctl_sw_2d=1;
3500 
                    ctl_sw_1d=1;
3501 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
3502 
                    ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
3503 
end
3504 
 
3505 
if (pla[46]) begin
3506 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1;
3507 6 gdevic 
                    ctl_iff1_iff2=1; /* RETN copies IFF2 into IFF1 */ end
3508 8 gdevic 
    if (M2 & T1) begin fMRead=1;
3509 6 gdevic 
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
3510 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
3511 8 gdevic 
    if (M2 & T2) begin fMRead=1;
3512 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
3513 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
3514 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
3515 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
3516 
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
3517 6 gdevic 
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
3518 
                    ctl_sw_2d=1;
3519 
                    ctl_sw_1d=1;
3520 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
3521 8 gdevic 
    if (M3 & T1) begin fMRead=1;
3522 6 gdevic 
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
3523 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
3524 8 gdevic 
    if (M3 & T2) begin fMRead=1;
3525 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
3526 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
3527 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
3528 8 gdevic 
    if (M3 & T3) begin fMRead=1; setM1=1;
3529 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
3530 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
3531 8 gdevic 
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
3532 6 gdevic 
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
3533 
                    ctl_sw_2d=1;
3534 
                    ctl_sw_1d=1;
3535 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
3536 
                    ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
3537 
end
3538 
 
3539 
if (pla[56]) begin
3540 8 gdevic 
    if (M1 & T3) begin
3541 6 gdevic 
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11;
3542 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
3543 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
3544 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
3545 
                    ctl_alu_op1_oe=1; /* OP1 latch */
3546 
                    ctl_alu_op1_sel_zero=1; /* Zero */
3547 8 gdevic 
                    ctl_sw_mask543_en=~((in_intr & im2) | in_nmi);
3548 
                    ctl_sw_1d=~in_nmi; ctl_66_oe=in_nmi;
3549 6 gdevic 
                    ctl_bus_ff_oe=in_intr & im1; end
3550 8 gdevic 
    if (M1 & T4) begin validPLA=1; end
3551 
    if (M1 & T5) begin nextM=1; ctl_mWrite=1;
3552 6 gdevic 
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
3553 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
3554 6 gdevic 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
3555 
                    ctl_sw_2d=1;
3556 
                    ctl_sw_1d=1;
3557 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
3558 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
3559 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end
3560 8 gdevic 
    if (M2 & T1) begin fMWrite=1;
3561 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
3562 6 gdevic 
                    ctl_apin_mux=1; /* Apin sourced from incrementer */
3563 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;
3564 8 gdevic 
                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
3565 6 gdevic 
                    ctl_sw_2u=1;
3566 
                    ctl_sw_1u=1;
3567 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
3568 8 gdevic 
    if (M2 & T2) begin fMWrite=1;
3569 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
3570 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
3571 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
3572 8 gdevic 
    if (M2 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
3573 6 gdevic 
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
3574 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
3575 6 gdevic 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
3576 8 gdevic 
    if (M3 & T1) begin fMWrite=1;
3577 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
3578 6 gdevic 
                    ctl_apin_mux=1; /* Apin sourced from incrementer */
3579 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;
3580 8 gdevic 
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
3581 6 gdevic 
                    ctl_sw_1u=1;
3582 
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
3583 8 gdevic 
    if (M3 & T2) begin fMWrite=1;
3584 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
3585 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
3586 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
3587 8 gdevic 
    if (M3 & T3) begin fMWrite=1; nextM=1; ctl_mRead=in_intr & im2; /* RST38 interrupt extension */ setM1=~(in_intr & im2); /* RST38 interrupt extension */
3588 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
3589 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
3590 
                    ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
3591 
// INTR IM2 continues here...
3592 8 gdevic 
    if (M4 & T1) begin fMRead=1;
3593 6 gdevic 
                    ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4d=1; /* Select 8-bit I register */
3594 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
3595 
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
3596 
                    ctl_sw_2u=1;
3597 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
3598 
                    ctl_alu_op1_oe=1; /* OP1 latch */ end
3599 8 gdevic 
    if (M4 & T2) begin fMRead=1;
3600 6 gdevic 
                    ctl_sw_4u=1;
3601 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
3602 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
3603 8 gdevic 
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
3604 6 gdevic 
                    ctl_sw_2d=1;
3605 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
3606 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end
3607 8 gdevic 
    if (M4 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
3608 
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
3609 6 gdevic 
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
3610 
                    ctl_sw_2d=1;
3611 
                    ctl_sw_1d=1;
3612 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
3613 8 gdevic 
    if (M5 & T1) begin fMRead=1;
3614 6 gdevic 
                    ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4d=1; /* Select 8-bit I register */
3615 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
3616 
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
3617 
                    ctl_sw_2u=1;
3618 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
3619 
                    ctl_alu_op1_oe=1; /* OP1 latch */ end
3620 8 gdevic 
    if (M5 & T2) begin fMRead=1;
3621 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
3622 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
3623 8 gdevic 
    if (M5 & T3) begin fMRead=1; setM1=1;
3624 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
3625 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
3626 8 gdevic 
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
3627 6 gdevic 
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
3628 
                    ctl_sw_2d=1;
3629 
                    ctl_sw_1d=1;
3630 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
3631 
                    ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
3632 
end
3633 
 
3634 
// CB-Table opcodes
3635 
if (pla[49]) begin
3636 8 gdevic 
    if (M1 & T3) begin
3637 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
3638 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
3639 6 gdevic 
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
3640 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
3641 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
3642 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
3643 
                    ctl_flags_sz_we=1;
3644 
                    ctl_flags_xy_we=1;
3645 
                    ctl_flags_hf_we=1;
3646 
                    ctl_flags_pf_we=1;
3647 
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
3648 
                    ctl_flags_cf_we=1;
3649 
                    ctl_state_tbl_cb_set=1; setCBED=1; /* CB-table prefix */ end
3650 8 gdevic 
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
3651 
    if (M2 & T1) begin fMRead=1;
3652 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
3653 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
3654 8 gdevic 
    if (M2 & T2) begin fMRead=1;
3655 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
3656 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
3657 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
3658 8 gdevic 
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1; end
3659 
    if (M3 & T1) begin fMRead=1;
3660 6 gdevic 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
3661 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ ixy_d=1; /* Compute WZ=IX+d */ end
3662 8 gdevic 
    if (M3 & T2) begin fMRead=1;
3663 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
3664 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
3665 6 gdevic 
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ ixy_d=1; /* Compute WZ=IX+d */ end
3666 8 gdevic 
    if (M3 & T3) begin fMRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
3667 
    if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
3668 
    if (M3 & T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
3669 
    if (M4 & T1) begin
3670 6 gdevic 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
3671 
                    ctl_alu_bs_oe=1; /* Bit-selector unit */
3672 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
3673 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
3674 
                    ctl_ir_we=1; end
3675 
// Loading a new instruction immediately changes PLA wires and continues into the new effective instructions' M4/T1 cycle
3676 
end
3677 
 
3678 
// Special Purposes PLA Entries
3679 
if (pla[3]) begin
3680 8 gdevic 
    if (M1 & T2) begin
3681 6 gdevic 
                    ctl_state_ixiy_we=1; ctl_state_iy_set=op5; setIXIY=1; /* IX/IY prefix */ end
3682 8 gdevic 
    if (M1 & T4) begin validPLA=1; setM1=1;
3683 6 gdevic 
                    ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end
3684 
end
3685 
 
3686 
if (pla[44]) begin
3687 8 gdevic 
    if (M1 & T2) begin
3688 6 gdevic 
                    ctl_state_tbl_cb_set=1; setCBED=1; /* CB-table prefix */ end
3689 8 gdevic 
    if (M1 & T4) begin validPLA=1; setM1=1;
3690 6 gdevic 
                    ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end
3691 
end
3692 
 
3693 
if (pla[51]) begin
3694 8 gdevic 
    if (M1 & T2) begin
3695 6 gdevic 
                    ctl_state_tbl_ed_set=1; setCBED=1; /* ED-table prefix */ end
3696 8 gdevic 
    if (M1 & T4) begin validPLA=1; setM1=1;
3697 6 gdevic 
                    ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end
3698 
end
3699 
 
3700 
if (pla[76]) begin
3701 8 gdevic 
    begin
3702 
                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
3703 6 gdevic 
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1; end
3704 8 gdevic 
    if (M1 & T1) begin
3705 6 gdevic 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; end
3706 
end
3707 
 
3708 
if (pla[78]) begin
3709 8 gdevic 
    begin
3710 
                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
3711 6 gdevic 
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1; end
3712 8 gdevic 
    if (M1 & T1) begin
3713 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
3714 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
3715 
                    ctl_flags_xy_we=1;
3716 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; end
3717 
end
3718 
 
3719 
if (pla[79]) begin
3720 8 gdevic 
    begin
3721 
                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
3722 6 gdevic 
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1; end
3723 8 gdevic 
    if (M1 & T1) begin
3724 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
3725 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
3726 
                    ctl_flags_xy_we=1;
3727 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; end
3728 
end
3729 
 
3730 
if (pla[80]) begin
3731 8 gdevic 
    begin
3732 
                    ctl_alu_core_hf|=~ctl_alu_op_low;
3733 6 gdevic 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
3734 8 gdevic 
    if (M1 & T1) begin
3735 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
3736 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
3737 
                    ctl_flags_xy_we=1;
3738 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; end
3739 
end
3740 
 
3741 
if (pla[84]) begin
3742 8 gdevic 
    begin
3743 
                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
3744 6 gdevic 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
3745 8 gdevic 
    if (M1 & T1) begin
3746 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
3747 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
3748 
                    ctl_flags_xy_we=1;
3749 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; end
3750 
end
3751 
 
3752 
if (pla[85]) begin
3753 8 gdevic 
    begin
3754 
                    ctl_alu_core_S=1; ctl_flags_cf_set=1;
3755 6 gdevic 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
3756 8 gdevic 
    if (M1 & T1) begin
3757 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
3758 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
3759 
                    ctl_flags_xy_we=1;
3760 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end
3761 8 gdevic 
    if (M1 & T2) begin
3762 6 gdevic 
                    ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */ end
3763 
end
3764 
 
3765 
if (pla[86]) begin
3766 8 gdevic 
    begin
3767 6 gdevic 
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
3768 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
3769 8 gdevic 
    if (M1 & T1) begin
3770 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
3771 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
3772 
                    ctl_flags_xy_we=1;
3773 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end
3774 8 gdevic 
    if (M1 & T2) begin
3775 6 gdevic 
                    ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */ end
3776 
end
3777 
 
3778 
if (pla[88]) begin
3779 8 gdevic 
    begin
3780 
                    ctl_alu_core_R=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
3781 6 gdevic 
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
3782 8 gdevic 
    if (M1 & T1) begin
3783 6 gdevic 
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
3784 
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
3785 
                    ctl_flags_xy_we=1;
3786 
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end
3787 8 gdevic 
    if (M1 & T2) begin
3788 6 gdevic 
                    ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */ end
3789 
end
3790 
 
3791 
// State machine to compute (IX+d)
3792 
if (ixy_d) begin
3793 8 gdevic 
    if (T1) begin
3794 6 gdevic 
                    ctl_sw_2d=1;
3795 
                    ctl_sw_1d=1;
3796 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
3797 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
3798 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
3799 6 gdevic 
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
3800 
                    ctl_flags_sz_we=1; end
3801 8 gdevic 
    if (T2) begin
3802 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;
3803 8 gdevic 
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
3804 6 gdevic 
                    ctl_sw_2d=1;
3805 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
3806 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
3807 6 gdevic 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
3808 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
3809 8 gdevic 
                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
3810 6 gdevic 
                    ctl_flags_hf_we=1; end
3811 8 gdevic 
    if (T3) begin
3812 
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
3813 6 gdevic 
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
3814 
                    ctl_sw_2u=1;
3815 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
3816 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
3817 
                    ctl_alu_res_oe=1; /* Result latch */
3818 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
3819 8 gdevic 
                    ctl_alu_core_hf|=~ctl_alu_op_low;
3820 
                    ctl_flags_cf2_we=1; end
3821 
    if (T4) begin
3822 6 gdevic 
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;
3823 8 gdevic 
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
3824 6 gdevic 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
3825 8 gdevic 
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
3826 6 gdevic 
                    ctl_alu_op2_sel_zero=1; /* Zero */
3827 
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
3828 
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
3829 8 gdevic 
                    ctl_alu_core_hf|=~ctl_alu_op_low;
3830 6 gdevic 
                    ctl_flags_hf_we=1;
3831 
                    ctl_flags_use_cf2=1;
3832 
                    ctl_alu_sel_op2_neg=flags_sf; end
3833 8 gdevic 
    if (T5) begin
3834 6 gdevic 
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
3835 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
3836 8 gdevic 
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
3837 6 gdevic 
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
3838 
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
3839 
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
3840 
                    ctl_alu_res_oe=1; /* Result latch */
3841 
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
3842 8 gdevic 
                    ctl_alu_core_hf|=~ctl_alu_op_low;
3843 6 gdevic 
                    ctl_flags_xy_we=1;
3844 
                    ctl_alu_sel_op2_neg=flags_sf;
3845 8 gdevic 
                    ctl_state_ixiy_we=1; ctl_state_ixiy_clr=~setIXIY; /* Clear IX/IY flag */ end
3846 6 gdevic 
end
3847 
 
3848 
// Default instruction fetch (M1) state machine
3849 8 gdevic 
if (1) begin
3850 
    if (M1 & T1) begin
3851 
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
3852 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
3853 6 gdevic 
                    ctl_bus_inc_oe=1; ctl_apin_mux2=1; /* Apin sourced from AL */ end
3854 8 gdevic 
    if (M1 & T2) begin
3855 6 gdevic 
                    ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit IR */
3856 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
3857 
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
3858 8 gdevic 
                    ctl_state_ixiy_we=1; ctl_state_ixiy_clr=~setIXIY; /* Clear IX/IY flag */
3859 
                    ctl_state_tbl_clr=~setCBED; /* Clear CB/ED prefix */
3860 6 gdevic 
                    ctl_ir_we=1;
3861 
                    ctl_bus_zero_oe=in_halt; ctl_bus_ff_oe=(in_intr & (im1 | im2)) | in_nmi; end
3862 8 gdevic 
    if (M1 & T3) begin
3863 6 gdevic 
                    ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; /* Write 16-bit IR */
3864 8 gdevic 
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
3865 6 gdevic 
                    ctl_bus_inc_oe=1; ctl_apin_mux2=1; /* Apin sourced from AL */
3866 
                    ctl_inc_limit6=1; /* Limit the incrementer to 6 bits */ end
3867 8 gdevic 
    if (M1 & T4) begin
3868 6 gdevic 
                    ctl_eval_cond=1; /* Evaluate flags condition based on the opcode[5:3] */ end
3869 
end
3870 
 
3871 8 gdevic 
// For all undecoded instructions, at M1/T4 advance a byte to the next opcode
3872 
if (~validPLA) begin
3873 
    if (M1 & T4) begin setM1=1; end
3874 
end
3875 
 
3876 
// The last cycle of an instruction is also the first cycle of the next one
3877 
if (setM1) begin
3878 
    begin
3879 
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
3880 
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
3881 
end
3882 
 

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