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// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.
 
// PROGRAM              "Quartus II 64-Bit"
// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED              "Sat Dec 10 09:02:54 2016"
 
module memory_ifc(
        clk,
        nM1_int,
        ctl_mRead,
        ctl_mWrite,
        in_intr,
        nreset,
        fIORead,
        fIOWrite,
        setM1,
        ctl_iorw,
        timings_en,
        iorq_Tw,
        nhold_clk_wait,
        nM1_out,
        nRFSH_out,
        nMREQ_out,
        nRD_out,
        nWR_out,
        nIORQ_out,
        latch_wait,
        wait_m1
);
 
 
input wire      clk;
input wire      nM1_int;
input wire      ctl_mRead;
input wire      ctl_mWrite;
input wire      in_intr;
input wire      nreset;
input wire      fIORead;
input wire      fIOWrite;
input wire      setM1;
input wire      ctl_iorw;
input wire      timings_en;
input wire      iorq_Tw;
input wire      nhold_clk_wait;
output wire     nM1_out;
output wire     nRFSH_out;
output wire     nMREQ_out;
output wire     nRD_out;
output wire     nWR_out;
output wire     nIORQ_out;
output wire     latch_wait;
output wire     wait_m1;
 
wire    intr_iorq;
wire    ioRead;
wire    iorq;
wire    ioWrite;
wire    m1_mreq;
wire    mrd_mreq;
wire    mwr_mreq;
reg     mwr_wr;
wire    nMEMRQ_int;
wire    nq2;
reg     q1;
reg     q2;
reg     wait_iorq;
reg     wait_m_ALTERA_SYNTHESIZED1;
reg     wait_mrd;
reg     wait_mwr;
wire    SYNTHESIZED_WIRE_0;
reg     DFFE_m1_ff3;
wire    SYNTHESIZED_WIRE_1;
reg     SYNTHESIZED_WIRE_15;
reg     DFFE_iorq_ff4;
reg     SYNTHESIZED_WIRE_16;
reg     DFFE_mrd_ff3;
reg     DFFE_intr_ff3;
wire    SYNTHESIZED_WIRE_2;
reg     SYNTHESIZED_WIRE_17;
wire    SYNTHESIZED_WIRE_3;
reg     SYNTHESIZED_WIRE_18;
wire    SYNTHESIZED_WIRE_19;
reg     DFFE_iorq_ff1;
reg     DFFE_m1_ff1;
reg     DFFE_mrd_ff1;
reg     DFFE_mwr_ff1;
reg     DFFE_mreq_ff2;
 
 
 
 
assign  nMREQ_out = SYNTHESIZED_WIRE_0 & nMEMRQ_int;
 
assign  ioRead = iorq & fIORead;
 
assign  SYNTHESIZED_WIRE_1 = ~(DFFE_m1_ff3 | wait_m_ALTERA_SYNTHESIZED1);
 
assign  m1_mreq = ~(in_intr | SYNTHESIZED_WIRE_1);
 
assign  iorq = SYNTHESIZED_WIRE_15 | DFFE_iorq_ff4 | SYNTHESIZED_WIRE_16;
 
assign  ioWrite = iorq & fIOWrite;
 
assign  latch_wait = wait_mrd | wait_iorq | wait_m_ALTERA_SYNTHESIZED1 | wait_mwr;
 
assign  nMEMRQ_int = ~(m1_mreq | mrd_mreq | mwr_mreq);
 
assign  nRD_out = ~(m1_mreq | mrd_mreq | ioRead);
 
assign  mrd_mreq = DFFE_mrd_ff3 | wait_mrd;
 
assign  nWR_out = ~(ioWrite | mwr_wr);
 
assign  mwr_mreq = mwr_wr | wait_mwr;
 
assign  nIORQ_out = ~(intr_iorq | iorq);
 
assign  intr_iorq = DFFE_intr_ff3 | wait_iorq;
 
assign  nM1_out = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_17;
 
assign  SYNTHESIZED_WIRE_0 = ~(SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_18);
 
assign  nRFSH_out = ~(nq2 & SYNTHESIZED_WIRE_17);
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
begin
if (!nreset)
        begin
        wait_iorq <= 0;
        end
else
        begin
        wait_iorq <= iorq_Tw;
        end
end
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
        begin
        DFFE_intr_ff3 <= 0;
        end
else
if (nhold_clk_wait)
        begin
        DFFE_intr_ff3 <= wait_iorq;
        end
end
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
        begin
        DFFE_iorq_ff1 <= 0;
        end
else
if (timings_en)
        begin
        DFFE_iorq_ff1 <= ctl_iorw;
        end
end
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
        begin
        SYNTHESIZED_WIRE_16 <= 0;
        end
else
if (timings_en)
        begin
        SYNTHESIZED_WIRE_16 <= DFFE_iorq_ff1;
        end
end
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
begin
if (!nreset)
        begin
        SYNTHESIZED_WIRE_15 <= 0;
        end
else
if (timings_en)
        begin
        SYNTHESIZED_WIRE_15 <= SYNTHESIZED_WIRE_16;
        end
end
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
begin
if (!nreset)
        begin
        DFFE_iorq_ff4 <= 0;
        end
else
if (timings_en)
        begin
        DFFE_iorq_ff4 <= SYNTHESIZED_WIRE_15;
        end
end
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
        begin
        SYNTHESIZED_WIRE_17 <= 0;
        end
else
if (timings_en)
        begin
        SYNTHESIZED_WIRE_17 <= nM1_int;
        end
end
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
begin
if (!nreset)
        begin
        DFFE_m1_ff1 <= 1;
        end
else
if (timings_en)
        begin
        DFFE_m1_ff1 <= setM1;
        end
end
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
begin
if (!nreset)
        begin
        wait_m_ALTERA_SYNTHESIZED1 <= 0;
        end
else
if (timings_en)
        begin
        wait_m_ALTERA_SYNTHESIZED1 <= DFFE_m1_ff1;
        end
end
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
        begin
        DFFE_m1_ff3 <= 0;
        end
else
if (timings_en)
        begin
        DFFE_m1_ff3 <= wait_m_ALTERA_SYNTHESIZED1;
        end
end
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
        begin
        DFFE_mrd_ff1 <= 0;
        end
else
if (timings_en)
        begin
        DFFE_mrd_ff1 <= ctl_mRead;
        end
end
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
begin
if (!nreset)
        begin
        wait_mrd <= 0;
        end
else
if (timings_en)
        begin
        wait_mrd <= DFFE_mrd_ff1;
        end
end
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
begin
if (!nreset)
        begin
        DFFE_mrd_ff3 <= 0;
        end
else
if (timings_en)
        begin
        DFFE_mrd_ff3 <= wait_mrd;
        end
end
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
begin
if (!nreset)
        begin
        SYNTHESIZED_WIRE_18 <= 0;
        end
else
if (timings_en)
        begin
        SYNTHESIZED_WIRE_18 <= SYNTHESIZED_WIRE_17;
        end
end
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
begin
if (!nreset)
        begin
        DFFE_mreq_ff2 <= 0;
        end
else
if (timings_en)
        begin
        DFFE_mreq_ff2 <= SYNTHESIZED_WIRE_18;
        end
end
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
        begin
        DFFE_mwr_ff1 <= 0;
        end
else
if (timings_en)
        begin
        DFFE_mwr_ff1 <= ctl_mWrite;
        end
end
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
begin
if (!nreset)
        begin
        wait_mwr <= 0;
        end
else
if (timings_en)
        begin
        wait_mwr <= DFFE_mwr_ff1;
        end
end
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
begin
if (!nreset)
        begin
        mwr_wr <= 0;
        end
else
if (timings_en)
        begin
        mwr_wr <= wait_mwr;
        end
end
 
assign  SYNTHESIZED_WIRE_19 =  ~clk;
 
assign  nq2 =  ~q2;
 
assign  SYNTHESIZED_WIRE_2 =  ~nreset;
 
assign  SYNTHESIZED_WIRE_3 =  ~DFFE_mreq_ff2;
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
        begin
        q1 <= 0;
        end
else
if (timings_en)
        begin
        q1 <= SYNTHESIZED_WIRE_17;
        end
end
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
        begin
        q2 <= 0;
        end
else
if (timings_en)
        begin
        q2 <= q1;
        end
end
 
assign  wait_m1 = wait_m_ALTERA_SYNTHESIZED1;
 
endmodule

Line No.	Rev	Author	Line
1	3	gdevic	`// Copyright (C) 1991-2013 Altera Corporation`
2			`// Your use of Altera Corporation's design tools, logic functions`
3			`// and other software and tools, and its AMPP partner logic`
4			`// functions, and any output files from any of the foregoing`
5			`// (including device programming or simulation files), and any`
6			`// associated documentation or information are expressly subject`
7			`// to the terms and conditions of the Altera Program License`
8			`// Subscription Agreement, Altera MegaCore Function License`
9			`// Agreement, or other applicable license agreement, including,`
10			`// without limitation, that your use is for the sole purpose of`
11			`// programming logic devices manufactured by Altera and sold by`
12			`// Altera or its authorized distributors. Please refer to the`
13			`// applicable agreement for further details.`
14
15			`// PROGRAM "Quartus II 64-Bit"`
16			`// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"`
17	16	gdevic	`// CREATED "Sat Dec 10 09:02:54 2016"`
18	3	gdevic
19			`module memory_ifc(`
20			`clk,`
21			`nM1_int,`
22			`ctl_mRead,`
23			`ctl_mWrite,`
24			`in_intr,`
25			`nreset,`
26			`fIORead,`
27			`fIOWrite,`
28			`setM1,`
29			`ctl_iorw,`
30			`timings_en,`
31			`iorq_Tw,`
32	16	gdevic	`nhold_clk_wait,`
33	3	gdevic	`nM1_out,`
34			`nRFSH_out,`
35			`nMREQ_out,`
36			`nRD_out,`
37			`nWR_out,`
38			`nIORQ_out,`
39	13	gdevic	`latch_wait,`
40			`wait_m1`
41	3	gdevic	`);`
42
43
44			`input wire clk;`
45			`input wire nM1_int;`
46			`input wire ctl_mRead;`
47			`input wire ctl_mWrite;`
48			`input wire in_intr;`
49			`input wire nreset;`
50			`input wire fIORead;`
51			`input wire fIOWrite;`
52			`input wire setM1;`
53			`input wire ctl_iorw;`
54			`input wire timings_en;`
55			`input wire iorq_Tw;`
56	16	gdevic	`input wire nhold_clk_wait;`
57	3	gdevic	`output wire nM1_out;`
58			`output wire nRFSH_out;`
59			`output wire nMREQ_out;`
60			`output wire nRD_out;`
61			`output wire nWR_out;`
62			`output wire nIORQ_out;`
63			`output wire latch_wait;`
64	13	gdevic	`output wire wait_m1;`
65	3	gdevic
66			`wire intr_iorq;`
67			`wire ioRead;`
68			`wire iorq;`
69			`wire ioWrite;`
70			`wire m1_mreq;`
71			`wire mrd_mreq;`
72			`wire mwr_mreq;`
73			`reg mwr_wr;`
74			`wire nMEMRQ_int;`
75			`wire nq2;`
76			`reg q1;`
77			`reg q2;`
78			`reg wait_iorq;`
79	13	gdevic	`reg wait_m_ALTERA_SYNTHESIZED1;`
80	3	gdevic	`reg wait_mrd;`
81			`reg wait_mwr;`
82			`wire SYNTHESIZED_WIRE_0;`
83			`reg DFFE_m1_ff3;`
84			`wire SYNTHESIZED_WIRE_1;`
85	16	gdevic	`reg SYNTHESIZED_WIRE_15;`
86			`reg DFFE_iorq_ff4;`
87	13	gdevic	`reg SYNTHESIZED_WIRE_16;`
88	3	gdevic	`reg DFFE_mrd_ff3;`
89			`reg DFFE_intr_ff3;`
90			`wire SYNTHESIZED_WIRE_2;`
91	16	gdevic	`reg SYNTHESIZED_WIRE_17;`
92			`wire SYNTHESIZED_WIRE_3;`
93	3	gdevic	`reg SYNTHESIZED_WIRE_18;`
94	16	gdevic	`wire SYNTHESIZED_WIRE_19;`
95	3	gdevic	`reg DFFE_iorq_ff1;`
96			`reg DFFE_m1_ff1;`
97			`reg DFFE_mrd_ff1;`
98			`reg DFFE_mwr_ff1;`
99			`reg DFFE_mreq_ff2;`
100
101
102
103
104			`assign nMREQ_out = SYNTHESIZED_WIRE_0 & nMEMRQ_int;`
105
106			`assign ioRead = iorq & fIORead;`
107
108	13	gdevic	`assign SYNTHESIZED_WIRE_1 = ~(DFFE_m1_ff3 \| wait_m_ALTERA_SYNTHESIZED1);`
109	3	gdevic
110			`assign m1_mreq = ~(in_intr \| SYNTHESIZED_WIRE_1);`
111
112	16	gdevic	`assign iorq = SYNTHESIZED_WIRE_15 \| DFFE_iorq_ff4 \| SYNTHESIZED_WIRE_16;`
113	3	gdevic
114			`assign ioWrite = iorq & fIOWrite;`
115
116	13	gdevic	`assign latch_wait = wait_mrd \| wait_iorq \| wait_m_ALTERA_SYNTHESIZED1 \| wait_mwr;`
117	3	gdevic
118			`assign nMEMRQ_int = ~(m1_mreq \| mrd_mreq \| mwr_mreq);`
119
120			`assign nRD_out = ~(m1_mreq \| mrd_mreq \| ioRead);`
121
122			`assign mrd_mreq = DFFE_mrd_ff3 \| wait_mrd;`
123
124			`assign nWR_out = ~(ioWrite \| mwr_wr);`
125
126			`assign mwr_mreq = mwr_wr \| wait_mwr;`
127
128			`assign nIORQ_out = ~(intr_iorq \| iorq);`
129
130			`assign intr_iorq = DFFE_intr_ff3 \| wait_iorq;`
131
132	16	gdevic	`assign nM1_out = SYNTHESIZED_WIRE_2 \| SYNTHESIZED_WIRE_17;`
133	3	gdevic
134	16	gdevic	`assign SYNTHESIZED_WIRE_0 = ~(SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_18);`
135	13	gdevic
136	16	gdevic	`assign nRFSH_out = ~(nq2 & SYNTHESIZED_WIRE_17);`
137	3	gdevic
138
139	16	gdevic	`always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)`
140	3	gdevic	`begin`
141			`if (!nreset)`
142			`begin`
143			`wait_iorq <= 0;`
144			`end`
145			`else`
146			`begin`
147			`wait_iorq <= iorq_Tw;`
148			`end`
149			`end`
150
151
152			`always@(posedge clk or negedge nreset)`
153			`begin`
154			`if (!nreset)`
155			`begin`
156			`DFFE_intr_ff3 <= 0;`
157			`end`
158			`else`
159	16	gdevic	`if (nhold_clk_wait)`
160	3	gdevic	`begin`
161			`DFFE_intr_ff3 <= wait_iorq;`
162			`end`
163			`end`
164
165
166			`always@(posedge clk or negedge nreset)`
167			`begin`
168			`if (!nreset)`
169			`begin`
170			`DFFE_iorq_ff1 <= 0;`
171			`end`
172			`else`
173			`if (timings_en)`
174			`begin`
175			`DFFE_iorq_ff1 <= ctl_iorw;`
176			`end`
177			`end`
178
179
180			`always@(posedge clk or negedge nreset)`
181			`begin`
182			`if (!nreset)`
183			`begin`
184	16	gdevic	`SYNTHESIZED_WIRE_16 <= 0;`
185	3	gdevic	`end`
186			`else`
187			`if (timings_en)`
188			`begin`
189	16	gdevic	`SYNTHESIZED_WIRE_16 <= DFFE_iorq_ff1;`
190	3	gdevic	`end`
191			`end`
192
193
194	16	gdevic	`always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)`
195	3	gdevic	`begin`
196			`if (!nreset)`
197			`begin`
198	16	gdevic	`SYNTHESIZED_WIRE_15 <= 0;`
199	3	gdevic	`end`
200			`else`
201			`if (timings_en)`
202			`begin`
203	16	gdevic	`SYNTHESIZED_WIRE_15 <= SYNTHESIZED_WIRE_16;`
204	3	gdevic	`end`
205			`end`
206
207
208	16	gdevic	`always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)`
209	3	gdevic	`begin`
210			`if (!nreset)`
211			`begin`
212			`DFFE_iorq_ff4 <= 0;`
213			`end`
214			`else`
215			`if (timings_en)`
216			`begin`
217	16	gdevic	`DFFE_iorq_ff4 <= SYNTHESIZED_WIRE_15;`
218	3	gdevic	`end`
219			`end`
220
221
222			`always@(posedge clk or negedge nreset)`
223			`begin`
224			`if (!nreset)`
225			`begin`
226	16	gdevic	`SYNTHESIZED_WIRE_17 <= 0;`
227	3	gdevic	`end`
228			`else`
229			`if (timings_en)`
230			`begin`
231	16	gdevic	`SYNTHESIZED_WIRE_17 <= nM1_int;`
232	3	gdevic	`end`
233			`end`
234
235
236	16	gdevic	`always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)`
237	3	gdevic	`begin`
238			`if (!nreset)`
239			`begin`
240			`DFFE_m1_ff1 <= 1;`
241			`end`
242			`else`
243			`if (timings_en)`
244			`begin`
245			`DFFE_m1_ff1 <= setM1;`
246			`end`
247			`end`
248
249
250	16	gdevic	`always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)`
251	3	gdevic	`begin`
252			`if (!nreset)`
253			`begin`
254	13	gdevic	`wait_m_ALTERA_SYNTHESIZED1 <= 0;`
255	3	gdevic	`end`
256			`else`
257			`if (timings_en)`
258			`begin`
259	13	gdevic	`wait_m_ALTERA_SYNTHESIZED1 <= DFFE_m1_ff1;`
260	3	gdevic	`end`
261			`end`
262
263
264			`always@(posedge clk or negedge nreset)`
265			`begin`
266			`if (!nreset)`
267			`begin`
268			`DFFE_m1_ff3 <= 0;`
269			`end`
270			`else`
271			`if (timings_en)`
272			`begin`
273	13	gdevic	`DFFE_m1_ff3 <= wait_m_ALTERA_SYNTHESIZED1;`
274	3	gdevic	`end`
275			`end`
276
277
278			`always@(posedge clk or negedge nreset)`
279			`begin`
280			`if (!nreset)`
281			`begin`
282			`DFFE_mrd_ff1 <= 0;`
283			`end`
284			`else`
285			`if (timings_en)`
286			`begin`
287			`DFFE_mrd_ff1 <= ctl_mRead;`
288			`end`
289			`end`
290
291
292	16	gdevic	`always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)`
293	3	gdevic	`begin`
294			`if (!nreset)`
295			`begin`
296			`wait_mrd <= 0;`
297			`end`
298			`else`
299			`if (timings_en)`
300			`begin`
301			`wait_mrd <= DFFE_mrd_ff1;`
302			`end`
303			`end`
304
305
306	16	gdevic	`always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)`
307	3	gdevic	`begin`
308			`if (!nreset)`
309			`begin`
310			`DFFE_mrd_ff3 <= 0;`
311			`end`
312			`else`
313			`if (timings_en)`
314			`begin`
315			`DFFE_mrd_ff3 <= wait_mrd;`
316			`end`
317			`end`
318
319
320	16	gdevic	`always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)`
321	3	gdevic	`begin`
322			`if (!nreset)`
323			`begin`
324	16	gdevic	`SYNTHESIZED_WIRE_18 <= 0;`
325	3	gdevic	`end`
326			`else`
327			`if (timings_en)`
328			`begin`
329	16	gdevic	`SYNTHESIZED_WIRE_18 <= SYNTHESIZED_WIRE_17;`
330	3	gdevic	`end`
331			`end`
332
333
334	16	gdevic	`always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)`
335	3	gdevic	`begin`
336			`if (!nreset)`
337			`begin`
338			`DFFE_mreq_ff2 <= 0;`
339			`end`
340			`else`
341			`if (timings_en)`
342			`begin`
343	16	gdevic	`DFFE_mreq_ff2 <= SYNTHESIZED_WIRE_18;`
344	3	gdevic	`end`
345			`end`
346
347
348			`always@(posedge clk or negedge nreset)`
349			`begin`
350			`if (!nreset)`
351			`begin`
352			`DFFE_mwr_ff1 <= 0;`
353			`end`
354			`else`
355			`if (timings_en)`
356			`begin`
357			`DFFE_mwr_ff1 <= ctl_mWrite;`
358			`end`
359			`end`
360
361
362	16	gdevic	`always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)`
363	3	gdevic	`begin`
364			`if (!nreset)`
365			`begin`
366			`wait_mwr <= 0;`
367			`end`
368			`else`
369			`if (timings_en)`
370			`begin`
371			`wait_mwr <= DFFE_mwr_ff1;`
372			`end`
373			`end`
374
375
376	16	gdevic	`always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)`
377	3	gdevic	`begin`
378			`if (!nreset)`
379			`begin`
380			`mwr_wr <= 0;`
381			`end`
382			`else`
383			`if (timings_en)`
384			`begin`
385			`mwr_wr <= wait_mwr;`
386			`end`
387			`end`
388
389	16	gdevic	`assign SYNTHESIZED_WIRE_19 = ~clk;`
390	3	gdevic
391			`assign nq2 = ~q2;`
392
393	13	gdevic	`assign SYNTHESIZED_WIRE_2 = ~nreset;`
394	3	gdevic
395	13	gdevic	`assign SYNTHESIZED_WIRE_3 = ~DFFE_mreq_ff2;`
396	3	gdevic
397	13	gdevic
398	3	gdevic	`always@(posedge clk or negedge nreset)`
399			`begin`
400			`if (!nreset)`
401			`begin`
402			`q1 <= 0;`
403			`end`
404			`else`
405			`if (timings_en)`
406			`begin`
407	16	gdevic	`q1 <= SYNTHESIZED_WIRE_17;`
408	3	gdevic	`end`
409			`end`
410
411
412			`always@(posedge clk or negedge nreset)`
413			`begin`
414			`if (!nreset)`
415			`begin`
416			`q2 <= 0;`
417			`end`
418			`else`
419			`if (timings_en)`
420			`begin`
421			`q2 <= q1;`
422			`end`
423			`end`
424
425	13	gdevic	`assign wait_m1 = wait_m_ALTERA_SYNTHESIZED1;`
426	3	gdevic
427			`endmodule`

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