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[/] [a-z80/] [trunk/] [cpu/] [control/] [memory_ifc.v] - Blame information for rev 20

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1 3 gdevic
// Copyright (C) 1991-2013 Altera Corporation
2
// Your use of Altera Corporation's design tools, logic functions 
3
// and other software and tools, and its AMPP partner logic 
4
// functions, and any output files from any of the foregoing 
5
// (including device programming or simulation files), and any 
6
// associated documentation or information are expressly subject 
7
// to the terms and conditions of the Altera Program License 
8
// Subscription Agreement, Altera MegaCore Function License 
9
// Agreement, or other applicable license agreement, including, 
10
// without limitation, that your use is for the sole purpose of 
11
// programming logic devices manufactured by Altera and sold by 
12
// Altera or its authorized distributors.  Please refer to the 
13
// applicable agreement for further details.
14
 
15
// PROGRAM              "Quartus II 64-Bit"
16
// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
17 20 gdevic
// CREATED              "Sun Dec 09 19:14:29 2018"
18 3 gdevic
 
19
module memory_ifc(
20
        clk,
21
        nM1_int,
22
        ctl_mRead,
23
        ctl_mWrite,
24
        in_intr,
25
        nreset,
26
        fIORead,
27
        fIOWrite,
28
        setM1,
29
        ctl_iorw,
30
        timings_en,
31
        iorq_Tw,
32 16 gdevic
        nhold_clk_wait,
33 3 gdevic
        nM1_out,
34
        nRFSH_out,
35
        nMREQ_out,
36
        nRD_out,
37
        nWR_out,
38
        nIORQ_out,
39 13 gdevic
        latch_wait,
40
        wait_m1
41 3 gdevic
);
42
 
43
 
44
input wire      clk;
45
input wire      nM1_int;
46
input wire      ctl_mRead;
47
input wire      ctl_mWrite;
48
input wire      in_intr;
49
input wire      nreset;
50
input wire      fIORead;
51
input wire      fIOWrite;
52
input wire      setM1;
53
input wire      ctl_iorw;
54
input wire      timings_en;
55
input wire      iorq_Tw;
56 16 gdevic
input wire      nhold_clk_wait;
57 3 gdevic
output wire     nM1_out;
58
output wire     nRFSH_out;
59
output wire     nMREQ_out;
60
output wire     nRD_out;
61
output wire     nWR_out;
62
output wire     nIORQ_out;
63
output wire     latch_wait;
64 13 gdevic
output wire     wait_m1;
65 3 gdevic
 
66
wire    intr_iorq;
67
wire    ioRead;
68
wire    iorq;
69
wire    ioWrite;
70
wire    m1_mreq;
71
wire    mrd_mreq;
72
wire    mwr_mreq;
73
reg     mwr_wr;
74
wire    nMEMRQ_int;
75
wire    nq2;
76
reg     q1;
77
reg     q2;
78 18 gdevic
wire    wait_io;
79 3 gdevic
reg     wait_iorq;
80 18 gdevic
reg     wait_iorqinta;
81 13 gdevic
reg     wait_m_ALTERA_SYNTHESIZED1;
82 3 gdevic
reg     wait_mrd;
83
reg     wait_mwr;
84
wire    SYNTHESIZED_WIRE_0;
85
reg     DFFE_m1_ff3;
86
wire    SYNTHESIZED_WIRE_1;
87 18 gdevic
reg     DFFE_iorq_ff4;
88 16 gdevic
reg     SYNTHESIZED_WIRE_15;
89 3 gdevic
reg     DFFE_mrd_ff3;
90
reg     DFFE_intr_ff3;
91
wire    SYNTHESIZED_WIRE_2;
92 18 gdevic
reg     SYNTHESIZED_WIRE_16;
93
wire    SYNTHESIZED_WIRE_3;
94 16 gdevic
reg     SYNTHESIZED_WIRE_17;
95 18 gdevic
wire    SYNTHESIZED_WIRE_18;
96 3 gdevic
reg     DFFE_iorq_ff1;
97
reg     DFFE_m1_ff1;
98
reg     DFFE_mrd_ff1;
99
reg     DFFE_mwr_ff1;
100
reg     DFFE_mreq_ff2;
101
 
102
 
103
 
104
 
105
assign  nMREQ_out = SYNTHESIZED_WIRE_0 & nMEMRQ_int;
106
 
107
assign  ioRead = iorq & fIORead;
108
 
109 13 gdevic
assign  SYNTHESIZED_WIRE_1 = ~(DFFE_m1_ff3 | wait_m_ALTERA_SYNTHESIZED1);
110 3 gdevic
 
111
assign  m1_mreq = ~(in_intr | SYNTHESIZED_WIRE_1);
112
 
113 18 gdevic
assign  iorq = wait_iorq | DFFE_iorq_ff4 | SYNTHESIZED_WIRE_15;
114 3 gdevic
 
115
assign  ioWrite = iorq & fIOWrite;
116
 
117 18 gdevic
assign  latch_wait = wait_mrd | wait_io | wait_m_ALTERA_SYNTHESIZED1 | wait_mwr;
118 3 gdevic
 
119
assign  nMEMRQ_int = ~(m1_mreq | mrd_mreq | mwr_mreq);
120
 
121
assign  nRD_out = ~(m1_mreq | mrd_mreq | ioRead);
122
 
123
assign  mrd_mreq = DFFE_mrd_ff3 | wait_mrd;
124
 
125
assign  nWR_out = ~(ioWrite | mwr_wr);
126
 
127
assign  mwr_mreq = mwr_wr | wait_mwr;
128
 
129
assign  nIORQ_out = ~(intr_iorq | iorq);
130
 
131 18 gdevic
assign  wait_io = wait_iorqinta | wait_iorq;
132 3 gdevic
 
133 18 gdevic
assign  intr_iorq = DFFE_intr_ff3 | wait_iorqinta;
134 3 gdevic
 
135 18 gdevic
assign  nM1_out = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_16;
136 13 gdevic
 
137 18 gdevic
assign  SYNTHESIZED_WIRE_0 = ~(SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_17);
138 3 gdevic
 
139 18 gdevic
assign  nRFSH_out = ~(nq2 & SYNTHESIZED_WIRE_16);
140 3 gdevic
 
141 18 gdevic
 
142
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
143 3 gdevic
begin
144
if (!nreset)
145
        begin
146 18 gdevic
        wait_iorqinta <= 0;
147 3 gdevic
        end
148
else
149
        begin
150 18 gdevic
        wait_iorqinta <= iorq_Tw;
151 3 gdevic
        end
152
end
153
 
154
 
155
always@(posedge clk or negedge nreset)
156
begin
157
if (!nreset)
158
        begin
159
        DFFE_intr_ff3 <= 0;
160
        end
161
else
162 16 gdevic
if (nhold_clk_wait)
163 3 gdevic
        begin
164 18 gdevic
        DFFE_intr_ff3 <= wait_iorqinta;
165 3 gdevic
        end
166
end
167
 
168
 
169
always@(posedge clk or negedge nreset)
170
begin
171
if (!nreset)
172
        begin
173
        DFFE_iorq_ff1 <= 0;
174
        end
175
else
176
if (timings_en)
177
        begin
178
        DFFE_iorq_ff1 <= ctl_iorw;
179
        end
180
end
181
 
182
 
183
always@(posedge clk or negedge nreset)
184
begin
185
if (!nreset)
186
        begin
187 18 gdevic
        SYNTHESIZED_WIRE_15 <= 0;
188 3 gdevic
        end
189
else
190
if (timings_en)
191
        begin
192 18 gdevic
        SYNTHESIZED_WIRE_15 <= DFFE_iorq_ff1;
193 3 gdevic
        end
194
end
195
 
196
 
197 18 gdevic
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
198 3 gdevic
begin
199
if (!nreset)
200
        begin
201 18 gdevic
        wait_iorq <= 0;
202 3 gdevic
        end
203
else
204
if (timings_en)
205
        begin
206 18 gdevic
        wait_iorq <= SYNTHESIZED_WIRE_15;
207 3 gdevic
        end
208
end
209
 
210
 
211 18 gdevic
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
212 3 gdevic
begin
213
if (!nreset)
214
        begin
215
        DFFE_iorq_ff4 <= 0;
216
        end
217
else
218
if (timings_en)
219
        begin
220 18 gdevic
        DFFE_iorq_ff4 <= wait_iorq;
221 3 gdevic
        end
222
end
223
 
224
 
225
always@(posedge clk or negedge nreset)
226
begin
227
if (!nreset)
228
        begin
229 18 gdevic
        SYNTHESIZED_WIRE_16 <= 0;
230 3 gdevic
        end
231
else
232
if (timings_en)
233
        begin
234 18 gdevic
        SYNTHESIZED_WIRE_16 <= nM1_int;
235 3 gdevic
        end
236
end
237
 
238
 
239 18 gdevic
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
240 3 gdevic
begin
241
if (!nreset)
242
        begin
243
        DFFE_m1_ff1 <= 1;
244
        end
245
else
246
if (timings_en)
247
        begin
248
        DFFE_m1_ff1 <= setM1;
249
        end
250
end
251
 
252
 
253 18 gdevic
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
254 3 gdevic
begin
255
if (!nreset)
256
        begin
257 13 gdevic
        wait_m_ALTERA_SYNTHESIZED1 <= 0;
258 3 gdevic
        end
259
else
260
if (timings_en)
261
        begin
262 13 gdevic
        wait_m_ALTERA_SYNTHESIZED1 <= DFFE_m1_ff1;
263 3 gdevic
        end
264
end
265
 
266
 
267
always@(posedge clk or negedge nreset)
268
begin
269
if (!nreset)
270
        begin
271
        DFFE_m1_ff3 <= 0;
272
        end
273
else
274
if (timings_en)
275
        begin
276 13 gdevic
        DFFE_m1_ff3 <= wait_m_ALTERA_SYNTHESIZED1;
277 3 gdevic
        end
278
end
279
 
280
 
281
always@(posedge clk or negedge nreset)
282
begin
283
if (!nreset)
284
        begin
285
        DFFE_mrd_ff1 <= 0;
286
        end
287
else
288
if (timings_en)
289
        begin
290
        DFFE_mrd_ff1 <= ctl_mRead;
291
        end
292
end
293
 
294
 
295 18 gdevic
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
296 3 gdevic
begin
297
if (!nreset)
298
        begin
299
        wait_mrd <= 0;
300
        end
301
else
302
if (timings_en)
303
        begin
304
        wait_mrd <= DFFE_mrd_ff1;
305
        end
306
end
307
 
308
 
309 18 gdevic
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
310 3 gdevic
begin
311
if (!nreset)
312
        begin
313
        DFFE_mrd_ff3 <= 0;
314
        end
315
else
316
if (timings_en)
317
        begin
318
        DFFE_mrd_ff3 <= wait_mrd;
319
        end
320
end
321
 
322
 
323 18 gdevic
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
324 3 gdevic
begin
325
if (!nreset)
326
        begin
327 18 gdevic
        SYNTHESIZED_WIRE_17 <= 0;
328 3 gdevic
        end
329
else
330
if (timings_en)
331
        begin
332 18 gdevic
        SYNTHESIZED_WIRE_17 <= SYNTHESIZED_WIRE_16;
333 3 gdevic
        end
334
end
335
 
336
 
337 18 gdevic
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
338 3 gdevic
begin
339
if (!nreset)
340
        begin
341
        DFFE_mreq_ff2 <= 0;
342
        end
343
else
344
if (timings_en)
345
        begin
346 18 gdevic
        DFFE_mreq_ff2 <= SYNTHESIZED_WIRE_17;
347 3 gdevic
        end
348
end
349
 
350
 
351
always@(posedge clk or negedge nreset)
352
begin
353
if (!nreset)
354
        begin
355
        DFFE_mwr_ff1 <= 0;
356
        end
357
else
358
if (timings_en)
359
        begin
360
        DFFE_mwr_ff1 <= ctl_mWrite;
361
        end
362
end
363
 
364
 
365 18 gdevic
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
366 3 gdevic
begin
367
if (!nreset)
368
        begin
369
        wait_mwr <= 0;
370
        end
371
else
372
if (timings_en)
373
        begin
374
        wait_mwr <= DFFE_mwr_ff1;
375
        end
376
end
377
 
378
 
379 18 gdevic
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
380 3 gdevic
begin
381
if (!nreset)
382
        begin
383
        mwr_wr <= 0;
384
        end
385
else
386
if (timings_en)
387
        begin
388
        mwr_wr <= wait_mwr;
389
        end
390
end
391
 
392 18 gdevic
assign  SYNTHESIZED_WIRE_18 =  ~clk;
393 3 gdevic
 
394
assign  nq2 =  ~q2;
395
 
396 13 gdevic
assign  SYNTHESIZED_WIRE_2 =  ~nreset;
397 3 gdevic
 
398 13 gdevic
assign  SYNTHESIZED_WIRE_3 =  ~DFFE_mreq_ff2;
399 3 gdevic
 
400 13 gdevic
 
401 3 gdevic
always@(posedge clk or negedge nreset)
402
begin
403
if (!nreset)
404
        begin
405
        q1 <= 0;
406
        end
407
else
408
if (timings_en)
409
        begin
410 18 gdevic
        q1 <= SYNTHESIZED_WIRE_16;
411 3 gdevic
        end
412
end
413
 
414
 
415
always@(posedge clk or negedge nreset)
416
begin
417
if (!nreset)
418
        begin
419
        q2 <= 0;
420
        end
421
else
422
if (timings_en)
423
        begin
424
        q2 <= q1;
425
        end
426
end
427
 
428 13 gdevic
assign  wait_m1 = wait_m_ALTERA_SYNTHESIZED1;
429 3 gdevic
 
430
endmodule

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