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[/] [a-z80/] [trunk/] [cpu/] [control/] [sequencer.v] - Blame information for rev 3

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1 3 gdevic 
// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors.  Please refer to the
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// applicable agreement for further details.
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// PROGRAM              "Quartus II 64-Bit"
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// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED              "Sun Nov 16 23:11:10 2014"
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19 
module sequencer(
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        clk,
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        nextM,
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        setM1,
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        nreset,
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        hold_clk_iorq,
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        hold_clk_wait,
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        hold_clk_busrq,
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        M1,
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        M2,
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        M3,
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        M4,
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        M5,
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        M6,
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        T1,
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        T2,
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        T3,
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        T4,
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        T5,
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        T6,
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        timings_en
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);
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42 
 
43 
input wire      clk;
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input wire      nextM;
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input wire      setM1;
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input wire      nreset;
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input wire      hold_clk_iorq;
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input wire      hold_clk_wait;
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input wire      hold_clk_busrq;
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output wire     M1;
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output wire     M2;
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output wire     M3;
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output wire     M4;
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output wire     M5;
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output reg      M6;
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output wire     T1;
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output wire     T2;
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output wire     T3;
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output wire     T4;
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output wire     T5;
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output reg      T6;
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output wire     timings_en;
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wire    ena_M;
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wire    ena_T;
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reg     DFFE_M4_ff;
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wire    SYNTHESIZED_WIRE_20;
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reg     DFFE_M5_ff;
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reg     DFFE_T1_ff;
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wire    SYNTHESIZED_WIRE_21;
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reg     DFFE_T2_ff;
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reg     DFFE_T3_ff;
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reg     DFFE_T4_ff;
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reg     DFFE_T5_ff;
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reg     DFFE_M1_ff;
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reg     DFFE_M2_ff;
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reg     DFFE_M3_ff;
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wire    SYNTHESIZED_WIRE_10;
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wire    SYNTHESIZED_WIRE_11;
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wire    SYNTHESIZED_WIRE_12;
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wire    SYNTHESIZED_WIRE_13;
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wire    SYNTHESIZED_WIRE_14;
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wire    SYNTHESIZED_WIRE_15;
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wire    SYNTHESIZED_WIRE_16;
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wire    SYNTHESIZED_WIRE_17;
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wire    SYNTHESIZED_WIRE_18;
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wire    SYNTHESIZED_WIRE_19;
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assign  M1 = DFFE_M1_ff;
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assign  M2 = DFFE_M2_ff;
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assign  M3 = DFFE_M3_ff;
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assign  M4 = DFFE_M4_ff;
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assign  M5 = DFFE_M5_ff;
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assign  T1 = DFFE_T1_ff;
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assign  T2 = DFFE_T2_ff;
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assign  T3 = DFFE_T3_ff;
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assign  T4 = DFFE_T4_ff;
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assign  T5 = DFFE_T5_ff;
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assign  SYNTHESIZED_WIRE_13 = DFFE_M4_ff & SYNTHESIZED_WIRE_20;
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assign  SYNTHESIZED_WIRE_14 = DFFE_M5_ff & SYNTHESIZED_WIRE_20;
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assign  SYNTHESIZED_WIRE_15 = DFFE_T1_ff & SYNTHESIZED_WIRE_21;
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assign  SYNTHESIZED_WIRE_16 = DFFE_T2_ff & SYNTHESIZED_WIRE_21;
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assign  SYNTHESIZED_WIRE_17 = DFFE_T3_ff & SYNTHESIZED_WIRE_21;
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assign  SYNTHESIZED_WIRE_18 = DFFE_T4_ff & SYNTHESIZED_WIRE_21;
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assign  SYNTHESIZED_WIRE_19 = DFFE_T5_ff & SYNTHESIZED_WIRE_21;
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assign  SYNTHESIZED_WIRE_10 = DFFE_M1_ff & SYNTHESIZED_WIRE_20;
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assign  SYNTHESIZED_WIRE_11 = DFFE_M2_ff & SYNTHESIZED_WIRE_20;
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assign  SYNTHESIZED_WIRE_12 = DFFE_M3_ff & SYNTHESIZED_WIRE_20;
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assign  ena_T = ~(hold_clk_iorq | hold_clk_wait | hold_clk_busrq);
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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        begin
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        DFFE_M1_ff <= 1;
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        end
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else
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if (ena_M)
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        begin
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        DFFE_M1_ff <= setM1;
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        end
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end
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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        begin
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        DFFE_M2_ff <= 0;
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        end
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else
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if (ena_M)
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        begin
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        DFFE_M2_ff <= SYNTHESIZED_WIRE_10;
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        end
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end
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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        begin
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        DFFE_M3_ff <= 0;
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        end
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else
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if (ena_M)
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        begin
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        DFFE_M3_ff <= SYNTHESIZED_WIRE_11;
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        end
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end
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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        begin
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        DFFE_M4_ff <= 0;
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        end
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else
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if (ena_M)
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        begin
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        DFFE_M4_ff <= SYNTHESIZED_WIRE_12;
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        end
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end
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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        begin
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        DFFE_M5_ff <= 0;
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        end
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else
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if (ena_M)
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        begin
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        DFFE_M5_ff <= SYNTHESIZED_WIRE_13;
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        end
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end
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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        begin
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        M6 <= 0;
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        end
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else
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if (ena_M)
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        begin
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        M6 <= SYNTHESIZED_WIRE_14;
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        end
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end
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assign  SYNTHESIZED_WIRE_21 =  ~ena_M;
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assign  SYNTHESIZED_WIRE_20 =  ~setM1;
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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        begin
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        DFFE_T1_ff <= 1;
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        end
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else
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if (ena_T)
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        begin
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        DFFE_T1_ff <= ena_M;
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        end
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end
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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        begin
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        DFFE_T2_ff <= 0;
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        end
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else
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if (ena_T)
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        begin
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        DFFE_T2_ff <= SYNTHESIZED_WIRE_15;
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        end
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end
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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        begin
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        DFFE_T3_ff <= 0;
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        end
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else
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if (ena_T)
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        begin
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        DFFE_T3_ff <= SYNTHESIZED_WIRE_16;
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        end
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end
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always@(posedge clk or negedge nreset)
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begin
257 
if (!nreset)
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        begin
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        DFFE_T4_ff <= 0;
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        end
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else
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if (ena_T)
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        begin
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        DFFE_T4_ff <= SYNTHESIZED_WIRE_17;
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        end
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end
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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        begin
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        DFFE_T5_ff <= 0;
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        end
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else
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if (ena_T)
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        begin
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        DFFE_T5_ff <= SYNTHESIZED_WIRE_18;
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        end
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end
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283 
always@(posedge clk or negedge nreset)
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begin
285 
if (!nreset)
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        begin
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        T6 <= 0;
288 
        end
289 
else
290 
if (ena_T)
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        begin
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        T6 <= SYNTHESIZED_WIRE_19;
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        end
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end
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296 
assign  ena_M = nextM;
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assign  timings_en = ena_T;
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endmodule

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