OpenCores
URL https://opencores.org/ocsvn/a-z80/a-z80/trunk

Subversion Repositories a-z80

[/] [a-z80/] [trunk/] [cpu/] [top-level-files.txt] - Blame information for rev 3

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 gdevic
This is a list of source files that are part of the top-level design.
2
It is read by various Python scripts for the top level integration and
3
synthesis. Every line that does not refer to a valid file is ignored.
4
 
5
------ Control block -------
6
control/clk_delay.v
7
control/decode_state.v
8
control/exec_module.i
9
control/execute.sv
10
control/interrupts.v
11
control/ir.v
12
control/pin_control.v
13
control/pla_decode.sv
14
control/resets.v
15
control/memory_ifc.v
16
control/sequencer.v
17
 
18
---------- ALU -------------
19
alu/alu_control.v
20
alu/alu_select.v
21
alu/alu_flags.v
22
alu/alu.v
23
 
24
------ Register file -------
25
registers/reg_file.v
26
registers/reg_control.v
27
 
28
------ Address latch -------
29
bus/address_latch.v
30
bus/address_pins.v
31
 
32
--------- Misc bus ---------
33
bus/bus_control.v
34
bus/bus_switch.sv
35
 
36
------ I/O pin control -----
37
bus/data_pins.v
38
bus/control_pins_n.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.