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[/] [a-z80/] [trunk/] [cpu/] [top-level-files.txt] - Blame information for rev 8

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This is a list of A-Z80 top-level files and their dependencies.
These files comprise the A-Z80 CPU proper. Use export.py to copy
them into your project folder.
 
------ Control block -------
control/clk_delay.v
control/decode_state.v
control/exec_module.vh
control/execute.v
+ control/exec_matrix.vh
+ control/exec_matrix_compiled.vh
+ control/exec_module.vh
+ control/exec_zero.vh
+ control/temp_wires.vh
control/interrupts.v
control/ir.v
control/pin_control.v
control/pla_decode.v
control/resets.v
control/memory_ifc.v
control/sequencer.v
 
---------- ALU -------------
alu/alu_control.v
+ alu/alu_mux_4.v
+ alu/alu_mux_8.v
alu/alu_select.v
alu/alu_flags.v
+ alu/alu_mux_2.v
+ alu/alu_mux_4.v
alu/alu.v
+ alu/alu_core.v
+ alu/alu_slice.v
+ alu/alu_bit_select.v
+ alu/alu_shifter_core.v
+ alu/alu_mux_2z.v
+ alu/alu_mux_3z.v
+ alu/alu_prep_daa.v
 
------ Register file -------
registers/reg_file.v
+ registers/reg_latch.v
registers/reg_control.v
 
------ Address latch -------
bus/address_latch.v
+ bus/address_mux.v
+ bus/inc_dec.v
+ bus/inc_dec_2bit.v
bus/address_pins.v
 
--------- Misc bus ---------
bus/bus_control.v
bus/bus_switch.v
+ bus/data_switch.v
+ bus/data_switch_mask.v
 
------ I/O pin control -----
bus/data_pins.v
bus/control_pins_n.v
 
--------- Top level --------
+ toplevel/z80_top_direct_n.v
+ toplevel/core.vh
+ toplevel/coremodules.vh
+ toplevel/globals.vh
 
Files=49

Line No.	Rev	Author	Line
1	8	gdevic	`This is a list of A-Z80 top-level files and their dependencies.`
2			`These files comprise the A-Z80 CPU proper. Use export.py to copy`
3			`them into your project folder.`
4	3	gdevic
5			`------ Control block -------`
6			`control/clk_delay.v`
7			`control/decode_state.v`
8	6	gdevic	`control/exec_module.vh`
9	8	gdevic	`control/execute.v`
10			`+ control/exec_matrix.vh`
11			`+ control/exec_matrix_compiled.vh`
12			`+ control/exec_module.vh`
13			`+ control/exec_zero.vh`
14			`+ control/temp_wires.vh`
15	3	gdevic	`control/interrupts.v`
16			`control/ir.v`
17			`control/pin_control.v`
18	8	gdevic	`control/pla_decode.v`
19	3	gdevic	`control/resets.v`
20			`control/memory_ifc.v`
21			`control/sequencer.v`
22
23			`---------- ALU -------------`
24			`alu/alu_control.v`
25	8	gdevic	`+ alu/alu_mux_4.v`
26			`+ alu/alu_mux_8.v`
27	3	gdevic	`alu/alu_select.v`
28			`alu/alu_flags.v`
29	8	gdevic	`+ alu/alu_mux_2.v`
30			`+ alu/alu_mux_4.v`
31	3	gdevic	`alu/alu.v`
32	8	gdevic	`+ alu/alu_core.v`
33			`+ alu/alu_slice.v`
34			`+ alu/alu_bit_select.v`
35			`+ alu/alu_shifter_core.v`
36			`+ alu/alu_mux_2z.v`
37			`+ alu/alu_mux_3z.v`
38			`+ alu/alu_prep_daa.v`
39	3	gdevic
40			`------ Register file -------`
41			`registers/reg_file.v`
42	8	gdevic	`+ registers/reg_latch.v`
43	3	gdevic	`registers/reg_control.v`
44
45			`------ Address latch -------`
46			`bus/address_latch.v`
47	8	gdevic	`+ bus/address_mux.v`
48			`+ bus/inc_dec.v`
49			`+ bus/inc_dec_2bit.v`
50	3	gdevic	`bus/address_pins.v`
51
52			`--------- Misc bus ---------`
53			`bus/bus_control.v`
54	8	gdevic	`bus/bus_switch.v`
55			`+ bus/data_switch.v`
56			`+ bus/data_switch_mask.v`
57	3	gdevic
58			`------ I/O pin control -----`
59			`bus/data_pins.v`
60			`bus/control_pins_n.v`
61	8	gdevic
62			`--------- Top level --------`
63			`+ toplevel/z80_top_direct_n.v`
64			`+ toplevel/core.vh`
65			`+ toplevel/coremodules.vh`
66			`+ toplevel/globals.vh`
67
68			`Files=49`

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[/] [a-z80/] [trunk/] [cpu/] [top-level-files.txt] - Blame information for rev 8