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8 |
gdevic |
// Automatically generated by gencoremodules.py
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clk_delay clk_delay_(
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.clk (clk),
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.in_intr (in_intr),
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.nreset (nreset),
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.T1 (T1),
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.latch_wait (latch_wait),
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.mwait (mwait),
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.M1 (M1),
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.busrq (busrq),
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.setM1 (setM1),
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.hold_clk_iorq (hold_clk_iorq),
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.hold_clk_wait (hold_clk_wait),
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.iorq_Tw (iorq_Tw),
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| 16 |
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.busack (busack),
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.pin_control_oe (pin_control_oe),
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.hold_clk_busrq (hold_clk_busrq)
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);
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decode_state decode_state_(
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.ctl_state_iy_set (ctl_state_iy_set),
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.ctl_state_ixiy_clr (ctl_state_ixiy_clr),
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.ctl_state_ixiy_we (ctl_state_ixiy_we),
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.ctl_state_halt_set (ctl_state_halt_set),
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.ctl_state_tbl_ed_set (ctl_state_tbl_ed_set),
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.ctl_state_tbl_cb_set (ctl_state_tbl_cb_set),
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.ctl_state_alu (ctl_state_alu),
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.clk (clk),
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.address_is_1 (address_is_1),
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.ctl_repeat_we (ctl_repeat_we),
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.in_intr (in_intr),
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.in_nmi (in_nmi),
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.nreset (nreset),
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13 |
gdevic |
.ctl_state_tbl_we (ctl_state_tbl_we),
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.hold_clk_wait (hold_clk_wait),
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8 |
gdevic |
.in_halt (in_halt),
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.table_cb (table_cb),
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.table_ed (table_ed),
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.table_xx (table_xx),
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.use_ix (use_ix),
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.use_ixiy (use_ixiy),
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.in_alu (in_alu),
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| 44 |
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.repeat_en (repeat_en)
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);
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execute execute_(
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.ctl_state_iy_set (ctl_state_iy_set),
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.ctl_state_ixiy_clr (ctl_state_ixiy_clr),
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.ctl_state_ixiy_we (ctl_state_ixiy_we),
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.ctl_state_halt_set (ctl_state_halt_set),
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.ctl_state_tbl_ed_set (ctl_state_tbl_ed_set),
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.ctl_state_tbl_cb_set (ctl_state_tbl_cb_set),
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.ctl_state_alu (ctl_state_alu),
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.ctl_repeat_we (ctl_repeat_we),
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| 56 |
13 |
gdevic |
.ctl_state_tbl_we (ctl_state_tbl_we),
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8 |
gdevic |
.ctl_iff1_iff2 (ctl_iff1_iff2),
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.ctl_iffx_we (ctl_iffx_we),
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.ctl_iffx_bit (ctl_iffx_bit),
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.ctl_im_we (ctl_im_we),
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.ctl_no_ints (ctl_no_ints),
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.ctl_ir_we (ctl_ir_we),
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.ctl_mRead (ctl_mRead),
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.ctl_mWrite (ctl_mWrite),
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.ctl_iorw (ctl_iorw),
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.ctl_shift_en (ctl_shift_en),
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.ctl_daa_oe (ctl_daa_oe),
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.ctl_alu_op_low (ctl_alu_op_low),
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.ctl_cond_short (ctl_cond_short),
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.ctl_alu_core_hf (ctl_alu_core_hf),
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.ctl_eval_cond (ctl_eval_cond),
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.ctl_66_oe (ctl_66_oe),
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.ctl_pf_sel (ctl_pf_sel),
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.ctl_alu_oe (ctl_alu_oe),
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.ctl_alu_shift_oe (ctl_alu_shift_oe),
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.ctl_alu_op2_oe (ctl_alu_op2_oe),
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.ctl_alu_res_oe (ctl_alu_res_oe),
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.ctl_alu_op1_oe (ctl_alu_op1_oe),
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.ctl_alu_bs_oe (ctl_alu_bs_oe),
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.ctl_alu_op1_sel_bus (ctl_alu_op1_sel_bus),
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.ctl_alu_op1_sel_low (ctl_alu_op1_sel_low),
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.ctl_alu_op1_sel_zero (ctl_alu_op1_sel_zero),
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.ctl_alu_op2_sel_zero (ctl_alu_op2_sel_zero),
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.ctl_alu_op2_sel_bus (ctl_alu_op2_sel_bus),
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.ctl_alu_op2_sel_lq (ctl_alu_op2_sel_lq),
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.ctl_alu_sel_op2_neg (ctl_alu_sel_op2_neg),
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.ctl_alu_sel_op2_high (ctl_alu_sel_op2_high),
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.ctl_alu_core_R (ctl_alu_core_R),
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.ctl_alu_core_V (ctl_alu_core_V),
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.ctl_alu_core_S (ctl_alu_core_S),
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.ctl_flags_oe (ctl_flags_oe),
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.ctl_flags_bus (ctl_flags_bus),
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.ctl_flags_alu (ctl_flags_alu),
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.ctl_flags_nf_set (ctl_flags_nf_set),
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.ctl_flags_cf_set (ctl_flags_cf_set),
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.ctl_flags_cf_cpl (ctl_flags_cf_cpl),
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.ctl_flags_cf_we (ctl_flags_cf_we),
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.ctl_flags_sz_we (ctl_flags_sz_we),
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.ctl_flags_xy_we (ctl_flags_xy_we),
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.ctl_flags_hf_we (ctl_flags_hf_we),
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.ctl_flags_pf_we (ctl_flags_pf_we),
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.ctl_flags_nf_we (ctl_flags_nf_we),
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.ctl_flags_cf2_we (ctl_flags_cf2_we),
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.ctl_flags_hf_cpl (ctl_flags_hf_cpl),
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.ctl_flags_use_cf2 (ctl_flags_use_cf2),
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.ctl_flags_hf2_we (ctl_flags_hf2_we),
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.ctl_flags_nf_clr (ctl_flags_nf_clr),
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.ctl_alu_zero_16bit (ctl_alu_zero_16bit),
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.ctl_flags_cf2_sel_shift (ctl_flags_cf2_sel_shift),
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.ctl_flags_cf2_sel_daa (ctl_flags_cf2_sel_daa),
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.ctl_sw_4u (ctl_sw_4u),
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.ctl_reg_in_hi (ctl_reg_in_hi),
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.ctl_reg_in_lo (ctl_reg_in_lo),
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.ctl_reg_out_lo (ctl_reg_out_lo),
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.ctl_reg_out_hi (ctl_reg_out_hi),
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.ctl_reg_exx (ctl_reg_exx),
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.ctl_reg_ex_af (ctl_reg_ex_af),
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.ctl_reg_ex_de_hl (ctl_reg_ex_de_hl),
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.ctl_reg_use_sp (ctl_reg_use_sp),
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.ctl_reg_sel_pc (ctl_reg_sel_pc),
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.ctl_reg_sel_ir (ctl_reg_sel_ir),
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.ctl_reg_sel_wz (ctl_reg_sel_wz),
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.ctl_reg_gp_we (ctl_reg_gp_we),
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.ctl_reg_not_pc (ctl_reg_not_pc),
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.ctl_reg_sys_we_lo (ctl_reg_sys_we_lo),
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.ctl_reg_sys_we_hi (ctl_reg_sys_we_hi),
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.ctl_reg_sys_we (ctl_reg_sys_we),
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| 128 |
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.ctl_sw_4d (ctl_sw_4d),
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.ctl_reg_gp_hilo (ctl_reg_gp_hilo),
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.ctl_reg_gp_sel (ctl_reg_gp_sel),
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.ctl_reg_sys_hilo (ctl_reg_sys_hilo),
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| 132 |
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.ctl_inc_cy (ctl_inc_cy),
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| 133 |
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.ctl_inc_dec (ctl_inc_dec),
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| 134 |
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.ctl_al_we (ctl_al_we),
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.ctl_inc_limit6 (ctl_inc_limit6),
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| 136 |
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.ctl_bus_inc_oe (ctl_bus_inc_oe),
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.ctl_apin_mux (ctl_apin_mux),
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.ctl_apin_mux2 (ctl_apin_mux2),
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.ctl_bus_ff_oe (ctl_bus_ff_oe),
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.ctl_bus_zero_oe (ctl_bus_zero_oe),
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| 141 |
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.ctl_sw_1u (ctl_sw_1u),
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| 142 |
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.ctl_sw_1d (ctl_sw_1d),
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| 143 |
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.ctl_sw_2u (ctl_sw_2u),
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| 144 |
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.ctl_sw_2d (ctl_sw_2d),
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| 145 |
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.ctl_sw_mask543_en (ctl_sw_mask543_en),
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.ctl_bus_db_we (ctl_bus_db_we),
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| 147 |
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.ctl_bus_db_oe (ctl_bus_db_oe),
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| 148 |
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.nextM (nextM),
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| 149 |
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.setM1 (setM1),
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| 150 |
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.fFetch (fFetch),
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| 151 |
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.fMRead (fMRead),
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| 152 |
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.fMWrite (fMWrite),
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| 153 |
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.fIORead (fIORead),
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| 154 |
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.fIOWrite (fIOWrite),
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| 155 |
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.pla (pla),
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| 156 |
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.in_intr (in_intr),
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| 157 |
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.in_nmi (in_nmi),
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| 158 |
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.in_halt (in_halt),
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| 159 |
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.im1 (im1),
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| 160 |
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.im2 (im2),
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| 161 |
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.use_ixiy (use_ixiy),
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| 162 |
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.flags_cond_true (flags_cond_true),
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| 163 |
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.repeat_en (repeat_en),
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| 164 |
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.flags_zf (flags_zf),
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| 165 |
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.flags_nf (flags_nf),
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| 166 |
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.flags_sf (flags_sf),
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| 167 |
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.flags_cf (flags_cf),
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| 168 |
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.M1 (M1),
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| 169 |
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.M2 (M2),
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| 170 |
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.M3 (M3),
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| 171 |
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.M4 (M4),
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| 172 |
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.M5 (M5),
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| 173 |
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.T1 (T1),
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| 174 |
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.T2 (T2),
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| 175 |
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.T3 (T3),
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| 176 |
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.T4 (T4),
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| 177 |
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.T5 (T5),
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| 178 |
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.T6 (T6)
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| 179 |
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);
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| 181 |
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interrupts interrupts_(
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| 182 |
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.ctl_iff1_iff2 (ctl_iff1_iff2),
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| 183 |
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.nmi (nmi),
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| 184 |
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.setM1 (setM1),
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| 185 |
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.intr (intr),
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| 186 |
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.ctl_iffx_we (ctl_iffx_we),
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| 187 |
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.ctl_iffx_bit (ctl_iffx_bit),
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| 188 |
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.ctl_im_we (ctl_im_we),
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| 189 |
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.clk (clk),
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| 190 |
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.ctl_no_ints (ctl_no_ints),
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| 191 |
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.nreset (nreset),
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| 192 |
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.db (db0[4:3]),
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| 193 |
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.iff2 (iff2),
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| 194 |
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.im1 (im1),
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| 195 |
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.im2 (im2),
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| 196 |
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.in_nmi (in_nmi),
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| 197 |
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.in_intr (in_intr)
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| 198 |
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);
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| 199 |
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| 200 |
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ir ir_(
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| 201 |
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.ctl_ir_we (ctl_ir_we),
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| 202 |
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.clk (clk),
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| 203 |
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.nreset (nreset),
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| 204 |
13 |
gdevic |
.hold_clk_wait (hold_clk_wait),
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| 205 |
8 |
gdevic |
.db (db0[7:0]),
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| 206 |
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.opcode (opcode)
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| 207 |
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);
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| 208 |
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| 209 |
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pin_control pin_control_(
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| 210 |
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.fFetch (fFetch),
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| 211 |
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.fMRead (fMRead),
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| 212 |
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.fMWrite (fMWrite),
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| 213 |
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.fIORead (fIORead),
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| 214 |
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.fIOWrite (fIOWrite),
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| 215 |
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.T1 (T1),
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| 216 |
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.T2 (T2),
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| 217 |
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.T3 (T3),
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| 218 |
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.T4 (T4),
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| 219 |
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.bus_ab_pin_we (bus_ab_pin_we),
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| 220 |
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.bus_db_pin_oe (bus_db_pin_oe),
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| 221 |
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.bus_db_pin_re (bus_db_pin_re)
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| 222 |
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);
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| 223 |
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| 224 |
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pla_decode pla_decode_(
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| 225 |
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.prefix (prefix),
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| 226 |
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.opcode (opcode),
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| 227 |
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.pla (pla)
|
| 228 |
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);
|
| 229 |
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| 230 |
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resets resets_(
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| 231 |
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.reset_in (reset_in),
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| 232 |
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.clk (clk),
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| 233 |
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.M1 (M1),
|
| 234 |
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.T2 (T2),
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| 235 |
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.fpga_reset (fpga_reset),
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| 236 |
13 |
gdevic |
.hold_clk_wait (hold_clk_wait),
|
| 237 |
8 |
gdevic |
.clrpc (clrpc),
|
| 238 |
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.nreset (nreset)
|
| 239 |
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);
|
| 240 |
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|
|
| 241 |
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memory_ifc memory_ifc_(
|
| 242 |
|
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.clk (clk),
|
| 243 |
|
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.nM1_int (nM1_int),
|
| 244 |
|
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.ctl_mRead (ctl_mRead),
|
| 245 |
|
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.ctl_mWrite (ctl_mWrite),
|
| 246 |
|
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.in_intr (in_intr),
|
| 247 |
|
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.nreset (nreset),
|
| 248 |
|
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.fIORead (fIORead),
|
| 249 |
|
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.fIOWrite (fIOWrite),
|
| 250 |
|
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.setM1 (setM1),
|
| 251 |
|
|
.ctl_iorw (ctl_iorw),
|
| 252 |
|
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.timings_en (timings_en),
|
| 253 |
|
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.iorq_Tw (iorq_Tw),
|
| 254 |
|
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.hold_clk_wait (hold_clk_wait),
|
| 255 |
|
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.nM1_out (nM1_out),
|
| 256 |
|
|
.nRFSH_out (nRFSH_out),
|
| 257 |
|
|
.nMREQ_out (nMREQ_out),
|
| 258 |
|
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.nRD_out (nRD_out),
|
| 259 |
|
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.nWR_out (nWR_out),
|
| 260 |
|
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.nIORQ_out (nIORQ_out),
|
| 261 |
13 |
gdevic |
.latch_wait (latch_wait),
|
| 262 |
|
|
.wait_m1 (wait_m1)
|
| 263 |
8 |
gdevic |
);
|
| 264 |
|
|
|
| 265 |
|
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sequencer sequencer_(
|
| 266 |
|
|
.clk (clk),
|
| 267 |
|
|
.nextM (nextM),
|
| 268 |
|
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.setM1 (setM1),
|
| 269 |
|
|
.nreset (nreset),
|
| 270 |
|
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.hold_clk_iorq (hold_clk_iorq),
|
| 271 |
|
|
.hold_clk_wait (hold_clk_wait),
|
| 272 |
|
|
.hold_clk_busrq (hold_clk_busrq),
|
| 273 |
|
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.M1 (M1),
|
| 274 |
|
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.M2 (M2),
|
| 275 |
|
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.M3 (M3),
|
| 276 |
|
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.M4 (M4),
|
| 277 |
|
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.M5 (M5),
|
| 278 |
|
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.T1 (T1),
|
| 279 |
|
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.T2 (T2),
|
| 280 |
|
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.T3 (T3),
|
| 281 |
|
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.T4 (T4),
|
| 282 |
|
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.T5 (T5),
|
| 283 |
|
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.T6 (T6),
|
| 284 |
|
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.timings_en (timings_en)
|
| 285 |
|
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);
|
| 286 |
|
|
|
| 287 |
|
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alu_control alu_control_(
|
| 288 |
|
|
.alu_shift_db0 (alu_shift_db0),
|
| 289 |
|
|
.alu_shift_db7 (alu_shift_db7),
|
| 290 |
|
|
.ctl_shift_en (ctl_shift_en),
|
| 291 |
|
|
.alu_low_gt_9 (alu_low_gt_9),
|
| 292 |
|
|
.alu_high_gt_9 (alu_high_gt_9),
|
| 293 |
|
|
.alu_high_eq_9 (alu_high_eq_9),
|
| 294 |
|
|
.ctl_daa_oe (ctl_daa_oe),
|
| 295 |
|
|
.ctl_alu_op_low (ctl_alu_op_low),
|
| 296 |
|
|
.alu_parity_out (alu_parity_out),
|
| 297 |
|
|
.flags_cf (flags_cf),
|
| 298 |
|
|
.flags_zf (flags_zf),
|
| 299 |
|
|
.flags_pf (flags_pf),
|
| 300 |
|
|
.flags_sf (flags_sf),
|
| 301 |
|
|
.ctl_cond_short (ctl_cond_short),
|
| 302 |
|
|
.alu_vf_out (alu_vf_out),
|
| 303 |
|
|
.iff2 (iff2),
|
| 304 |
|
|
.ctl_alu_core_hf (ctl_alu_core_hf),
|
| 305 |
|
|
.ctl_eval_cond (ctl_eval_cond),
|
| 306 |
|
|
.repeat_en (repeat_en),
|
| 307 |
|
|
.flags_cf_latch (flags_cf_latch),
|
| 308 |
|
|
.flags_hf2 (flags_hf2),
|
| 309 |
|
|
.flags_hf (flags_hf),
|
| 310 |
|
|
.ctl_66_oe (ctl_66_oe),
|
| 311 |
|
|
.clk (clk),
|
| 312 |
|
|
.ctl_pf_sel (ctl_pf_sel),
|
| 313 |
|
|
.op543 ({pla[104],pla[103],pla[102]}),
|
| 314 |
|
|
.alu_shift_in (alu_shift_in),
|
| 315 |
|
|
.alu_shift_right (alu_shift_right),
|
| 316 |
|
|
.alu_shift_left (alu_shift_left),
|
| 317 |
|
|
.shift_cf_out (shift_cf_out),
|
| 318 |
|
|
.alu_parity_in (alu_parity_in),
|
| 319 |
|
|
.flags_cond_true (flags_cond_true),
|
| 320 |
|
|
.daa_cf_out (daa_cf_out),
|
| 321 |
|
|
.pf_sel (pf_sel),
|
| 322 |
|
|
.alu_op_low (alu_op_low),
|
| 323 |
|
|
.alu_core_cf_in (alu_core_cf_in),
|
| 324 |
|
|
.db (db1[7:0])
|
| 325 |
|
|
);
|
| 326 |
|
|
|
| 327 |
|
|
alu_select alu_select_(
|
| 328 |
|
|
.ctl_alu_oe (ctl_alu_oe),
|
| 329 |
|
|
.ctl_alu_shift_oe (ctl_alu_shift_oe),
|
| 330 |
|
|
.ctl_alu_op2_oe (ctl_alu_op2_oe),
|
| 331 |
|
|
.ctl_alu_res_oe (ctl_alu_res_oe),
|
| 332 |
|
|
.ctl_alu_op1_oe (ctl_alu_op1_oe),
|
| 333 |
|
|
.ctl_alu_bs_oe (ctl_alu_bs_oe),
|
| 334 |
|
|
.ctl_alu_op1_sel_bus (ctl_alu_op1_sel_bus),
|
| 335 |
|
|
.ctl_alu_op1_sel_low (ctl_alu_op1_sel_low),
|
| 336 |
|
|
.ctl_alu_op1_sel_zero (ctl_alu_op1_sel_zero),
|
| 337 |
|
|
.ctl_alu_op2_sel_zero (ctl_alu_op2_sel_zero),
|
| 338 |
|
|
.ctl_alu_op2_sel_bus (ctl_alu_op2_sel_bus),
|
| 339 |
|
|
.ctl_alu_op2_sel_lq (ctl_alu_op2_sel_lq),
|
| 340 |
|
|
.ctl_alu_sel_op2_neg (ctl_alu_sel_op2_neg),
|
| 341 |
|
|
.ctl_alu_sel_op2_high (ctl_alu_sel_op2_high),
|
| 342 |
|
|
.ctl_alu_core_R (ctl_alu_core_R),
|
| 343 |
|
|
.ctl_alu_core_V (ctl_alu_core_V),
|
| 344 |
|
|
.ctl_alu_core_S (ctl_alu_core_S),
|
| 345 |
|
|
.alu_oe (alu_oe),
|
| 346 |
|
|
.alu_shift_oe (alu_shift_oe),
|
| 347 |
|
|
.alu_op2_oe (alu_op2_oe),
|
| 348 |
|
|
.alu_res_oe (alu_res_oe),
|
| 349 |
|
|
.alu_op1_oe (alu_op1_oe),
|
| 350 |
|
|
.alu_bs_oe (alu_bs_oe),
|
| 351 |
|
|
.alu_op1_sel_bus (alu_op1_sel_bus),
|
| 352 |
|
|
.alu_op1_sel_low (alu_op1_sel_low),
|
| 353 |
|
|
.alu_op1_sel_zero (alu_op1_sel_zero),
|
| 354 |
|
|
.alu_op2_sel_zero (alu_op2_sel_zero),
|
| 355 |
|
|
.alu_op2_sel_bus (alu_op2_sel_bus),
|
| 356 |
|
|
.alu_op2_sel_lq (alu_op2_sel_lq),
|
| 357 |
|
|
.alu_sel_op2_neg (alu_sel_op2_neg),
|
| 358 |
|
|
.alu_sel_op2_high (alu_sel_op2_high),
|
| 359 |
|
|
.alu_core_R (alu_core_R),
|
| 360 |
|
|
.alu_core_V (alu_core_V),
|
| 361 |
|
|
.alu_core_S (alu_core_S)
|
| 362 |
|
|
);
|
| 363 |
|
|
|
| 364 |
|
|
alu_flags alu_flags_(
|
| 365 |
|
|
.ctl_flags_oe (ctl_flags_oe),
|
| 366 |
|
|
.ctl_flags_bus (ctl_flags_bus),
|
| 367 |
|
|
.ctl_flags_alu (ctl_flags_alu),
|
| 368 |
|
|
.alu_sf_out (alu_sf_out),
|
| 369 |
|
|
.alu_yf_out (alu_yf_out),
|
| 370 |
|
|
.alu_xf_out (alu_xf_out),
|
| 371 |
|
|
.ctl_flags_nf_set (ctl_flags_nf_set),
|
| 372 |
|
|
.alu_zero (alu_zero),
|
| 373 |
|
|
.shift_cf_out (shift_cf_out),
|
| 374 |
|
|
.alu_core_cf_out (alu_core_cf_out),
|
| 375 |
|
|
.daa_cf_out (daa_cf_out),
|
| 376 |
|
|
.ctl_flags_cf_set (ctl_flags_cf_set),
|
| 377 |
|
|
.ctl_flags_cf_cpl (ctl_flags_cf_cpl),
|
| 378 |
|
|
.pf_sel (pf_sel),
|
| 379 |
|
|
.ctl_flags_cf_we (ctl_flags_cf_we),
|
| 380 |
|
|
.ctl_flags_sz_we (ctl_flags_sz_we),
|
| 381 |
|
|
.ctl_flags_xy_we (ctl_flags_xy_we),
|
| 382 |
|
|
.ctl_flags_hf_we (ctl_flags_hf_we),
|
| 383 |
|
|
.ctl_flags_pf_we (ctl_flags_pf_we),
|
| 384 |
|
|
.ctl_flags_nf_we (ctl_flags_nf_we),
|
| 385 |
|
|
.ctl_flags_cf2_we (ctl_flags_cf2_we),
|
| 386 |
|
|
.ctl_flags_hf_cpl (ctl_flags_hf_cpl),
|
| 387 |
|
|
.ctl_flags_use_cf2 (ctl_flags_use_cf2),
|
| 388 |
|
|
.ctl_flags_hf2_we (ctl_flags_hf2_we),
|
| 389 |
|
|
.ctl_flags_nf_clr (ctl_flags_nf_clr),
|
| 390 |
|
|
.ctl_alu_zero_16bit (ctl_alu_zero_16bit),
|
| 391 |
|
|
.clk (clk),
|
| 392 |
|
|
.ctl_flags_cf2_sel_shift (ctl_flags_cf2_sel_shift),
|
| 393 |
|
|
.ctl_flags_cf2_sel_daa (ctl_flags_cf2_sel_daa),
|
| 394 |
|
|
.flags_sf (flags_sf),
|
| 395 |
|
|
.flags_zf (flags_zf),
|
| 396 |
|
|
.flags_hf (flags_hf),
|
| 397 |
|
|
.flags_pf (flags_pf),
|
| 398 |
|
|
.flags_cf (flags_cf),
|
| 399 |
|
|
.flags_nf (flags_nf),
|
| 400 |
|
|
.flags_cf_latch (flags_cf_latch),
|
| 401 |
|
|
.flags_hf2 (flags_hf2),
|
| 402 |
|
|
.db (db1[7:0])
|
| 403 |
|
|
);
|
| 404 |
|
|
|
| 405 |
|
|
alu alu_(
|
| 406 |
|
|
.alu_core_R (alu_core_R),
|
| 407 |
|
|
.alu_core_V (alu_core_V),
|
| 408 |
|
|
.alu_core_S (alu_core_S),
|
| 409 |
|
|
.alu_bs_oe (alu_bs_oe),
|
| 410 |
|
|
.alu_parity_in (alu_parity_in),
|
| 411 |
|
|
.alu_oe (alu_oe),
|
| 412 |
|
|
.alu_shift_oe (alu_shift_oe),
|
| 413 |
|
|
.alu_core_cf_in (alu_core_cf_in),
|
| 414 |
|
|
.alu_op2_oe (alu_op2_oe),
|
| 415 |
|
|
.alu_op1_oe (alu_op1_oe),
|
| 416 |
|
|
.alu_res_oe (alu_res_oe),
|
| 417 |
|
|
.alu_op1_sel_low (alu_op1_sel_low),
|
| 418 |
|
|
.alu_op1_sel_zero (alu_op1_sel_zero),
|
| 419 |
|
|
.alu_op1_sel_bus (alu_op1_sel_bus),
|
| 420 |
|
|
.alu_op2_sel_zero (alu_op2_sel_zero),
|
| 421 |
|
|
.alu_op2_sel_bus (alu_op2_sel_bus),
|
| 422 |
|
|
.alu_op2_sel_lq (alu_op2_sel_lq),
|
| 423 |
|
|
.alu_op_low (alu_op_low),
|
| 424 |
|
|
.alu_shift_in (alu_shift_in),
|
| 425 |
|
|
.alu_sel_op2_neg (alu_sel_op2_neg),
|
| 426 |
|
|
.alu_sel_op2_high (alu_sel_op2_high),
|
| 427 |
|
|
.alu_shift_left (alu_shift_left),
|
| 428 |
|
|
.alu_shift_right (alu_shift_right),
|
| 429 |
|
|
.clk (clk),
|
| 430 |
|
|
.bsel (db0[5:3]),
|
| 431 |
|
|
.alu_zero (alu_zero),
|
| 432 |
|
|
.alu_parity_out (alu_parity_out),
|
| 433 |
|
|
.alu_high_eq_9 (alu_high_eq_9),
|
| 434 |
|
|
.alu_high_gt_9 (alu_high_gt_9),
|
| 435 |
|
|
.alu_low_gt_9 (alu_low_gt_9),
|
| 436 |
|
|
.alu_shift_db0 (alu_shift_db0),
|
| 437 |
|
|
.alu_shift_db7 (alu_shift_db7),
|
| 438 |
|
|
.alu_core_cf_out (alu_core_cf_out),
|
| 439 |
|
|
.alu_sf_out (alu_sf_out),
|
| 440 |
|
|
.alu_yf_out (alu_yf_out),
|
| 441 |
|
|
.alu_xf_out (alu_xf_out),
|
| 442 |
|
|
.alu_vf_out (alu_vf_out),
|
| 443 |
|
|
.db (db2[7:0]),
|
| 444 |
|
|
.test_db_high (test_db_high),
|
| 445 |
|
|
.test_db_low (test_db_low)
|
| 446 |
|
|
);
|
| 447 |
|
|
|
| 448 |
|
|
reg_file reg_file_(
|
| 449 |
|
|
.reg_sel_sys_lo (reg_sel_sys_lo),
|
| 450 |
|
|
.reg_sel_gp_lo (reg_sel_gp_lo),
|
| 451 |
|
|
.reg_sel_sys_hi (reg_sel_sys_hi),
|
| 452 |
|
|
.reg_sel_gp_hi (reg_sel_gp_hi),
|
| 453 |
|
|
.reg_sel_ir (reg_sel_ir),
|
| 454 |
|
|
.reg_sel_pc (reg_sel_pc),
|
| 455 |
|
|
.ctl_sw_4u (ctl_sw_4u),
|
| 456 |
|
|
.reg_sel_wz (reg_sel_wz),
|
| 457 |
|
|
.reg_sel_sp (reg_sel_sp),
|
| 458 |
|
|
.reg_sel_iy (reg_sel_iy),
|
| 459 |
|
|
.reg_sel_ix (reg_sel_ix),
|
| 460 |
|
|
.reg_sel_hl2 (reg_sel_hl2),
|
| 461 |
|
|
.reg_sel_hl (reg_sel_hl),
|
| 462 |
|
|
.reg_sel_de2 (reg_sel_de2),
|
| 463 |
|
|
.reg_sel_de (reg_sel_de),
|
| 464 |
|
|
.reg_sel_bc2 (reg_sel_bc2),
|
| 465 |
|
|
.reg_sel_bc (reg_sel_bc),
|
| 466 |
|
|
.reg_sel_af2 (reg_sel_af2),
|
| 467 |
|
|
.reg_sel_af (reg_sel_af),
|
| 468 |
|
|
.reg_gp_we (reg_gp_we),
|
| 469 |
|
|
.reg_sys_we_lo (reg_sys_we_lo),
|
| 470 |
|
|
.reg_sys_we_hi (reg_sys_we_hi),
|
| 471 |
|
|
.ctl_reg_in_hi (ctl_reg_in_hi),
|
| 472 |
|
|
.ctl_reg_in_lo (ctl_reg_in_lo),
|
| 473 |
|
|
.ctl_reg_out_lo (ctl_reg_out_lo),
|
| 474 |
|
|
.ctl_reg_out_hi (ctl_reg_out_hi),
|
| 475 |
|
|
.clk (clk),
|
| 476 |
|
|
.reg_sw_4d_lo (reg_sw_4d_lo),
|
| 477 |
|
|
.reg_sw_4d_hi (reg_sw_4d_hi),
|
| 478 |
|
|
.db_hi_as (db_hi_as[7:0]),
|
| 479 |
|
|
.db_hi_ds (db2[7:0]),
|
| 480 |
|
|
.db_lo_as (db_lo_as[7:0]),
|
| 481 |
|
|
.db_lo_ds (db1[7:0])
|
| 482 |
|
|
);
|
| 483 |
|
|
|
| 484 |
|
|
reg_control reg_control_(
|
| 485 |
|
|
.ctl_reg_exx (ctl_reg_exx),
|
| 486 |
|
|
.ctl_reg_ex_af (ctl_reg_ex_af),
|
| 487 |
|
|
.ctl_reg_ex_de_hl (ctl_reg_ex_de_hl),
|
| 488 |
|
|
.ctl_reg_use_sp (ctl_reg_use_sp),
|
| 489 |
|
|
.nreset (nreset),
|
| 490 |
|
|
.ctl_reg_sel_pc (ctl_reg_sel_pc),
|
| 491 |
|
|
.ctl_reg_sel_ir (ctl_reg_sel_ir),
|
| 492 |
|
|
.ctl_reg_sel_wz (ctl_reg_sel_wz),
|
| 493 |
|
|
.ctl_reg_gp_we (ctl_reg_gp_we),
|
| 494 |
|
|
.ctl_reg_not_pc (ctl_reg_not_pc),
|
| 495 |
|
|
.use_ixiy (use_ixiy),
|
| 496 |
|
|
.use_ix (use_ix),
|
| 497 |
|
|
.ctl_reg_sys_we_lo (ctl_reg_sys_we_lo),
|
| 498 |
|
|
.ctl_reg_sys_we_hi (ctl_reg_sys_we_hi),
|
| 499 |
|
|
.ctl_reg_sys_we (ctl_reg_sys_we),
|
| 500 |
|
|
.clk (clk),
|
| 501 |
|
|
.ctl_sw_4d (ctl_sw_4d),
|
| 502 |
13 |
gdevic |
.hold_clk_wait (hold_clk_wait),
|
| 503 |
8 |
gdevic |
.ctl_reg_gp_hilo (ctl_reg_gp_hilo),
|
| 504 |
|
|
.ctl_reg_gp_sel (ctl_reg_gp_sel),
|
| 505 |
|
|
.ctl_reg_sys_hilo (ctl_reg_sys_hilo),
|
| 506 |
|
|
.reg_sel_bc (reg_sel_bc),
|
| 507 |
|
|
.reg_sel_bc2 (reg_sel_bc2),
|
| 508 |
|
|
.reg_sel_ix (reg_sel_ix),
|
| 509 |
|
|
.reg_sel_iy (reg_sel_iy),
|
| 510 |
|
|
.reg_sel_de (reg_sel_de),
|
| 511 |
|
|
.reg_sel_hl (reg_sel_hl),
|
| 512 |
|
|
.reg_sel_de2 (reg_sel_de2),
|
| 513 |
|
|
.reg_sel_hl2 (reg_sel_hl2),
|
| 514 |
|
|
.reg_sel_af (reg_sel_af),
|
| 515 |
|
|
.reg_sel_af2 (reg_sel_af2),
|
| 516 |
|
|
.reg_sel_wz (reg_sel_wz),
|
| 517 |
|
|
.reg_sel_pc (reg_sel_pc),
|
| 518 |
|
|
.reg_sel_ir (reg_sel_ir),
|
| 519 |
|
|
.reg_sel_sp (reg_sel_sp),
|
| 520 |
|
|
.reg_sel_gp_hi (reg_sel_gp_hi),
|
| 521 |
|
|
.reg_sel_gp_lo (reg_sel_gp_lo),
|
| 522 |
|
|
.reg_sel_sys_lo (reg_sel_sys_lo),
|
| 523 |
|
|
.reg_sel_sys_hi (reg_sel_sys_hi),
|
| 524 |
|
|
.reg_gp_we (reg_gp_we),
|
| 525 |
|
|
.reg_sys_we_lo (reg_sys_we_lo),
|
| 526 |
|
|
.reg_sys_we_hi (reg_sys_we_hi),
|
| 527 |
|
|
.reg_sw_4d_lo (reg_sw_4d_lo),
|
| 528 |
|
|
.reg_sw_4d_hi (reg_sw_4d_hi)
|
| 529 |
|
|
);
|
| 530 |
|
|
|
| 531 |
|
|
address_latch address_latch_(
|
| 532 |
|
|
.ctl_inc_cy (ctl_inc_cy),
|
| 533 |
|
|
.ctl_inc_dec (ctl_inc_dec),
|
| 534 |
|
|
.ctl_al_we (ctl_al_we),
|
| 535 |
|
|
.ctl_inc_limit6 (ctl_inc_limit6),
|
| 536 |
|
|
.ctl_bus_inc_oe (ctl_bus_inc_oe),
|
| 537 |
|
|
.clk (clk),
|
| 538 |
|
|
.ctl_apin_mux (ctl_apin_mux),
|
| 539 |
|
|
.ctl_apin_mux2 (ctl_apin_mux2),
|
| 540 |
|
|
.clrpc (clrpc),
|
| 541 |
|
|
.nreset (nreset),
|
| 542 |
|
|
.address_is_1 (address_is_1),
|
| 543 |
|
|
.abus ({db_hi_as[7:0], db_lo_as[7:0]}),
|
| 544 |
|
|
.address (address)
|
| 545 |
|
|
);
|
| 546 |
|
|
|
| 547 |
|
|
bus_control bus_control_(
|
| 548 |
|
|
.ctl_bus_ff_oe (ctl_bus_ff_oe),
|
| 549 |
|
|
.ctl_bus_zero_oe (ctl_bus_zero_oe),
|
| 550 |
|
|
.db (db0[7:0])
|
| 551 |
|
|
);
|
| 552 |
|
|
|
| 553 |
|
|
bus_switch bus_switch_(
|
| 554 |
|
|
.ctl_sw_1u (ctl_sw_1u),
|
| 555 |
|
|
.ctl_sw_1d (ctl_sw_1d),
|
| 556 |
|
|
.ctl_sw_2u (ctl_sw_2u),
|
| 557 |
|
|
.ctl_sw_2d (ctl_sw_2d),
|
| 558 |
|
|
.ctl_sw_mask543_en (ctl_sw_mask543_en),
|
| 559 |
|
|
.bus_sw_1u (bus_sw_1u),
|
| 560 |
|
|
.bus_sw_1d (bus_sw_1d),
|
| 561 |
|
|
.bus_sw_2u (bus_sw_2u),
|
| 562 |
|
|
.bus_sw_2d (bus_sw_2d),
|
| 563 |
|
|
.bus_sw_mask543_en (bus_sw_mask543_en)
|
| 564 |
|
|
);
|
