OpenCores
URL https://opencores.org/ocsvn/a-z80/a-z80/trunk

Subversion Repositories a-z80

[/] [a-z80/] [trunk/] [cpu/] [toplevel/] [coremodules.vh] - Blame information for rev 16

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 8 gdevic
// Automatically generated by gencoremodules.py
2
 
3
clk_delay clk_delay_(
4
    .clk (clk),
5
    .in_intr (in_intr),
6
    .nreset (nreset),
7
    .T1 (T1),
8
    .latch_wait (latch_wait),
9
    .mwait (mwait),
10
    .M1 (M1),
11
    .busrq (busrq),
12
    .setM1 (setM1),
13
    .hold_clk_iorq (hold_clk_iorq),
14
    .hold_clk_wait (hold_clk_wait),
15
    .iorq_Tw (iorq_Tw),
16
    .busack (busack),
17
    .pin_control_oe (pin_control_oe),
18 16 gdevic
    .hold_clk_busrq (hold_clk_busrq),
19
    .nhold_clk_wait (nhold_clk_wait)
20 8 gdevic
);
21
 
22
decode_state decode_state_(
23
    .ctl_state_iy_set (ctl_state_iy_set),
24
    .ctl_state_ixiy_clr (ctl_state_ixiy_clr),
25
    .ctl_state_ixiy_we (ctl_state_ixiy_we),
26
    .ctl_state_halt_set (ctl_state_halt_set),
27
    .ctl_state_tbl_ed_set (ctl_state_tbl_ed_set),
28
    .ctl_state_tbl_cb_set (ctl_state_tbl_cb_set),
29
    .ctl_state_alu (ctl_state_alu),
30
    .clk (clk),
31
    .address_is_1 (address_is_1),
32
    .ctl_repeat_we (ctl_repeat_we),
33
    .in_intr (in_intr),
34
    .in_nmi (in_nmi),
35
    .nreset (nreset),
36 13 gdevic
    .ctl_state_tbl_we (ctl_state_tbl_we),
37 16 gdevic
    .nhold_clk_wait (nhold_clk_wait),
38 8 gdevic
    .in_halt (in_halt),
39
    .table_cb (table_cb),
40
    .table_ed (table_ed),
41
    .table_xx (table_xx),
42
    .use_ix (use_ix),
43
    .use_ixiy (use_ixiy),
44
    .in_alu (in_alu),
45
    .repeat_en (repeat_en)
46
);
47
 
48
execute execute_(
49
    .ctl_state_iy_set (ctl_state_iy_set),
50
    .ctl_state_ixiy_clr (ctl_state_ixiy_clr),
51
    .ctl_state_ixiy_we (ctl_state_ixiy_we),
52
    .ctl_state_halt_set (ctl_state_halt_set),
53
    .ctl_state_tbl_ed_set (ctl_state_tbl_ed_set),
54
    .ctl_state_tbl_cb_set (ctl_state_tbl_cb_set),
55
    .ctl_state_alu (ctl_state_alu),
56
    .ctl_repeat_we (ctl_repeat_we),
57 13 gdevic
    .ctl_state_tbl_we (ctl_state_tbl_we),
58 8 gdevic
    .ctl_iff1_iff2 (ctl_iff1_iff2),
59
    .ctl_iffx_we (ctl_iffx_we),
60
    .ctl_iffx_bit (ctl_iffx_bit),
61
    .ctl_im_we (ctl_im_we),
62
    .ctl_no_ints (ctl_no_ints),
63
    .ctl_ir_we (ctl_ir_we),
64
    .ctl_mRead (ctl_mRead),
65
    .ctl_mWrite (ctl_mWrite),
66
    .ctl_iorw (ctl_iorw),
67
    .ctl_shift_en (ctl_shift_en),
68
    .ctl_daa_oe (ctl_daa_oe),
69
    .ctl_alu_op_low (ctl_alu_op_low),
70
    .ctl_cond_short (ctl_cond_short),
71
    .ctl_alu_core_hf (ctl_alu_core_hf),
72
    .ctl_eval_cond (ctl_eval_cond),
73
    .ctl_66_oe (ctl_66_oe),
74
    .ctl_pf_sel (ctl_pf_sel),
75
    .ctl_alu_oe (ctl_alu_oe),
76
    .ctl_alu_shift_oe (ctl_alu_shift_oe),
77
    .ctl_alu_op2_oe (ctl_alu_op2_oe),
78
    .ctl_alu_res_oe (ctl_alu_res_oe),
79
    .ctl_alu_op1_oe (ctl_alu_op1_oe),
80
    .ctl_alu_bs_oe (ctl_alu_bs_oe),
81
    .ctl_alu_op1_sel_bus (ctl_alu_op1_sel_bus),
82
    .ctl_alu_op1_sel_low (ctl_alu_op1_sel_low),
83
    .ctl_alu_op1_sel_zero (ctl_alu_op1_sel_zero),
84
    .ctl_alu_op2_sel_zero (ctl_alu_op2_sel_zero),
85
    .ctl_alu_op2_sel_bus (ctl_alu_op2_sel_bus),
86
    .ctl_alu_op2_sel_lq (ctl_alu_op2_sel_lq),
87
    .ctl_alu_sel_op2_neg (ctl_alu_sel_op2_neg),
88
    .ctl_alu_sel_op2_high (ctl_alu_sel_op2_high),
89
    .ctl_alu_core_R (ctl_alu_core_R),
90
    .ctl_alu_core_V (ctl_alu_core_V),
91
    .ctl_alu_core_S (ctl_alu_core_S),
92
    .ctl_flags_oe (ctl_flags_oe),
93
    .ctl_flags_bus (ctl_flags_bus),
94
    .ctl_flags_alu (ctl_flags_alu),
95
    .ctl_flags_nf_set (ctl_flags_nf_set),
96
    .ctl_flags_cf_set (ctl_flags_cf_set),
97
    .ctl_flags_cf_cpl (ctl_flags_cf_cpl),
98
    .ctl_flags_cf_we (ctl_flags_cf_we),
99
    .ctl_flags_sz_we (ctl_flags_sz_we),
100
    .ctl_flags_xy_we (ctl_flags_xy_we),
101
    .ctl_flags_hf_we (ctl_flags_hf_we),
102
    .ctl_flags_pf_we (ctl_flags_pf_we),
103
    .ctl_flags_nf_we (ctl_flags_nf_we),
104
    .ctl_flags_cf2_we (ctl_flags_cf2_we),
105
    .ctl_flags_hf_cpl (ctl_flags_hf_cpl),
106
    .ctl_flags_use_cf2 (ctl_flags_use_cf2),
107
    .ctl_flags_hf2_we (ctl_flags_hf2_we),
108
    .ctl_flags_nf_clr (ctl_flags_nf_clr),
109
    .ctl_alu_zero_16bit (ctl_alu_zero_16bit),
110
    .ctl_flags_cf2_sel_shift (ctl_flags_cf2_sel_shift),
111
    .ctl_flags_cf2_sel_daa (ctl_flags_cf2_sel_daa),
112
    .ctl_sw_4u (ctl_sw_4u),
113
    .ctl_reg_in_hi (ctl_reg_in_hi),
114
    .ctl_reg_in_lo (ctl_reg_in_lo),
115
    .ctl_reg_out_lo (ctl_reg_out_lo),
116
    .ctl_reg_out_hi (ctl_reg_out_hi),
117
    .ctl_reg_exx (ctl_reg_exx),
118
    .ctl_reg_ex_af (ctl_reg_ex_af),
119
    .ctl_reg_ex_de_hl (ctl_reg_ex_de_hl),
120
    .ctl_reg_use_sp (ctl_reg_use_sp),
121
    .ctl_reg_sel_pc (ctl_reg_sel_pc),
122
    .ctl_reg_sel_ir (ctl_reg_sel_ir),
123
    .ctl_reg_sel_wz (ctl_reg_sel_wz),
124
    .ctl_reg_gp_we (ctl_reg_gp_we),
125
    .ctl_reg_not_pc (ctl_reg_not_pc),
126
    .ctl_reg_sys_we_lo (ctl_reg_sys_we_lo),
127
    .ctl_reg_sys_we_hi (ctl_reg_sys_we_hi),
128
    .ctl_reg_sys_we (ctl_reg_sys_we),
129
    .ctl_sw_4d (ctl_sw_4d),
130
    .ctl_reg_gp_hilo (ctl_reg_gp_hilo),
131
    .ctl_reg_gp_sel (ctl_reg_gp_sel),
132
    .ctl_reg_sys_hilo (ctl_reg_sys_hilo),
133
    .ctl_inc_cy (ctl_inc_cy),
134
    .ctl_inc_dec (ctl_inc_dec),
135
    .ctl_al_we (ctl_al_we),
136
    .ctl_inc_limit6 (ctl_inc_limit6),
137
    .ctl_bus_inc_oe (ctl_bus_inc_oe),
138
    .ctl_apin_mux (ctl_apin_mux),
139
    .ctl_apin_mux2 (ctl_apin_mux2),
140
    .ctl_bus_ff_oe (ctl_bus_ff_oe),
141
    .ctl_bus_zero_oe (ctl_bus_zero_oe),
142
    .ctl_sw_1u (ctl_sw_1u),
143
    .ctl_sw_1d (ctl_sw_1d),
144
    .ctl_sw_2u (ctl_sw_2u),
145
    .ctl_sw_2d (ctl_sw_2d),
146
    .ctl_sw_mask543_en (ctl_sw_mask543_en),
147
    .ctl_bus_db_we (ctl_bus_db_we),
148
    .ctl_bus_db_oe (ctl_bus_db_oe),
149
    .nextM (nextM),
150
    .setM1 (setM1),
151
    .fFetch (fFetch),
152
    .fMRead (fMRead),
153
    .fMWrite (fMWrite),
154
    .fIORead (fIORead),
155
    .fIOWrite (fIOWrite),
156
    .pla (pla),
157
    .in_intr (in_intr),
158
    .in_nmi (in_nmi),
159
    .in_halt (in_halt),
160
    .im1 (im1),
161
    .im2 (im2),
162
    .use_ixiy (use_ixiy),
163
    .flags_cond_true (flags_cond_true),
164
    .repeat_en (repeat_en),
165
    .flags_zf (flags_zf),
166
    .flags_nf (flags_nf),
167
    .flags_sf (flags_sf),
168
    .flags_cf (flags_cf),
169
    .M1 (M1),
170
    .M2 (M2),
171
    .M3 (M3),
172
    .M4 (M4),
173
    .M5 (M5),
174
    .T1 (T1),
175
    .T2 (T2),
176
    .T3 (T3),
177
    .T4 (T4),
178
    .T5 (T5),
179
    .T6 (T6)
180
);
181
 
182
interrupts interrupts_(
183
    .ctl_iff1_iff2 (ctl_iff1_iff2),
184
    .nmi (nmi),
185
    .setM1 (setM1),
186
    .intr (intr),
187
    .ctl_iffx_we (ctl_iffx_we),
188
    .ctl_iffx_bit (ctl_iffx_bit),
189
    .ctl_im_we (ctl_im_we),
190
    .clk (clk),
191
    .ctl_no_ints (ctl_no_ints),
192
    .nreset (nreset),
193
    .db (db0[4:3]),
194
    .iff2 (iff2),
195
    .im1 (im1),
196
    .im2 (im2),
197
    .in_nmi (in_nmi),
198
    .in_intr (in_intr)
199
);
200
 
201
ir ir_(
202
    .ctl_ir_we (ctl_ir_we),
203
    .clk (clk),
204
    .nreset (nreset),
205 16 gdevic
    .nhold_clk_wait (nhold_clk_wait),
206 8 gdevic
    .db (db0[7:0]),
207
    .opcode (opcode)
208
);
209
 
210
pin_control pin_control_(
211
    .fFetch (fFetch),
212
    .fMRead (fMRead),
213
    .fMWrite (fMWrite),
214
    .fIORead (fIORead),
215
    .fIOWrite (fIOWrite),
216
    .T1 (T1),
217
    .T2 (T2),
218
    .T3 (T3),
219
    .T4 (T4),
220
    .bus_ab_pin_we (bus_ab_pin_we),
221
    .bus_db_pin_oe (bus_db_pin_oe),
222
    .bus_db_pin_re (bus_db_pin_re)
223
);
224
 
225
pla_decode pla_decode_(
226
    .prefix (prefix),
227
    .opcode (opcode),
228
    .pla (pla)
229
);
230
 
231
resets resets_(
232
    .reset_in (reset_in),
233
    .clk (clk),
234
    .M1 (M1),
235
    .T2 (T2),
236
    .fpga_reset (fpga_reset),
237 16 gdevic
    .nhold_clk_wait (nhold_clk_wait),
238 8 gdevic
    .clrpc (clrpc),
239
    .nreset (nreset)
240
);
241
 
242
memory_ifc memory_ifc_(
243
    .clk (clk),
244
    .nM1_int (nM1_int),
245
    .ctl_mRead (ctl_mRead),
246
    .ctl_mWrite (ctl_mWrite),
247
    .in_intr (in_intr),
248
    .nreset (nreset),
249
    .fIORead (fIORead),
250
    .fIOWrite (fIOWrite),
251
    .setM1 (setM1),
252
    .ctl_iorw (ctl_iorw),
253
    .timings_en (timings_en),
254
    .iorq_Tw (iorq_Tw),
255 16 gdevic
    .nhold_clk_wait (nhold_clk_wait),
256 8 gdevic
    .nM1_out (nM1_out),
257
    .nRFSH_out (nRFSH_out),
258
    .nMREQ_out (nMREQ_out),
259
    .nRD_out (nRD_out),
260
    .nWR_out (nWR_out),
261
    .nIORQ_out (nIORQ_out),
262 13 gdevic
    .latch_wait (latch_wait),
263
    .wait_m1 (wait_m1)
264 8 gdevic
);
265
 
266
sequencer sequencer_(
267
    .clk (clk),
268
    .nextM (nextM),
269
    .setM1 (setM1),
270
    .nreset (nreset),
271
    .hold_clk_iorq (hold_clk_iorq),
272
    .hold_clk_wait (hold_clk_wait),
273
    .hold_clk_busrq (hold_clk_busrq),
274
    .M1 (M1),
275
    .M2 (M2),
276
    .M3 (M3),
277
    .M4 (M4),
278
    .M5 (M5),
279
    .T1 (T1),
280
    .T2 (T2),
281
    .T3 (T3),
282
    .T4 (T4),
283
    .T5 (T5),
284
    .T6 (T6),
285
    .timings_en (timings_en)
286
);
287
 
288
alu_control alu_control_(
289
    .alu_shift_db0 (alu_shift_db0),
290
    .alu_shift_db7 (alu_shift_db7),
291
    .ctl_shift_en (ctl_shift_en),
292
    .alu_low_gt_9 (alu_low_gt_9),
293
    .alu_high_gt_9 (alu_high_gt_9),
294
    .alu_high_eq_9 (alu_high_eq_9),
295
    .ctl_daa_oe (ctl_daa_oe),
296
    .ctl_alu_op_low (ctl_alu_op_low),
297
    .alu_parity_out (alu_parity_out),
298
    .flags_cf (flags_cf),
299
    .flags_zf (flags_zf),
300
    .flags_pf (flags_pf),
301
    .flags_sf (flags_sf),
302
    .ctl_cond_short (ctl_cond_short),
303
    .alu_vf_out (alu_vf_out),
304
    .iff2 (iff2),
305
    .ctl_alu_core_hf (ctl_alu_core_hf),
306
    .ctl_eval_cond (ctl_eval_cond),
307
    .repeat_en (repeat_en),
308
    .flags_cf_latch (flags_cf_latch),
309
    .flags_hf2 (flags_hf2),
310
    .flags_hf (flags_hf),
311
    .ctl_66_oe (ctl_66_oe),
312
    .clk (clk),
313
    .ctl_pf_sel (ctl_pf_sel),
314
    .op543 ({pla[104],pla[103],pla[102]}),
315
    .alu_shift_in (alu_shift_in),
316
    .alu_shift_right (alu_shift_right),
317
    .alu_shift_left (alu_shift_left),
318
    .shift_cf_out (shift_cf_out),
319
    .alu_parity_in (alu_parity_in),
320
    .flags_cond_true (flags_cond_true),
321
    .daa_cf_out (daa_cf_out),
322
    .pf_sel (pf_sel),
323
    .alu_op_low (alu_op_low),
324
    .alu_core_cf_in (alu_core_cf_in),
325
    .db (db1[7:0])
326
);
327
 
328
alu_select alu_select_(
329
    .ctl_alu_oe (ctl_alu_oe),
330
    .ctl_alu_shift_oe (ctl_alu_shift_oe),
331
    .ctl_alu_op2_oe (ctl_alu_op2_oe),
332
    .ctl_alu_res_oe (ctl_alu_res_oe),
333
    .ctl_alu_op1_oe (ctl_alu_op1_oe),
334
    .ctl_alu_bs_oe (ctl_alu_bs_oe),
335
    .ctl_alu_op1_sel_bus (ctl_alu_op1_sel_bus),
336
    .ctl_alu_op1_sel_low (ctl_alu_op1_sel_low),
337
    .ctl_alu_op1_sel_zero (ctl_alu_op1_sel_zero),
338
    .ctl_alu_op2_sel_zero (ctl_alu_op2_sel_zero),
339
    .ctl_alu_op2_sel_bus (ctl_alu_op2_sel_bus),
340
    .ctl_alu_op2_sel_lq (ctl_alu_op2_sel_lq),
341
    .ctl_alu_sel_op2_neg (ctl_alu_sel_op2_neg),
342
    .ctl_alu_sel_op2_high (ctl_alu_sel_op2_high),
343
    .ctl_alu_core_R (ctl_alu_core_R),
344
    .ctl_alu_core_V (ctl_alu_core_V),
345
    .ctl_alu_core_S (ctl_alu_core_S),
346
    .alu_oe (alu_oe),
347
    .alu_shift_oe (alu_shift_oe),
348
    .alu_op2_oe (alu_op2_oe),
349
    .alu_res_oe (alu_res_oe),
350
    .alu_op1_oe (alu_op1_oe),
351
    .alu_bs_oe (alu_bs_oe),
352
    .alu_op1_sel_bus (alu_op1_sel_bus),
353
    .alu_op1_sel_low (alu_op1_sel_low),
354
    .alu_op1_sel_zero (alu_op1_sel_zero),
355
    .alu_op2_sel_zero (alu_op2_sel_zero),
356
    .alu_op2_sel_bus (alu_op2_sel_bus),
357
    .alu_op2_sel_lq (alu_op2_sel_lq),
358
    .alu_sel_op2_neg (alu_sel_op2_neg),
359
    .alu_sel_op2_high (alu_sel_op2_high),
360
    .alu_core_R (alu_core_R),
361
    .alu_core_V (alu_core_V),
362
    .alu_core_S (alu_core_S)
363
);
364
 
365
alu_flags alu_flags_(
366
    .ctl_flags_oe (ctl_flags_oe),
367
    .ctl_flags_bus (ctl_flags_bus),
368
    .ctl_flags_alu (ctl_flags_alu),
369
    .alu_sf_out (alu_sf_out),
370
    .alu_yf_out (alu_yf_out),
371
    .alu_xf_out (alu_xf_out),
372
    .ctl_flags_nf_set (ctl_flags_nf_set),
373
    .alu_zero (alu_zero),
374
    .shift_cf_out (shift_cf_out),
375
    .alu_core_cf_out (alu_core_cf_out),
376
    .daa_cf_out (daa_cf_out),
377
    .ctl_flags_cf_set (ctl_flags_cf_set),
378
    .ctl_flags_cf_cpl (ctl_flags_cf_cpl),
379
    .pf_sel (pf_sel),
380
    .ctl_flags_cf_we (ctl_flags_cf_we),
381
    .ctl_flags_sz_we (ctl_flags_sz_we),
382
    .ctl_flags_xy_we (ctl_flags_xy_we),
383
    .ctl_flags_hf_we (ctl_flags_hf_we),
384
    .ctl_flags_pf_we (ctl_flags_pf_we),
385
    .ctl_flags_nf_we (ctl_flags_nf_we),
386
    .ctl_flags_cf2_we (ctl_flags_cf2_we),
387
    .ctl_flags_hf_cpl (ctl_flags_hf_cpl),
388
    .ctl_flags_use_cf2 (ctl_flags_use_cf2),
389
    .ctl_flags_hf2_we (ctl_flags_hf2_we),
390
    .ctl_flags_nf_clr (ctl_flags_nf_clr),
391
    .ctl_alu_zero_16bit (ctl_alu_zero_16bit),
392
    .clk (clk),
393
    .ctl_flags_cf2_sel_shift (ctl_flags_cf2_sel_shift),
394
    .ctl_flags_cf2_sel_daa (ctl_flags_cf2_sel_daa),
395 16 gdevic
    .nhold_clk_wait (nhold_clk_wait),
396 8 gdevic
    .flags_sf (flags_sf),
397
    .flags_zf (flags_zf),
398
    .flags_hf (flags_hf),
399
    .flags_pf (flags_pf),
400
    .flags_cf (flags_cf),
401
    .flags_nf (flags_nf),
402
    .flags_cf_latch (flags_cf_latch),
403
    .flags_hf2 (flags_hf2),
404
    .db (db1[7:0])
405
);
406
 
407
alu alu_(
408
    .alu_core_R (alu_core_R),
409
    .alu_core_V (alu_core_V),
410
    .alu_core_S (alu_core_S),
411
    .alu_bs_oe (alu_bs_oe),
412
    .alu_parity_in (alu_parity_in),
413
    .alu_oe (alu_oe),
414
    .alu_shift_oe (alu_shift_oe),
415
    .alu_core_cf_in (alu_core_cf_in),
416
    .alu_op2_oe (alu_op2_oe),
417
    .alu_op1_oe (alu_op1_oe),
418
    .alu_res_oe (alu_res_oe),
419
    .alu_op1_sel_low (alu_op1_sel_low),
420
    .alu_op1_sel_zero (alu_op1_sel_zero),
421
    .alu_op1_sel_bus (alu_op1_sel_bus),
422
    .alu_op2_sel_zero (alu_op2_sel_zero),
423
    .alu_op2_sel_bus (alu_op2_sel_bus),
424
    .alu_op2_sel_lq (alu_op2_sel_lq),
425
    .alu_op_low (alu_op_low),
426
    .alu_shift_in (alu_shift_in),
427
    .alu_sel_op2_neg (alu_sel_op2_neg),
428
    .alu_sel_op2_high (alu_sel_op2_high),
429
    .alu_shift_left (alu_shift_left),
430
    .alu_shift_right (alu_shift_right),
431
    .clk (clk),
432
    .bsel (db0[5:3]),
433
    .alu_zero (alu_zero),
434
    .alu_parity_out (alu_parity_out),
435
    .alu_high_eq_9 (alu_high_eq_9),
436
    .alu_high_gt_9 (alu_high_gt_9),
437
    .alu_low_gt_9 (alu_low_gt_9),
438
    .alu_shift_db0 (alu_shift_db0),
439
    .alu_shift_db7 (alu_shift_db7),
440
    .alu_core_cf_out (alu_core_cf_out),
441
    .alu_sf_out (alu_sf_out),
442
    .alu_yf_out (alu_yf_out),
443
    .alu_xf_out (alu_xf_out),
444
    .alu_vf_out (alu_vf_out),
445
    .db (db2[7:0]),
446
    .test_db_high (test_db_high),
447
    .test_db_low (test_db_low)
448
);
449
 
450
reg_file reg_file_(
451
    .reg_sel_sys_lo (reg_sel_sys_lo),
452
    .reg_sel_gp_lo (reg_sel_gp_lo),
453
    .reg_sel_sys_hi (reg_sel_sys_hi),
454
    .reg_sel_gp_hi (reg_sel_gp_hi),
455
    .reg_sel_ir (reg_sel_ir),
456
    .reg_sel_pc (reg_sel_pc),
457
    .ctl_sw_4u (ctl_sw_4u),
458
    .reg_sel_wz (reg_sel_wz),
459
    .reg_sel_sp (reg_sel_sp),
460
    .reg_sel_iy (reg_sel_iy),
461
    .reg_sel_ix (reg_sel_ix),
462
    .reg_sel_hl2 (reg_sel_hl2),
463
    .reg_sel_hl (reg_sel_hl),
464
    .reg_sel_de2 (reg_sel_de2),
465
    .reg_sel_de (reg_sel_de),
466
    .reg_sel_bc2 (reg_sel_bc2),
467
    .reg_sel_bc (reg_sel_bc),
468
    .reg_sel_af2 (reg_sel_af2),
469
    .reg_sel_af (reg_sel_af),
470
    .reg_gp_we (reg_gp_we),
471
    .reg_sys_we_lo (reg_sys_we_lo),
472
    .reg_sys_we_hi (reg_sys_we_hi),
473
    .ctl_reg_in_hi (ctl_reg_in_hi),
474
    .ctl_reg_in_lo (ctl_reg_in_lo),
475
    .ctl_reg_out_lo (ctl_reg_out_lo),
476
    .ctl_reg_out_hi (ctl_reg_out_hi),
477
    .clk (clk),
478
    .reg_sw_4d_lo (reg_sw_4d_lo),
479
    .reg_sw_4d_hi (reg_sw_4d_hi),
480
    .db_hi_as (db_hi_as[7:0]),
481
    .db_hi_ds (db2[7:0]),
482
    .db_lo_as (db_lo_as[7:0]),
483
    .db_lo_ds (db1[7:0])
484
);
485
 
486
reg_control reg_control_(
487
    .ctl_reg_exx (ctl_reg_exx),
488
    .ctl_reg_ex_af (ctl_reg_ex_af),
489
    .ctl_reg_ex_de_hl (ctl_reg_ex_de_hl),
490
    .ctl_reg_use_sp (ctl_reg_use_sp),
491
    .nreset (nreset),
492
    .ctl_reg_sel_pc (ctl_reg_sel_pc),
493
    .ctl_reg_sel_ir (ctl_reg_sel_ir),
494
    .ctl_reg_sel_wz (ctl_reg_sel_wz),
495
    .ctl_reg_gp_we (ctl_reg_gp_we),
496
    .ctl_reg_not_pc (ctl_reg_not_pc),
497
    .use_ixiy (use_ixiy),
498
    .use_ix (use_ix),
499
    .ctl_reg_sys_we_lo (ctl_reg_sys_we_lo),
500
    .ctl_reg_sys_we_hi (ctl_reg_sys_we_hi),
501
    .ctl_reg_sys_we (ctl_reg_sys_we),
502
    .clk (clk),
503
    .ctl_sw_4d (ctl_sw_4d),
504 16 gdevic
    .nhold_clk_wait (nhold_clk_wait),
505 8 gdevic
    .ctl_reg_gp_hilo (ctl_reg_gp_hilo),
506
    .ctl_reg_gp_sel (ctl_reg_gp_sel),
507
    .ctl_reg_sys_hilo (ctl_reg_sys_hilo),
508
    .reg_sel_bc (reg_sel_bc),
509
    .reg_sel_bc2 (reg_sel_bc2),
510
    .reg_sel_ix (reg_sel_ix),
511
    .reg_sel_iy (reg_sel_iy),
512
    .reg_sel_de (reg_sel_de),
513
    .reg_sel_hl (reg_sel_hl),
514
    .reg_sel_de2 (reg_sel_de2),
515
    .reg_sel_hl2 (reg_sel_hl2),
516
    .reg_sel_af (reg_sel_af),
517
    .reg_sel_af2 (reg_sel_af2),
518
    .reg_sel_wz (reg_sel_wz),
519
    .reg_sel_pc (reg_sel_pc),
520
    .reg_sel_ir (reg_sel_ir),
521
    .reg_sel_sp (reg_sel_sp),
522
    .reg_sel_gp_hi (reg_sel_gp_hi),
523
    .reg_sel_gp_lo (reg_sel_gp_lo),
524
    .reg_sel_sys_lo (reg_sel_sys_lo),
525
    .reg_sel_sys_hi (reg_sel_sys_hi),
526
    .reg_gp_we (reg_gp_we),
527
    .reg_sys_we_lo (reg_sys_we_lo),
528
    .reg_sys_we_hi (reg_sys_we_hi),
529
    .reg_sw_4d_lo (reg_sw_4d_lo),
530
    .reg_sw_4d_hi (reg_sw_4d_hi)
531
);
532
 
533
address_latch address_latch_(
534
    .ctl_inc_cy (ctl_inc_cy),
535
    .ctl_inc_dec (ctl_inc_dec),
536
    .ctl_al_we (ctl_al_we),
537
    .ctl_inc_limit6 (ctl_inc_limit6),
538
    .ctl_bus_inc_oe (ctl_bus_inc_oe),
539
    .clk (clk),
540
    .ctl_apin_mux (ctl_apin_mux),
541
    .ctl_apin_mux2 (ctl_apin_mux2),
542
    .clrpc (clrpc),
543
    .nreset (nreset),
544
    .address_is_1 (address_is_1),
545
    .abus ({db_hi_as[7:0], db_lo_as[7:0]}),
546
    .address (address)
547
);
548
 
549
bus_control bus_control_(
550
    .ctl_bus_ff_oe (ctl_bus_ff_oe),
551
    .ctl_bus_zero_oe (ctl_bus_zero_oe),
552
    .db (db0[7:0])
553
);
554
 
555
bus_switch bus_switch_(
556
    .ctl_sw_1u (ctl_sw_1u),
557
    .ctl_sw_1d (ctl_sw_1d),
558
    .ctl_sw_2u (ctl_sw_2u),
559
    .ctl_sw_2d (ctl_sw_2d),
560
    .ctl_sw_mask543_en (ctl_sw_mask543_en),
561
    .bus_sw_1u (bus_sw_1u),
562
    .bus_sw_1d (bus_sw_1d),
563
    .bus_sw_2u (bus_sw_2u),
564
    .bus_sw_2d (bus_sw_2d),
565
    .bus_sw_mask543_en (bus_sw_mask543_en)
566
);

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.