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gdevic |
//============================================================================
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// Host design containing A-Z80 and a few peripherials
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//
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// This module defines a host board to be run on an FPGA.
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//
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// Copyright (C) 2014-2016 Goran Devic
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//============================================================================
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module host
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(
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input wire CLOCK_50,
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input wire KEY0, // KEY0 is reset
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input wire KEY1, // KEY1 generates a maskable interrupt (INT)
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input wire KEY2, // KEY2 generates a non-maskable interrupt (NMI)
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output wire UART_TXD,
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output wire [5:0] GPIO_0 // Test points
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);
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`default_nettype none
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// Export selected pins to the extension connector
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assign GPIO_0[0] = reset;
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assign GPIO_0[1] = locked;
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assign GPIO_0[2] = nM1;
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assign GPIO_0[3] = nMREQ;
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assign GPIO_0[4] = nRD;
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assign GPIO_0[5] = nWR;
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// Basic wires and the reset logic
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wire uart_tx;
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wire uart_busy;
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wire UartWE;
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wire reset;
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wire locked;
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assign reset = locked & KEY0;
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assign UART_TXD = uart_tx;
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// ----------------- CPU PINS -----------------
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wire nM1;
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wire nMREQ;
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wire nIORQ;
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wire nRD;
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wire nWR;
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wire nRFSH;
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wire nHALT;
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wire nBUSACK;
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wire nWAIT = 1;
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wire nBUSRQ = 1;
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wire nINT = KEY1;
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wire nNMI = KEY2;
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wire [15:0] A;
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wire [7:0] D;
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Instantiate PLL
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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wire pll_clk;
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pll pll_( .locked(locked), .inclk0(CLOCK_50), .c0(pll_clk) );
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Generate the CPU clock by dividing input clock by a factor of a power of 2
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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reg clk_cpu = 0; // Final CPU clock
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// Note: In order to test at 3.5 MHz, the PLL needs to be set to generate 14 MHz
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// and then this divider-by-4 brings the effective clock down to 3.5 MHz
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reg [0:0] counter = 0; // Clock divider counter
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always @(posedge pll_clk)
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begin
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if (counter=='0)
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clk_cpu <= ~clk_cpu;
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counter <= counter - 1'b1;
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end
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// ----------------- INTERNAL WIRES -----------------
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wire [7:0] RamData; // Data writer from the RAM module
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wire RamWE;
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assign RamWE = nIORQ==1 && nRD==1 && nWR==0;
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assign UartWE = nIORQ==0 && nRD==1 && nWR==0;
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// Memory map:
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// 0000 - 3FFF 16K RAM
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always_comb
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begin
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case ({nIORQ,nRD,nWR})
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3'b101: begin // Memory read
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casez (A[15:14])
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2'b00: D[7:0] = RamData;
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default:
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D[7:0] = 8'h76; // HALT
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endcase
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end
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3'b001: D[7:0] = {7'h0,uart_busy};
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// IO read *** Interrupts test ***
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// This value will be pushed on the data bus on an IORQ access which
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// means that:
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// In IM0: this is the opcode of an instruction to execute, set it to 0xFF
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// In IM2: this is a vector, set it to 0x80 (to correspond to a test program Hello World)
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3'b011: D[7:0] = 8'h80;
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default:
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D[7:0] = {8{1'bz}};
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endcase
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end
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Instantiate A-Z80 CPU module
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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z80_top_direct_n z80_( .*, .nRESET(reset), .CLK(clk_cpu) );
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Instantiate 16Kb of RAM memory
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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ram ram_( .address(A[13:0]), .clock(pll_clk), .data(D[7:0]), .wren(RamWE), .q(RamData[7:0]) );
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Instantiate UART module
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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uart #( .BAUD(115200), .IN_CLOCK(50000000) ) uart_(
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// Outputs
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.busy(uart_busy),
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.uart_tx(uart_tx),
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// Inputs
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.wr(UartWE),
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.data(D[7:0]),
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.clk(CLOCK_50),
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.reset(!reset)
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);
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endmodule
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