Subversion Repositories a-z80

# file : planAhead_rdn.tcl

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set device xc6slx16csg324-2

set projName clock

set design clock

set projDir [file dirname [info script]]

create_project $projName $projDir/results/$projName -part $device -force

set_property design_mode RTL [current_fileset -srcset]

set top_module clock_exdes

set_property top clock_exdes [get_property srcset [current_run]]

add_files -norecurse {../../../clock.v}

add_files -norecurse {../../example_design/clock_exdes.v}

import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/clock_exdes.xdc}

synth_design

opt_design

place_design

route_design

write_sdf -rename_top_module clock_exdes -file routed.sdf

write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module clock_exdes -file routed.v

report_timing -nworst 30 -path_type full -file routed.twr

report_drc -file report.drc

write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit