Subversion Repositories a-z80

#!/bin/sh

# file: simulate_vcs.sh

#

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# remove old files

rm -rf simv* csrc DVEfiles AN.DB

# compile all of the files

# Note that -sverilog is not strictly required- You can

#   remove the -sverilog if you change the type of the

#   localparam for the periods in the testbench file to

#   [63:0] from time

  vlogan -sverilog \

           clock_tb.v \

           ../../implement/results/routed.v

# prepare the simulation

vcs -sdf max:clock_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \

        +libext+.v -debug clock_tb.v ../../implement/results/routed.v

# run the simulation

./simv -ucli -i ucli_commands.key

# launch the viewer

#dve -vpd vcdplus.vpd -session vcs_session.tcl