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[/] [a-z80/] [trunk/] [host/] [basic_nexys3/] [ipcore_dir/] [ila.v] - Blame information for rev 8

Line No.	Rev	Author	Line
1	8	gdevic	`///////////////////////////////////////////////////////////////////////////////`
2			`// Copyright (c) 2016 Xilinx, Inc.`
3			`// All Rights Reserved`
4			`///////////////////////////////////////////////////////////////////////////////`
5			`// ____ ____`
6			`// / /\/ /`
7			`// /___/ \ / Vendor : Xilinx`
8			`// \ \ \/ Version : 14.7`
9			`// \ \ Application: Xilinx CORE Generator`
10			`// / / Filename : ila.v`
11			`// /___/ /\ Timestamp : Tue Feb 23 19:15:38 Central Standard Time 2016`
12			`// \ \ / \`
13			`// \___\/\___\`
14			`//`
15			`// Design Name: Verilog Synthesis Wrapper`
16			`///////////////////////////////////////////////////////////////////////////////`
17			`// This wrapper is used to integrate with Project Navigator and PlanAhead`
18
19			`timescale 1ns/1ps
20
21			`module ila(`
22			`CONTROL,`
23			`CLK,`
24			`DATA,`
25			`TRIG0) /* synthesis syn_black_box syn_noprune=1 */;`
26
27
28			`inout [35 : 0] CONTROL;`
29			`input CLK;`
30			`input [7 : 0] DATA;`
31			`input [7 : 0] TRIG0;`
32
33			`endmodule`