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[/] [a-z80/] [trunk/] [tools/] [dongle/] [dd.html] - Blame information for rev 3

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Line No.	Rev	Author	Line
1	3	gdevic	`<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01//EN">`
2			`<HTML><HEAD><TITLE>Z80 Instructions Timing</TITLE></HEAD><BODY>`
3			`<H1>Opcodes with DD prefix</H1>`
4			`DD 09 .. <A href="#09">ADD IX,BC</A><BR>`
5			`DD 19 .. <A href="#19">ADD IX,DE</A><BR>`
6			`DD 21 .. <A href="#21">LD IX,nn</A><BR>`
7			`DD 22 .. <A href="#22">LD (nn),IX</A><BR>`
8			`DD 23 .. <A href="#23">INC IX</A><BR>`
9			`DD 24 .. <A href="#24">INC IXh*</A><BR>`
10			`DD 25 .. <A href="#25">DEC IXh*</A><BR>`
11			`DD 26 .. <A href="#26">LD IXh,n*</A><BR>`
12			`DD 29 .. <A href="#29">ADD IX,IX</A><BR>`
13			`DD 2A .. <A href="#2A">LD IX,(nn)</A><BR>`
14			`DD 2B .. <A href="#2B">DEC IX</A><BR>`
15			`DD 2C .. <A href="#2C">INC IXl*</A><BR>`
16			`DD 2D .. <A href="#2D">DEC IXl*</A><BR>`
17			`DD 2E .. <A href="#2E">LD IXl,n*</A><BR>`
18			`DD 34 .. <A href="#34">INC (IX+d)</A><BR>`
19			`DD 35 .. <A href="#35">DEC (IX+d)</A><BR>`
20			`DD 36 .. <A href="#36">LD (IX+d),n</A><BR>`
21			`DD 39 .. <A href="#39">ADD IX,SP</A><BR>`
22			`DD 44 .. <A href="#44">LD B,IXh*</A><BR>`
23			`DD 45 .. <A href="#45">LD B,IXl*</A><BR>`
24			`DD 46 .. <A href="#46">LD B,(IX+d)</A><BR>`
25			`DD 4C .. <A href="#4C">LD C,IXh*</A><BR>`
26			`DD 4D .. <A href="#4D">LD C,IXl*</A><BR>`
27			`DD 4E .. <A href="#4E">LD C,(IX+d)</A><BR>`
28			`DD 54 .. <A href="#54">LD D,IXh*</A><BR>`
29			`DD 55 .. <A href="#55">LD D,IXl*</A><BR>`
30			`DD 56 .. <A href="#56">LD D,(IX+d)</A><BR>`
31			`DD 5C .. <A href="#5C">LD E,IXh*</A><BR>`
32			`DD 5D .. <A href="#5D">LD E,IXl*</A><BR>`
33			`DD 5E .. <A href="#5E">LD E,(IX+d)</A><BR>`
34			`DD 60 .. <A href="#60">LD IXh,B*</A><BR>`
35			`DD 61 .. <A href="#61">LD IXh,C*</A><BR>`
36			`DD 62 .. <A href="#62">LD IXh,D*</A><BR>`
37			`DD 63 .. <A href="#63">LD IXh,E*</A><BR>`
38			`DD 64 .. <A href="#64">LD IXh,IXh*</A><BR>`
39			`DD 65 .. <A href="#65">LD IXh,IXl*</A><BR>`
40			`DD 66 .. <A href="#66">LD H,(IX+d)</A><BR>`
41			`DD 67 .. <A href="#67">LD IXh,A*</A><BR>`
42			`DD 68 .. <A href="#68">LD IXl,B*</A><BR>`
43			`DD 69 .. <A href="#69">LD IXl,C*</A><BR>`
44			`DD 6A .. <A href="#6A">LD IXl,D*</A><BR>`
45			`DD 6B .. <A href="#6B">LD IXl,E*</A><BR>`
46			`DD 6C .. <A href="#6C">LD IXl,IXh*</A><BR>`
47			`DD 6D .. <A href="#6D">LD IXl,IXl*</A><BR>`
48			`DD 6E .. <A href="#6E">LD L,(IX+d)</A><BR>`
49			`DD 6F .. <A href="#6F">LD IXl,A*</A><BR>`
50			`DD 70 .. <A href="#70">LD (IX+d),B</A><BR>`
51			`DD 71 .. <A href="#71">LD (IX+d),C</A><BR>`
52			`DD 72 .. <A href="#72">LD (IX+d),D</A><BR>`
53			`DD 73 .. <A href="#73">LD (IX+d),E</A><BR>`
54			`DD 74 .. <A href="#74">LD (IX+d),H</A><BR>`
55			`DD 75 .. <A href="#75">LD (IX+d),L</A><BR>`
56			`DD 77 .. <A href="#77">LD (IX+d),A</A><BR>`
57			`DD 7C .. <A href="#7C">LD A,IXh*</A><BR>`
58			`DD 7D .. <A href="#7D">LD A,IXl*</A><BR>`
59			`DD 7E .. <A href="#7E">LD A,(IX+d)</A><BR>`
60			`DD 84 .. <A href="#84">ADD A,IXh*</A><BR>`
61			`DD 85 .. <A href="#85">ADD A,IXl*</A><BR>`
62			`DD 86 .. <A href="#86">ADD A,(IX+d)</A><BR>`
63			`DD 8C .. <A href="#8C">ADC A,IXh*</A><BR>`
64			`DD 8D .. <A href="#8D">ADC A,IXl*</A><BR>`
65			`DD 8E .. <A href="#8E">ADC A,(IX+d)</A><BR>`
66			`DD 94 .. <A href="#94">SUB IXh*</A><BR>`
67			`DD 95 .. <A href="#95">SUB IXl*</A><BR>`
68			`DD 96 .. <A href="#96">SUB (IX+d)</A><BR>`
69			`DD 9C .. <A href="#9C">SBC A,IXh*</A><BR>`
70			`DD 9D .. <A href="#9D">SBC A,IXl*</A><BR>`
71			`DD 9E .. <A href="#9E">SBC A,(IX+d)</A><BR>`
72			`DD A4 .. <A href="#A4">AND IXh*</A><BR>`
73			`DD A5 .. <A href="#A5">AND IXl*</A><BR>`
74			`DD A6 .. <A href="#A6">AND (IX+d)</A><BR>`
75			`DD AC .. <A href="#AC">XOR IXh*</A><BR>`
76			`DD AD .. <A href="#AD">XOR IXl*</A><BR>`
77			`DD AE .. <A href="#AE">XOR (IX+d)</A><BR>`
78			`DD B4 .. <A href="#B4">OR IXh*</A><BR>`
79			`DD B5 .. <A href="#B5">OR IXl*</A><BR>`
80			`DD B6 .. <A href="#B6">OR (IX+d)</A><BR>`
81			`DD BC .. <A href="#BC">CP IXh*</A><BR>`
82			`DD BD .. <A href="#BD">CP IXl*</A><BR>`
83			`DD BE .. <A href="#BE">CP (IX+d)</A><BR>`
84			`DD E1 .. <A href="#E1">POP IX</A><BR>`
85			`DD E3 .. <A href="#E3">EX (SP),IX</A><BR>`
86			`DD E5 .. <A href="#E5">PUSH IX</A><BR>`
87			`DD E9 .. <A href="#E9">JP (IX)</A><BR>`
88			`DD F9 .. <A href="#F9">LD SP,IX</A><BR>`
89			`<H1>Instructions Timing</H1>`
90			`<H3 id="09">Opcode: DD 09 => ADD IX,BC</H3>`
91			`<PRE>`
92			`-----------------------------------------------------------+`
93			`#001H T1 AB:000 DB:-- M1 \|`
94			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
95			`#003H T3 AB:000 DB:-- RFSH \|`
96			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
97			`-----------------------------------------------------------+`
98			`#005H T1 AB:001 DB:-- M1 \|`
99			`#006H T2 AB:001 DB:09 M1 MREQ RD \| Opcode read from 001 -> 09`
100			`#007H T3 AB:001 DB:-- RFSH \|`
101			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
102			`#009H T5 AB:001 DB:-- \|`
103			`#010H T6 AB:001 DB:-- \|`
104			`#011H T7 AB:001 DB:-- \|`
105			`#012H T8 AB:001 DB:-- \|`
106			`#013H T9 AB:001 DB:-- \|`
107			`#014H T10 AB:001 DB:-- \|`
108			`#015H T11 AB:001 DB:-- \|`
109			`-----------------------------------------------------------+`
110			`</PRE>`
111			`<H3 id="19">Opcode: DD 19 => ADD IX,DE</H3>`
112			`<PRE>`
113			`-----------------------------------------------------------+`
114			`#001H T1 AB:000 DB:-- M1 \|`
115			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
116			`#003H T3 AB:000 DB:-- RFSH \|`
117			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
118			`-----------------------------------------------------------+`
119			`#005H T1 AB:001 DB:-- M1 \|`
120			`#006H T2 AB:001 DB:19 M1 MREQ RD \| Opcode read from 001 -> 19`
121			`#007H T3 AB:001 DB:-- RFSH \|`
122			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
123			`#009H T5 AB:001 DB:-- \|`
124			`#010H T6 AB:001 DB:-- \|`
125			`#011H T7 AB:001 DB:-- \|`
126			`#012H T8 AB:001 DB:-- \|`
127			`#013H T9 AB:001 DB:-- \|`
128			`#014H T10 AB:001 DB:-- \|`
129			`#015H T11 AB:001 DB:-- \|`
130			`-----------------------------------------------------------+`
131			`</PRE>`
132			`<H3 id="21">Opcode: DD 21 n n => LD IX,nn</H3>`
133			`<PRE>`
134			`-----------------------------------------------------------+`
135			`#001H T1 AB:000 DB:-- M1 \|`
136			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
137			`#003H T3 AB:000 DB:-- RFSH \|`
138			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
139			`-----------------------------------------------------------+`
140			`#005H T1 AB:001 DB:-- M1 \|`
141			`#006H T2 AB:001 DB:21 M1 MREQ RD \| Opcode read from 001 -> 21`
142			`#007H T3 AB:001 DB:-- RFSH \|`
143			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
144			`#009H T5 AB:002 DB:-- \|`
145			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
146			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
147			`#012H T8 AB:003 DB:-- \|`
148			`#013H T9 AB:003 DB:02 MREQ RD \| Memory read from 003 -> 02`
149			`#014H T10 AB:003 DB:02 MREQ RD \| Memory read from 003 -> 02`
150			`-----------------------------------------------------------+`
151			`</PRE>`
152			`<H3 id="22">Opcode: DD 22 n n => LD (nn),IX</H3>`
153			`<PRE>`
154			`-----------------------------------------------------------+`
155			`#001H T1 AB:000 DB:-- M1 \|`
156			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
157			`#003H T3 AB:000 DB:-- RFSH \|`
158			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
159			`-----------------------------------------------------------+`
160			`#005H T1 AB:001 DB:-- M1 \|`
161			`#006H T2 AB:001 DB:22 M1 MREQ RD \| Opcode read from 001 -> 22`
162			`#007H T3 AB:001 DB:-- RFSH \|`
163			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
164			`#009H T5 AB:002 DB:-- \|`
165			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
166			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
167			`#012H T8 AB:003 DB:-- \|`
168			`#013H T9 AB:003 DB:02 MREQ RD \| Memory read from 003 -> 02`
169			`#014H T10 AB:003 DB:02 MREQ RD \| Memory read from 003 -> 02`
170			`#015H T11 AB:001 DB:-- \|`
171			`#016H T12 AB:001 DB:01 MREQ \|`
172			`#017H T13 AB:001 DB:01 MREQ WR \| Memory write to 001 <- 01`
173			`#018H T14 AB:002 DB:-- \|`
174			`#019H T15 AB:002 DB:02 MREQ \|`
175			`#020H T16 AB:002 DB:02 MREQ WR \| Memory write to 002 <- 02`
176			`-----------------------------------------------------------+`
177			`</PRE>`
178			`<H3 id="23">Opcode: DD 23 => INC IX</H3>`
179			`<PRE>`
180			`-----------------------------------------------------------+`
181			`#001H T1 AB:000 DB:-- M1 \|`
182			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
183			`#003H T3 AB:000 DB:-- RFSH \|`
184			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
185			`-----------------------------------------------------------+`
186			`#005H T1 AB:001 DB:-- M1 \|`
187			`#006H T2 AB:001 DB:23 M1 MREQ RD \| Opcode read from 001 -> 23`
188			`#007H T3 AB:001 DB:-- RFSH \|`
189			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
190			`#009H T5 AB:001 DB:-- \|`
191			`#010H T6 AB:001 DB:-- \|`
192			`-----------------------------------------------------------+`
193			`</PRE>`
194			`<H3 id="24">Opcode: DD 24 => INC IXh*</H3>`
195			`<PRE>`
196			`-----------------------------------------------------------+`
197			`#001H T1 AB:000 DB:-- M1 \|`
198			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
199			`#003H T3 AB:000 DB:-- RFSH \|`
200			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
201			`-----------------------------------------------------------+`
202			`#005H T1 AB:001 DB:-- M1 \|`
203			`#006H T2 AB:001 DB:24 M1 MREQ RD \| Opcode read from 001 -> 24`
204			`#007H T3 AB:001 DB:-- RFSH \|`
205			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
206			`-----------------------------------------------------------+`
207			`</PRE>`
208			`<H3 id="25">Opcode: DD 25 => DEC IXh*</H3>`
209			`<PRE>`
210			`-----------------------------------------------------------+`
211			`#001H T1 AB:000 DB:-- M1 \|`
212			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
213			`#003H T3 AB:000 DB:-- RFSH \|`
214			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
215			`-----------------------------------------------------------+`
216			`#005H T1 AB:001 DB:-- M1 \|`
217			`#006H T2 AB:001 DB:25 M1 MREQ RD \| Opcode read from 001 -> 25`
218			`#007H T3 AB:001 DB:-- RFSH \|`
219			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
220			`-----------------------------------------------------------+`
221			`</PRE>`
222			`<H3 id="26">Opcode: DD 26 n => LD IXh,n*</H3>`
223			`<PRE>`
224			`-----------------------------------------------------------+`
225			`#001H T1 AB:000 DB:-- M1 \|`
226			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
227			`#003H T3 AB:000 DB:-- RFSH \|`
228			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
229			`-----------------------------------------------------------+`
230			`#005H T1 AB:001 DB:-- M1 \|`
231			`#006H T2 AB:001 DB:26 M1 MREQ RD \| Opcode read from 001 -> 26`
232			`#007H T3 AB:001 DB:-- RFSH \|`
233			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
234			`#009H T5 AB:002 DB:-- \|`
235			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
236			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
237			`-----------------------------------------------------------+`
238			`</PRE>`
239			`<H3 id="29">Opcode: DD 29 => ADD IX,IX</H3>`
240			`<PRE>`
241			`-----------------------------------------------------------+`
242			`#001H T1 AB:000 DB:-- M1 \|`
243			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
244			`#003H T3 AB:000 DB:-- RFSH \|`
245			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
246			`-----------------------------------------------------------+`
247			`#005H T1 AB:001 DB:-- M1 \|`
248			`#006H T2 AB:001 DB:29 M1 MREQ RD \| Opcode read from 001 -> 29`
249			`#007H T3 AB:001 DB:-- RFSH \|`
250			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
251			`#009H T5 AB:001 DB:-- \|`
252			`#010H T6 AB:001 DB:-- \|`
253			`#011H T7 AB:001 DB:-- \|`
254			`#012H T8 AB:001 DB:-- \|`
255			`#013H T9 AB:001 DB:-- \|`
256			`#014H T10 AB:001 DB:-- \|`
257			`#015H T11 AB:001 DB:-- \|`
258			`-----------------------------------------------------------+`
259			`</PRE>`
260			`<H3 id="2A">Opcode: DD 2A n n => LD IX,(nn)</H3>`
261			`<PRE>`
262			`-----------------------------------------------------------+`
263			`#001H T1 AB:000 DB:-- M1 \|`
264			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
265			`#003H T3 AB:000 DB:-- RFSH \|`
266			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
267			`-----------------------------------------------------------+`
268			`#005H T1 AB:001 DB:-- M1 \|`
269			`#006H T2 AB:001 DB:2A M1 MREQ RD \| Opcode read from 001 -> 2A`
270			`#007H T3 AB:001 DB:-- RFSH \|`
271			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
272			`#009H T5 AB:002 DB:-- \|`
273			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
274			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
275			`#012H T8 AB:003 DB:-- \|`
276			`#013H T9 AB:003 DB:02 MREQ RD \| Memory read from 003 -> 02`
277			`#014H T10 AB:003 DB:02 MREQ RD \| Memory read from 003 -> 02`
278			`#015H T11 AB:001 DB:-- \|`
279			`#016H T12 AB:001 DB:2A MREQ RD \| Memory read from 001 -> 2A`
280			`#017H T13 AB:001 DB:2A MREQ RD \| Memory read from 001 -> 2A`
281			`#018H T14 AB:002 DB:-- \|`
282			`#019H T15 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
283			`#020H T16 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
284			`-----------------------------------------------------------+`
285			`</PRE>`
286			`<H3 id="2B">Opcode: DD 2B => DEC IX</H3>`
287			`<PRE>`
288			`-----------------------------------------------------------+`
289			`#001H T1 AB:000 DB:-- M1 \|`
290			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
291			`#003H T3 AB:000 DB:-- RFSH \|`
292			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
293			`-----------------------------------------------------------+`
294			`#005H T1 AB:001 DB:-- M1 \|`
295			`#006H T2 AB:001 DB:2B M1 MREQ RD \| Opcode read from 001 -> 2B`
296			`#007H T3 AB:001 DB:-- RFSH \|`
297			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
298			`#009H T5 AB:001 DB:-- \|`
299			`#010H T6 AB:001 DB:-- \|`
300			`-----------------------------------------------------------+`
301			`</PRE>`
302			`<H3 id="2C">Opcode: DD 2C => INC IXl*</H3>`
303			`<PRE>`
304			`-----------------------------------------------------------+`
305			`#001H T1 AB:000 DB:-- M1 \|`
306			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
307			`#003H T3 AB:000 DB:-- RFSH \|`
308			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
309			`-----------------------------------------------------------+`
310			`#005H T1 AB:001 DB:-- M1 \|`
311			`#006H T2 AB:001 DB:2C M1 MREQ RD \| Opcode read from 001 -> 2C`
312			`#007H T3 AB:001 DB:-- RFSH \|`
313			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
314			`-----------------------------------------------------------+`
315			`</PRE>`
316			`<H3 id="2D">Opcode: DD 2D => DEC IXl*</H3>`
317			`<PRE>`
318			`-----------------------------------------------------------+`
319			`#001H T1 AB:000 DB:-- M1 \|`
320			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
321			`#003H T3 AB:000 DB:-- RFSH \|`
322			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
323			`-----------------------------------------------------------+`
324			`#005H T1 AB:001 DB:-- M1 \|`
325			`#006H T2 AB:001 DB:2D M1 MREQ RD \| Opcode read from 001 -> 2D`
326			`#007H T3 AB:001 DB:-- RFSH \|`
327			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
328			`-----------------------------------------------------------+`
329			`</PRE>`
330			`<H3 id="2E">Opcode: DD 2E n => LD IXl,n*</H3>`
331			`<PRE>`
332			`-----------------------------------------------------------+`
333			`#001H T1 AB:000 DB:-- M1 \|`
334			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
335			`#003H T3 AB:000 DB:-- RFSH \|`
336			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
337			`-----------------------------------------------------------+`
338			`#005H T1 AB:001 DB:-- M1 \|`
339			`#006H T2 AB:001 DB:2E M1 MREQ RD \| Opcode read from 001 -> 2E`
340			`#007H T3 AB:001 DB:-- RFSH \|`
341			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
342			`#009H T5 AB:002 DB:-- \|`
343			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
344			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
345			`-----------------------------------------------------------+`
346			`</PRE>`
347			`<H3 id="34">Opcode: DD 34 d => INC (IX+d)</H3>`
348			`<PRE>`
349			`-----------------------------------------------------------+`
350			`#001H T1 AB:000 DB:-- M1 \|`
351			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
352			`#003H T3 AB:000 DB:-- RFSH \|`
353			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
354			`-----------------------------------------------------------+`
355			`#005H T1 AB:001 DB:-- M1 \|`
356			`#006H T2 AB:001 DB:34 M1 MREQ RD \| Opcode read from 001 -> 34`
357			`#007H T3 AB:001 DB:-- RFSH \|`
358			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
359			`#009H T5 AB:002 DB:-- \|`
360			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
361			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
362			`#012H T8 AB:002 DB:-- \|`
363			`#013H T9 AB:002 DB:-- \|`
364			`#014H T10 AB:002 DB:-- \|`
365			`#015H T11 AB:002 DB:-- \|`
366			`#016H T12 AB:002 DB:-- \|`
367			`#017H T13 AB:002 DB:-- \|`
368			`#018H T14 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
369			`#019H T15 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
370			`#020H T16 AB:002 DB:-- \|`
371			`#021H T17 AB:002 DB:-- \|`
372			`#022H T18 AB:002 DB:02 MREQ \|`
373			`#023H T19 AB:002 DB:02 MREQ WR \| Memory write to 002 <- 02`
374			`-----------------------------------------------------------+`
375			`</PRE>`
376			`<H3 id="35">Opcode: DD 35 d => DEC (IX+d)</H3>`
377			`<PRE>`
378			`-----------------------------------------------------------+`
379			`#001H T1 AB:000 DB:-- M1 \|`
380			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
381			`#003H T3 AB:000 DB:-- RFSH \|`
382			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
383			`-----------------------------------------------------------+`
384			`#005H T1 AB:001 DB:-- M1 \|`
385			`#006H T2 AB:001 DB:35 M1 MREQ RD \| Opcode read from 001 -> 35`
386			`#007H T3 AB:001 DB:-- RFSH \|`
387			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
388			`#009H T5 AB:002 DB:-- \|`
389			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
390			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
391			`#012H T8 AB:002 DB:-- \|`
392			`#013H T9 AB:002 DB:-- \|`
393			`#014H T10 AB:002 DB:-- \|`
394			`#015H T11 AB:002 DB:-- \|`
395			`#016H T12 AB:002 DB:-- \|`
396			`#017H T13 AB:002 DB:-- \|`
397			`#018H T14 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
398			`#019H T15 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
399			`#020H T16 AB:002 DB:-- \|`
400			`#021H T17 AB:002 DB:-- \|`
401			`#022H T18 AB:002 DB:00 MREQ \|`
402			`#023H T19 AB:002 DB:00 MREQ WR \| Memory write to 002 <- 00`
403			`-----------------------------------------------------------+`
404			`</PRE>`
405			`<H3 id="36">Opcode: DD 36 d n => LD (IX+d),n</H3>`
406			`<PRE>`
407			`-----------------------------------------------------------+`
408			`#001H T1 AB:000 DB:-- M1 \|`
409			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
410			`#003H T3 AB:000 DB:-- RFSH \|`
411			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
412			`-----------------------------------------------------------+`
413			`#005H T1 AB:001 DB:-- M1 \|`
414			`#006H T2 AB:001 DB:36 M1 MREQ RD \| Opcode read from 001 -> 36`
415			`#007H T3 AB:001 DB:-- RFSH \|`
416			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
417			`#009H T5 AB:002 DB:-- \|`
418			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
419			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
420			`#012H T8 AB:003 DB:-- \|`
421			`#013H T9 AB:003 DB:02 MREQ RD \| Memory read from 003 -> 02`
422			`#014H T10 AB:003 DB:02 MREQ RD \| Memory read from 003 -> 02`
423			`#015H T11 AB:003 DB:-- \|`
424			`#016H T12 AB:003 DB:-- \|`
425			`#017H T13 AB:002 DB:-- \|`
426			`#018H T14 AB:002 DB:02 MREQ \|`
427			`#019H T15 AB:002 DB:02 MREQ WR \| Memory write to 002 <- 02`
428			`-----------------------------------------------------------+`
429			`</PRE>`
430			`<H3 id="39">Opcode: DD 39 => ADD IX,SP</H3>`
431			`<PRE>`
432			`-----------------------------------------------------------+`
433			`#001H T1 AB:000 DB:-- M1 \|`
434			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
435			`#003H T3 AB:000 DB:-- RFSH \|`
436			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
437			`-----------------------------------------------------------+`
438			`#005H T1 AB:001 DB:-- M1 \|`
439			`#006H T2 AB:001 DB:39 M1 MREQ RD \| Opcode read from 001 -> 39`
440			`#007H T3 AB:001 DB:-- RFSH \|`
441			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
442			`#009H T5 AB:001 DB:-- \|`
443			`#010H T6 AB:001 DB:-- \|`
444			`#011H T7 AB:001 DB:-- \|`
445			`#012H T8 AB:001 DB:-- \|`
446			`#013H T9 AB:001 DB:-- \|`
447			`#014H T10 AB:001 DB:-- \|`
448			`#015H T11 AB:001 DB:-- \|`
449			`-----------------------------------------------------------+`
450			`</PRE>`
451			`<H3 id="44">Opcode: DD 44 => LD B,IXh*</H3>`
452			`<PRE>`
453			`-----------------------------------------------------------+`
454			`#001H T1 AB:000 DB:-- M1 \|`
455			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
456			`#003H T3 AB:000 DB:-- RFSH \|`
457			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
458			`-----------------------------------------------------------+`
459			`#005H T1 AB:001 DB:-- M1 \|`
460			`#006H T2 AB:001 DB:44 M1 MREQ RD \| Opcode read from 001 -> 44`
461			`#007H T3 AB:001 DB:-- RFSH \|`
462			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
463			`-----------------------------------------------------------+`
464			`</PRE>`
465			`<H3 id="45">Opcode: DD 45 => LD B,IXl*</H3>`
466			`<PRE>`
467			`-----------------------------------------------------------+`
468			`#001H T1 AB:000 DB:-- M1 \|`
469			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
470			`#003H T3 AB:000 DB:-- RFSH \|`
471			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
472			`-----------------------------------------------------------+`
473			`#005H T1 AB:001 DB:-- M1 \|`
474			`#006H T2 AB:001 DB:45 M1 MREQ RD \| Opcode read from 001 -> 45`
475			`#007H T3 AB:001 DB:-- RFSH \|`
476			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
477			`-----------------------------------------------------------+`
478			`</PRE>`
479			`<H3 id="46">Opcode: DD 46 d => LD B,(IX+d)</H3>`
480			`<PRE>`
481			`-----------------------------------------------------------+`
482			`#001H T1 AB:000 DB:-- M1 \|`
483			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
484			`#003H T3 AB:000 DB:-- RFSH \|`
485			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
486			`-----------------------------------------------------------+`
487			`#005H T1 AB:001 DB:-- M1 \|`
488			`#006H T2 AB:001 DB:46 M1 MREQ RD \| Opcode read from 001 -> 46`
489			`#007H T3 AB:001 DB:-- RFSH \|`
490			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
491			`#009H T5 AB:002 DB:-- \|`
492			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
493			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
494			`#012H T8 AB:002 DB:-- \|`
495			`#013H T9 AB:002 DB:-- \|`
496			`#014H T10 AB:002 DB:-- \|`
497			`#015H T11 AB:002 DB:-- \|`
498			`#016H T12 AB:002 DB:-- \|`
499			`#017H T13 AB:001 DB:-- \|`
500			`#018H T14 AB:001 DB:46 MREQ RD \| Memory read from 001 -> 46`
501			`#019H T15 AB:001 DB:46 MREQ RD \| Memory read from 001 -> 46`
502			`-----------------------------------------------------------+`
503			`</PRE>`
504			`<H3 id="4C">Opcode: DD 4C => LD C,IXh*</H3>`
505			`<PRE>`
506			`-----------------------------------------------------------+`
507			`#001H T1 AB:000 DB:-- M1 \|`
508			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
509			`#003H T3 AB:000 DB:-- RFSH \|`
510			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
511			`-----------------------------------------------------------+`
512			`#005H T1 AB:001 DB:-- M1 \|`
513			`#006H T2 AB:001 DB:4C M1 MREQ RD \| Opcode read from 001 -> 4C`
514			`#007H T3 AB:001 DB:-- RFSH \|`
515			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
516			`-----------------------------------------------------------+`
517			`</PRE>`
518			`<H3 id="4D">Opcode: DD 4D => LD C,IXl*</H3>`
519			`<PRE>`
520			`-----------------------------------------------------------+`
521			`#001H T1 AB:000 DB:-- M1 \|`
522			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
523			`#003H T3 AB:000 DB:-- RFSH \|`
524			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
525			`-----------------------------------------------------------+`
526			`#005H T1 AB:001 DB:-- M1 \|`
527			`#006H T2 AB:001 DB:4D M1 MREQ RD \| Opcode read from 001 -> 4D`
528			`#007H T3 AB:001 DB:-- RFSH \|`
529			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
530			`-----------------------------------------------------------+`
531			`</PRE>`
532			`<H3 id="4E">Opcode: DD 4E d => LD C,(IX+d)</H3>`
533			`<PRE>`
534			`-----------------------------------------------------------+`
535			`#001H T1 AB:000 DB:-- M1 \|`
536			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
537			`#003H T3 AB:000 DB:-- RFSH \|`
538			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
539			`-----------------------------------------------------------+`
540			`#005H T1 AB:001 DB:-- M1 \|`
541			`#006H T2 AB:001 DB:4E M1 MREQ RD \| Opcode read from 001 -> 4E`
542			`#007H T3 AB:001 DB:-- RFSH \|`
543			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
544			`#009H T5 AB:002 DB:-- \|`
545			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
546			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
547			`#012H T8 AB:002 DB:-- \|`
548			`#013H T9 AB:002 DB:-- \|`
549			`#014H T10 AB:002 DB:-- \|`
550			`#015H T11 AB:002 DB:-- \|`
551			`#016H T12 AB:002 DB:-- \|`
552			`#017H T13 AB:001 DB:-- \|`
553			`#018H T14 AB:001 DB:4E MREQ RD \| Memory read from 001 -> 4E`
554			`#019H T15 AB:001 DB:4E MREQ RD \| Memory read from 001 -> 4E`
555			`-----------------------------------------------------------+`
556			`</PRE>`
557			`<H3 id="54">Opcode: DD 54 => LD D,IXh*</H3>`
558			`<PRE>`
559			`-----------------------------------------------------------+`
560			`#001H T1 AB:000 DB:-- M1 \|`
561			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
562			`#003H T3 AB:000 DB:-- RFSH \|`
563			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
564			`-----------------------------------------------------------+`
565			`#005H T1 AB:001 DB:-- M1 \|`
566			`#006H T2 AB:001 DB:54 M1 MREQ RD \| Opcode read from 001 -> 54`
567			`#007H T3 AB:001 DB:-- RFSH \|`
568			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
569			`-----------------------------------------------------------+`
570			`</PRE>`
571			`<H3 id="55">Opcode: DD 55 => LD D,IXl*</H3>`
572			`<PRE>`
573			`-----------------------------------------------------------+`
574			`#001H T1 AB:000 DB:-- M1 \|`
575			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
576			`#003H T3 AB:000 DB:-- RFSH \|`
577			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
578			`-----------------------------------------------------------+`
579			`#005H T1 AB:001 DB:-- M1 \|`
580			`#006H T2 AB:001 DB:55 M1 MREQ RD \| Opcode read from 001 -> 55`
581			`#007H T3 AB:001 DB:-- RFSH \|`
582			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
583			`-----------------------------------------------------------+`
584			`</PRE>`
585			`<H3 id="56">Opcode: DD 56 d => LD D,(IX+d)</H3>`
586			`<PRE>`
587			`-----------------------------------------------------------+`
588			`#001H T1 AB:000 DB:-- M1 \|`
589			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
590			`#003H T3 AB:000 DB:-- RFSH \|`
591			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
592			`-----------------------------------------------------------+`
593			`#005H T1 AB:001 DB:-- M1 \|`
594			`#006H T2 AB:001 DB:56 M1 MREQ RD \| Opcode read from 001 -> 56`
595			`#007H T3 AB:001 DB:-- RFSH \|`
596			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
597			`#009H T5 AB:002 DB:-- \|`
598			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
599			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
600			`#012H T8 AB:002 DB:-- \|`
601			`#013H T9 AB:002 DB:-- \|`
602			`#014H T10 AB:002 DB:-- \|`
603			`#015H T11 AB:002 DB:-- \|`
604			`#016H T12 AB:002 DB:-- \|`
605			`#017H T13 AB:001 DB:-- \|`
606			`#018H T14 AB:001 DB:56 MREQ RD \| Memory read from 001 -> 56`
607			`#019H T15 AB:001 DB:56 MREQ RD \| Memory read from 001 -> 56`
608			`-----------------------------------------------------------+`
609			`</PRE>`
610			`<H3 id="5C">Opcode: DD 5C => LD E,IXh*</H3>`
611			`<PRE>`
612			`-----------------------------------------------------------+`
613			`#001H T1 AB:000 DB:-- M1 \|`
614			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
615			`#003H T3 AB:000 DB:-- RFSH \|`
616			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
617			`-----------------------------------------------------------+`
618			`#005H T1 AB:001 DB:-- M1 \|`
619			`#006H T2 AB:001 DB:5C M1 MREQ RD \| Opcode read from 001 -> 5C`
620			`#007H T3 AB:001 DB:-- RFSH \|`
621			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
622			`-----------------------------------------------------------+`
623			`</PRE>`
624			`<H3 id="5D">Opcode: DD 5D => LD E,IXl*</H3>`
625			`<PRE>`
626			`-----------------------------------------------------------+`
627			`#001H T1 AB:000 DB:-- M1 \|`
628			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
629			`#003H T3 AB:000 DB:-- RFSH \|`
630			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
631			`-----------------------------------------------------------+`
632			`#005H T1 AB:001 DB:-- M1 \|`
633			`#006H T2 AB:001 DB:5D M1 MREQ RD \| Opcode read from 001 -> 5D`
634			`#007H T3 AB:001 DB:-- RFSH \|`
635			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
636			`-----------------------------------------------------------+`
637			`</PRE>`
638			`<H3 id="5E">Opcode: DD 5E d => LD E,(IX+d)</H3>`
639			`<PRE>`
640			`-----------------------------------------------------------+`
641			`#001H T1 AB:000 DB:-- M1 \|`
642			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
643			`#003H T3 AB:000 DB:-- RFSH \|`
644			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
645			`-----------------------------------------------------------+`
646			`#005H T1 AB:001 DB:-- M1 \|`
647			`#006H T2 AB:001 DB:5E M1 MREQ RD \| Opcode read from 001 -> 5E`
648			`#007H T3 AB:001 DB:-- RFSH \|`
649			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
650			`#009H T5 AB:002 DB:-- \|`
651			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
652			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
653			`#012H T8 AB:002 DB:-- \|`
654			`#013H T9 AB:002 DB:-- \|`
655			`#014H T10 AB:002 DB:-- \|`
656			`#015H T11 AB:002 DB:-- \|`
657			`#016H T12 AB:002 DB:-- \|`
658			`#017H T13 AB:001 DB:-- \|`
659			`#018H T14 AB:001 DB:5E MREQ RD \| Memory read from 001 -> 5E`
660			`#019H T15 AB:001 DB:5E MREQ RD \| Memory read from 001 -> 5E`
661			`-----------------------------------------------------------+`
662			`</PRE>`
663			`<H3 id="60">Opcode: DD 60 => LD IXh,B*</H3>`
664			`<PRE>`
665			`-----------------------------------------------------------+`
666			`#001H T1 AB:000 DB:-- M1 \|`
667			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
668			`#003H T3 AB:000 DB:-- RFSH \|`
669			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
670			`-----------------------------------------------------------+`
671			`#005H T1 AB:001 DB:-- M1 \|`
672			`#006H T2 AB:001 DB:60 M1 MREQ RD \| Opcode read from 001 -> 60`
673			`#007H T3 AB:001 DB:-- RFSH \|`
674			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
675			`-----------------------------------------------------------+`
676			`</PRE>`
677			`<H3 id="61">Opcode: DD 61 => LD IXh,C*</H3>`
678			`<PRE>`
679			`-----------------------------------------------------------+`
680			`#001H T1 AB:000 DB:-- M1 \|`
681			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
682			`#003H T3 AB:000 DB:-- RFSH \|`
683			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
684			`-----------------------------------------------------------+`
685			`#005H T1 AB:001 DB:-- M1 \|`
686			`#006H T2 AB:001 DB:61 M1 MREQ RD \| Opcode read from 001 -> 61`
687			`#007H T3 AB:001 DB:-- RFSH \|`
688			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
689			`-----------------------------------------------------------+`
690			`</PRE>`
691			`<H3 id="62">Opcode: DD 62 => LD IXh,D*</H3>`
692			`<PRE>`
693			`-----------------------------------------------------------+`
694			`#001H T1 AB:000 DB:-- M1 \|`
695			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
696			`#003H T3 AB:000 DB:-- RFSH \|`
697			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
698			`-----------------------------------------------------------+`
699			`#005H T1 AB:001 DB:-- M1 \|`
700			`#006H T2 AB:001 DB:62 M1 MREQ RD \| Opcode read from 001 -> 62`
701			`#007H T3 AB:001 DB:-- RFSH \|`
702			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
703			`-----------------------------------------------------------+`
704			`</PRE>`
705			`<H3 id="63">Opcode: DD 63 => LD IXh,E*</H3>`
706			`<PRE>`
707			`-----------------------------------------------------------+`
708			`#001H T1 AB:000 DB:-- M1 \|`
709			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
710			`#003H T3 AB:000 DB:-- RFSH \|`
711			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
712			`-----------------------------------------------------------+`
713			`#005H T1 AB:001 DB:-- M1 \|`
714			`#006H T2 AB:001 DB:63 M1 MREQ RD \| Opcode read from 001 -> 63`
715			`#007H T3 AB:001 DB:-- RFSH \|`
716			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
717			`-----------------------------------------------------------+`
718			`</PRE>`
719			`<H3 id="64">Opcode: DD 64 => LD IXh,IXh*</H3>`
720			`<PRE>`
721			`-----------------------------------------------------------+`
722			`#001H T1 AB:000 DB:-- M1 \|`
723			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
724			`#003H T3 AB:000 DB:-- RFSH \|`
725			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
726			`-----------------------------------------------------------+`
727			`#005H T1 AB:001 DB:-- M1 \|`
728			`#006H T2 AB:001 DB:64 M1 MREQ RD \| Opcode read from 001 -> 64`
729			`#007H T3 AB:001 DB:-- RFSH \|`
730			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
731			`-----------------------------------------------------------+`
732			`</PRE>`
733			`<H3 id="65">Opcode: DD 65 => LD IXh,IXl*</H3>`
734			`<PRE>`
735			`-----------------------------------------------------------+`
736			`#001H T1 AB:000 DB:-- M1 \|`
737			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
738			`#003H T3 AB:000 DB:-- RFSH \|`
739			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
740			`-----------------------------------------------------------+`
741			`#005H T1 AB:001 DB:-- M1 \|`
742			`#006H T2 AB:001 DB:65 M1 MREQ RD \| Opcode read from 001 -> 65`
743			`#007H T3 AB:001 DB:-- RFSH \|`
744			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
745			`-----------------------------------------------------------+`
746			`</PRE>`
747			`<H3 id="66">Opcode: DD 66 d => LD H,(IX+d)</H3>`
748			`<PRE>`
749			`-----------------------------------------------------------+`
750			`#001H T1 AB:000 DB:-- M1 \|`
751			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
752			`#003H T3 AB:000 DB:-- RFSH \|`
753			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
754			`-----------------------------------------------------------+`
755			`#005H T1 AB:001 DB:-- M1 \|`
756			`#006H T2 AB:001 DB:66 M1 MREQ RD \| Opcode read from 001 -> 66`
757			`#007H T3 AB:001 DB:-- RFSH \|`
758			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
759			`#009H T5 AB:002 DB:-- \|`
760			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
761			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
762			`#012H T8 AB:002 DB:-- \|`
763			`#013H T9 AB:002 DB:-- \|`
764			`#014H T10 AB:002 DB:-- \|`
765			`#015H T11 AB:002 DB:-- \|`
766			`#016H T12 AB:002 DB:-- \|`
767			`#017H T13 AB:001 DB:-- \|`
768			`#018H T14 AB:001 DB:66 MREQ RD \| Memory read from 001 -> 66`
769			`#019H T15 AB:001 DB:66 MREQ RD \| Memory read from 001 -> 66`
770			`-----------------------------------------------------------+`
771			`</PRE>`
772			`<H3 id="67">Opcode: DD 67 => LD IXh,A*</H3>`
773			`<PRE>`
774			`-----------------------------------------------------------+`
775			`#001H T1 AB:000 DB:-- M1 \|`
776			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
777			`#003H T3 AB:000 DB:-- RFSH \|`
778			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
779			`-----------------------------------------------------------+`
780			`#005H T1 AB:001 DB:-- M1 \|`
781			`#006H T2 AB:001 DB:67 M1 MREQ RD \| Opcode read from 001 -> 67`
782			`#007H T3 AB:001 DB:-- RFSH \|`
783			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
784			`-----------------------------------------------------------+`
785			`</PRE>`
786			`<H3 id="68">Opcode: DD 68 => LD IXl,B*</H3>`
787			`<PRE>`
788			`-----------------------------------------------------------+`
789			`#001H T1 AB:000 DB:-- M1 \|`
790			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
791			`#003H T3 AB:000 DB:-- RFSH \|`
792			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
793			`-----------------------------------------------------------+`
794			`#005H T1 AB:001 DB:-- M1 \|`
795			`#006H T2 AB:001 DB:68 M1 MREQ RD \| Opcode read from 001 -> 68`
796			`#007H T3 AB:001 DB:-- RFSH \|`
797			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
798			`-----------------------------------------------------------+`
799			`</PRE>`
800			`<H3 id="69">Opcode: DD 69 => LD IXl,C*</H3>`
801			`<PRE>`
802			`-----------------------------------------------------------+`
803			`#001H T1 AB:000 DB:-- M1 \|`
804			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
805			`#003H T3 AB:000 DB:-- RFSH \|`
806			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
807			`-----------------------------------------------------------+`
808			`#005H T1 AB:001 DB:-- M1 \|`
809			`#006H T2 AB:001 DB:69 M1 MREQ RD \| Opcode read from 001 -> 69`
810			`#007H T3 AB:001 DB:-- RFSH \|`
811			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
812			`-----------------------------------------------------------+`
813			`</PRE>`
814			`<H3 id="6A">Opcode: DD 6A => LD IXl,D*</H3>`
815			`<PRE>`
816			`-----------------------------------------------------------+`
817			`#001H T1 AB:000 DB:-- M1 \|`
818			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
819			`#003H T3 AB:000 DB:-- RFSH \|`
820			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
821			`-----------------------------------------------------------+`
822			`#005H T1 AB:001 DB:-- M1 \|`
823			`#006H T2 AB:001 DB:6A M1 MREQ RD \| Opcode read from 001 -> 6A`
824			`#007H T3 AB:001 DB:-- RFSH \|`
825			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
826			`-----------------------------------------------------------+`
827			`</PRE>`
828			`<H3 id="6B">Opcode: DD 6B => LD IXl,E*</H3>`
829			`<PRE>`
830			`-----------------------------------------------------------+`
831			`#001H T1 AB:000 DB:-- M1 \|`
832			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
833			`#003H T3 AB:000 DB:-- RFSH \|`
834			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
835			`-----------------------------------------------------------+`
836			`#005H T1 AB:001 DB:-- M1 \|`
837			`#006H T2 AB:001 DB:6B M1 MREQ RD \| Opcode read from 001 -> 6B`
838			`#007H T3 AB:001 DB:-- RFSH \|`
839			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
840			`-----------------------------------------------------------+`
841			`</PRE>`
842			`<H3 id="6C">Opcode: DD 6C => LD IXl,IXh*</H3>`
843			`<PRE>`
844			`-----------------------------------------------------------+`
845			`#001H T1 AB:000 DB:-- M1 \|`
846			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
847			`#003H T3 AB:000 DB:-- RFSH \|`
848			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
849			`-----------------------------------------------------------+`
850			`#005H T1 AB:001 DB:-- M1 \|`
851			`#006H T2 AB:001 DB:6C M1 MREQ RD \| Opcode read from 001 -> 6C`
852			`#007H T3 AB:001 DB:-- RFSH \|`
853			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
854			`-----------------------------------------------------------+`
855			`</PRE>`
856			`<H3 id="6D">Opcode: DD 6D => LD IXl,IXl*</H3>`
857			`<PRE>`
858			`-----------------------------------------------------------+`
859			`#001H T1 AB:000 DB:-- M1 \|`
860			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
861			`#003H T3 AB:000 DB:-- RFSH \|`
862			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
863			`-----------------------------------------------------------+`
864			`#005H T1 AB:001 DB:-- M1 \|`
865			`#006H T2 AB:001 DB:6D M1 MREQ RD \| Opcode read from 001 -> 6D`
866			`#007H T3 AB:001 DB:-- RFSH \|`
867			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
868			`-----------------------------------------------------------+`
869			`</PRE>`
870			`<H3 id="6E">Opcode: DD 6E d => LD L,(IX+d)</H3>`
871			`<PRE>`
872			`-----------------------------------------------------------+`
873			`#001H T1 AB:000 DB:-- M1 \|`
874			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
875			`#003H T3 AB:000 DB:-- RFSH \|`
876			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
877			`-----------------------------------------------------------+`
878			`#005H T1 AB:001 DB:-- M1 \|`
879			`#006H T2 AB:001 DB:6E M1 MREQ RD \| Opcode read from 001 -> 6E`
880			`#007H T3 AB:001 DB:-- RFSH \|`
881			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
882			`#009H T5 AB:002 DB:-- \|`
883			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
884			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
885			`#012H T8 AB:002 DB:-- \|`
886			`#013H T9 AB:002 DB:-- \|`
887			`#014H T10 AB:002 DB:-- \|`
888			`#015H T11 AB:002 DB:-- \|`
889			`#016H T12 AB:002 DB:-- \|`
890			`#017H T13 AB:000 DB:-- \|`
891			`#018H T14 AB:000 DB:DD MREQ RD \| Memory read from 000 -> DD`
892			`#019H T15 AB:000 DB:DD MREQ RD \| Memory read from 000 -> DD`
893			`-----------------------------------------------------------+`
894			`</PRE>`
895			`<H3 id="6F">Opcode: DD 6F => LD IXl,A*</H3>`
896			`<PRE>`
897			`-----------------------------------------------------------+`
898			`#001H T1 AB:000 DB:-- M1 \|`
899			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
900			`#003H T3 AB:000 DB:-- RFSH \|`
901			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
902			`-----------------------------------------------------------+`
903			`#005H T1 AB:001 DB:-- M1 \|`
904			`#006H T2 AB:001 DB:6F M1 MREQ RD \| Opcode read from 001 -> 6F`
905			`#007H T3 AB:001 DB:-- RFSH \|`
906			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
907			`-----------------------------------------------------------+`
908			`</PRE>`
909			`<H3 id="70">Opcode: DD 70 d => LD (IX+d),B</H3>`
910			`<PRE>`
911			`-----------------------------------------------------------+`
912			`#001H T1 AB:000 DB:-- M1 \|`
913			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
914			`#003H T3 AB:000 DB:-- RFSH \|`
915			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
916			`-----------------------------------------------------------+`
917			`#005H T1 AB:001 DB:-- M1 \|`
918			`#006H T2 AB:001 DB:70 M1 MREQ RD \| Opcode read from 001 -> 70`
919			`#007H T3 AB:001 DB:-- RFSH \|`
920			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
921			`#009H T5 AB:002 DB:-- \|`
922			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
923			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
924			`#012H T8 AB:002 DB:-- \|`
925			`#013H T9 AB:002 DB:-- \|`
926			`#014H T10 AB:002 DB:-- \|`
927			`#015H T11 AB:002 DB:-- \|`
928			`#016H T12 AB:002 DB:-- \|`
929			`#017H T13 AB:000 DB:-- \|`
930			`#018H T14 AB:000 DB:46 MREQ \|`
931			`#019H T15 AB:000 DB:46 MREQ WR \| Memory write to 000 <- 46`
932			`-----------------------------------------------------------+`
933			`</PRE>`
934			`<H3 id="71">Opcode: DD 71 d => LD (IX+d),C</H3>`
935			`<PRE>`
936			`-----------------------------------------------------------+`
937			`#001H T1 AB:000 DB:-- M1 \|`
938			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
939			`#003H T3 AB:000 DB:-- RFSH \|`
940			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
941			`-----------------------------------------------------------+`
942			`#005H T1 AB:001 DB:-- M1 \|`
943			`#006H T2 AB:001 DB:71 M1 MREQ RD \| Opcode read from 001 -> 71`
944			`#007H T3 AB:001 DB:-- RFSH \|`
945			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
946			`#009H T5 AB:002 DB:-- \|`
947			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
948			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
949			`#012H T8 AB:002 DB:-- \|`
950			`#013H T9 AB:002 DB:-- \|`
951			`#014H T10 AB:002 DB:-- \|`
952			`#015H T11 AB:002 DB:-- \|`
953			`#016H T12 AB:002 DB:-- \|`
954			`#017H T13 AB:000 DB:-- \|`
955			`#018H T14 AB:000 DB:4E MREQ \|`
956			`#019H T15 AB:000 DB:4E MREQ WR \| Memory write to 000 <- 4E`
957			`-----------------------------------------------------------+`
958			`</PRE>`
959			`<H3 id="72">Opcode: DD 72 d => LD (IX+d),D</H3>`
960			`<PRE>`
961			`-----------------------------------------------------------+`
962			`#001H T1 AB:000 DB:-- M1 \|`
963			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
964			`#003H T3 AB:000 DB:-- RFSH \|`
965			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
966			`-----------------------------------------------------------+`
967			`#005H T1 AB:001 DB:-- M1 \|`
968			`#006H T2 AB:001 DB:72 M1 MREQ RD \| Opcode read from 001 -> 72`
969			`#007H T3 AB:001 DB:-- RFSH \|`
970			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
971			`#009H T5 AB:002 DB:-- \|`
972			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
973			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
974			`#012H T8 AB:002 DB:-- \|`
975			`#013H T9 AB:002 DB:-- \|`
976			`#014H T10 AB:002 DB:-- \|`
977			`#015H T11 AB:002 DB:-- \|`
978			`#016H T12 AB:002 DB:-- \|`
979			`#017H T13 AB:000 DB:-- \|`
980			`#018H T14 AB:000 DB:56 MREQ \|`
981			`#019H T15 AB:000 DB:56 MREQ WR \| Memory write to 000 <- 56`
982			`-----------------------------------------------------------+`
983			`</PRE>`
984			`<H3 id="73">Opcode: DD 73 d => LD (IX+d),E</H3>`
985			`<PRE>`
986			`-----------------------------------------------------------+`
987			`#001H T1 AB:000 DB:-- M1 \|`
988			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
989			`#003H T3 AB:000 DB:-- RFSH \|`
990			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
991			`-----------------------------------------------------------+`
992			`#005H T1 AB:001 DB:-- M1 \|`
993			`#006H T2 AB:001 DB:73 M1 MREQ RD \| Opcode read from 001 -> 73`
994			`#007H T3 AB:001 DB:-- RFSH \|`
995			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
996			`#009H T5 AB:002 DB:-- \|`
997			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
998			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
999			`#012H T8 AB:002 DB:-- \|`
1000			`#013H T9 AB:002 DB:-- \|`
1001			`#014H T10 AB:002 DB:-- \|`
1002			`#015H T11 AB:002 DB:-- \|`
1003			`#016H T12 AB:002 DB:-- \|`
1004			`#017H T13 AB:000 DB:-- \|`
1005			`#018H T14 AB:000 DB:5E MREQ \|`
1006			`#019H T15 AB:000 DB:5E MREQ WR \| Memory write to 000 <- 5E`
1007			`-----------------------------------------------------------+`
1008			`</PRE>`
1009			`<H3 id="74">Opcode: DD 74 d => LD (IX+d),H</H3>`
1010			`<PRE>`
1011			`-----------------------------------------------------------+`
1012			`#001H T1 AB:000 DB:-- M1 \|`
1013			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1014			`#003H T3 AB:000 DB:-- RFSH \|`
1015			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1016			`-----------------------------------------------------------+`
1017			`#005H T1 AB:001 DB:-- M1 \|`
1018			`#006H T2 AB:001 DB:74 M1 MREQ RD \| Opcode read from 001 -> 74`
1019			`#007H T3 AB:001 DB:-- RFSH \|`
1020			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1021			`#009H T5 AB:002 DB:-- \|`
1022			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
1023			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
1024			`#012H T8 AB:002 DB:-- \|`
1025			`#013H T9 AB:002 DB:-- \|`
1026			`#014H T10 AB:002 DB:-- \|`
1027			`#015H T11 AB:002 DB:-- \|`
1028			`#016H T12 AB:002 DB:-- \|`
1029			`#017H T13 AB:000 DB:-- \|`
1030			`#018H T14 AB:000 DB:66 MREQ \|`
1031			`#019H T15 AB:000 DB:66 MREQ WR \| Memory write to 000 <- 66`
1032			`-----------------------------------------------------------+`
1033			`</PRE>`
1034			`<H3 id="75">Opcode: DD 75 d => LD (IX+d),L</H3>`
1035			`<PRE>`
1036			`-----------------------------------------------------------+`
1037			`#001H T1 AB:000 DB:-- M1 \|`
1038			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1039			`#003H T3 AB:000 DB:-- RFSH \|`
1040			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1041			`-----------------------------------------------------------+`
1042			`#005H T1 AB:001 DB:-- M1 \|`
1043			`#006H T2 AB:001 DB:75 M1 MREQ RD \| Opcode read from 001 -> 75`
1044			`#007H T3 AB:001 DB:-- RFSH \|`
1045			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1046			`#009H T5 AB:002 DB:-- \|`
1047			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
1048			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
1049			`#012H T8 AB:002 DB:-- \|`
1050			`#013H T9 AB:002 DB:-- \|`
1051			`#014H T10 AB:002 DB:-- \|`
1052			`#015H T11 AB:002 DB:-- \|`
1053			`#016H T12 AB:002 DB:-- \|`
1054			`#017H T13 AB:000 DB:-- \|`
1055			`#018H T14 AB:000 DB:DD MREQ \|`
1056			`#019H T15 AB:000 DB:DD MREQ WR \| Memory write to 000 <- DD`
1057			`-----------------------------------------------------------+`
1058			`</PRE>`
1059			`<H3 id="77">Opcode: DD 77 d => LD (IX+d),A</H3>`
1060			`<PRE>`
1061			`-----------------------------------------------------------+`
1062			`#001H T1 AB:000 DB:-- M1 \|`
1063			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1064			`#003H T3 AB:000 DB:-- RFSH \|`
1065			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1066			`-----------------------------------------------------------+`
1067			`#005H T1 AB:001 DB:-- M1 \|`
1068			`#006H T2 AB:001 DB:77 M1 MREQ RD \| Opcode read from 001 -> 77`
1069			`#007H T3 AB:001 DB:-- RFSH \|`
1070			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1071			`#009H T5 AB:002 DB:-- \|`
1072			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
1073			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
1074			`#012H T8 AB:002 DB:-- \|`
1075			`#013H T9 AB:002 DB:-- \|`
1076			`#014H T10 AB:002 DB:-- \|`
1077			`#015H T11 AB:002 DB:-- \|`
1078			`#016H T12 AB:002 DB:-- \|`
1079			`#017H T13 AB:000 DB:-- \|`
1080			`#018H T14 AB:000 DB:FF MREQ \|`
1081			`#019H T15 AB:000 DB:FF MREQ WR \| Memory write to 000 <- FF`
1082			`-----------------------------------------------------------+`
1083			`</PRE>`
1084			`<H3 id="7C">Opcode: DD 7C => LD A,IXh*</H3>`
1085			`<PRE>`
1086			`-----------------------------------------------------------+`
1087			`#001H T1 AB:000 DB:-- M1 \|`
1088			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1089			`#003H T3 AB:000 DB:-- RFSH \|`
1090			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1091			`-----------------------------------------------------------+`
1092			`#005H T1 AB:001 DB:-- M1 \|`
1093			`#006H T2 AB:001 DB:7C M1 MREQ RD \| Opcode read from 001 -> 7C`
1094			`#007H T3 AB:001 DB:-- RFSH \|`
1095			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1096			`-----------------------------------------------------------+`
1097			`</PRE>`
1098			`<H3 id="7D">Opcode: DD 7D => LD A,IXl*</H3>`
1099			`<PRE>`
1100			`-----------------------------------------------------------+`
1101			`#001H T1 AB:000 DB:-- M1 \|`
1102			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1103			`#003H T3 AB:000 DB:-- RFSH \|`
1104			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1105			`-----------------------------------------------------------+`
1106			`#005H T1 AB:001 DB:-- M1 \|`
1107			`#006H T2 AB:001 DB:7D M1 MREQ RD \| Opcode read from 001 -> 7D`
1108			`#007H T3 AB:001 DB:-- RFSH \|`
1109			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1110			`-----------------------------------------------------------+`
1111			`</PRE>`
1112			`<H3 id="7E">Opcode: DD 7E d => LD A,(IX+d)</H3>`
1113			`<PRE>`
1114			`-----------------------------------------------------------+`
1115			`#001H T1 AB:000 DB:-- M1 \|`
1116			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1117			`#003H T3 AB:000 DB:-- RFSH \|`
1118			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1119			`-----------------------------------------------------------+`
1120			`#005H T1 AB:001 DB:-- M1 \|`
1121			`#006H T2 AB:001 DB:7E M1 MREQ RD \| Opcode read from 001 -> 7E`
1122			`#007H T3 AB:001 DB:-- RFSH \|`
1123			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1124			`#009H T5 AB:002 DB:-- \|`
1125			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
1126			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
1127			`#012H T8 AB:002 DB:-- \|`
1128			`#013H T9 AB:002 DB:-- \|`
1129			`#014H T10 AB:002 DB:-- \|`
1130			`#015H T11 AB:002 DB:-- \|`
1131			`#016H T12 AB:002 DB:-- \|`
1132			`#017H T13 AB:000 DB:-- \|`
1133			`#018H T14 AB:000 DB:DD MREQ RD \| Memory read from 000 -> DD`
1134			`#019H T15 AB:000 DB:DD MREQ RD \| Memory read from 000 -> DD`
1135			`-----------------------------------------------------------+`
1136			`</PRE>`
1137			`<H3 id="84">Opcode: DD 84 => ADD A,IXh*</H3>`
1138			`<PRE>`
1139			`-----------------------------------------------------------+`
1140			`#001H T1 AB:000 DB:-- M1 \|`
1141			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1142			`#003H T3 AB:000 DB:-- RFSH \|`
1143			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1144			`-----------------------------------------------------------+`
1145			`#005H T1 AB:001 DB:-- M1 \|`
1146			`#006H T2 AB:001 DB:84 M1 MREQ RD \| Opcode read from 001 -> 84`
1147			`#007H T3 AB:001 DB:-- RFSH \|`
1148			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1149			`-----------------------------------------------------------+`
1150			`</PRE>`
1151			`<H3 id="85">Opcode: DD 85 => ADD A,IXl*</H3>`
1152			`<PRE>`
1153			`-----------------------------------------------------------+`
1154			`#001H T1 AB:000 DB:-- M1 \|`
1155			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1156			`#003H T3 AB:000 DB:-- RFSH \|`
1157			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1158			`-----------------------------------------------------------+`
1159			`#005H T1 AB:001 DB:-- M1 \|`
1160			`#006H T2 AB:001 DB:85 M1 MREQ RD \| Opcode read from 001 -> 85`
1161			`#007H T3 AB:001 DB:-- RFSH \|`
1162			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1163			`-----------------------------------------------------------+`
1164			`</PRE>`
1165			`<H3 id="86">Opcode: DD 86 d => ADD A,(IX+d)</H3>`
1166			`<PRE>`
1167			`-----------------------------------------------------------+`
1168			`#001H T1 AB:000 DB:-- M1 \|`
1169			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1170			`#003H T3 AB:000 DB:-- RFSH \|`
1171			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1172			`-----------------------------------------------------------+`
1173			`#005H T1 AB:001 DB:-- M1 \|`
1174			`#006H T2 AB:001 DB:86 M1 MREQ RD \| Opcode read from 001 -> 86`
1175			`#007H T3 AB:001 DB:-- RFSH \|`
1176			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1177			`#009H T5 AB:002 DB:-- \|`
1178			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
1179			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
1180			`#012H T8 AB:002 DB:-- \|`
1181			`#013H T9 AB:002 DB:-- \|`
1182			`#014H T10 AB:002 DB:-- \|`
1183			`#015H T11 AB:002 DB:-- \|`
1184			`#016H T12 AB:002 DB:-- \|`
1185			`#017H T13 AB:000 DB:-- \|`
1186			`#018H T14 AB:000 DB:DD MREQ RD \| Memory read from 000 -> DD`
1187			`#019H T15 AB:000 DB:DD MREQ RD \| Memory read from 000 -> DD`
1188			`-----------------------------------------------------------+`
1189			`</PRE>`
1190			`<H3 id="8C">Opcode: DD 8C => ADC A,IXh*</H3>`
1191			`<PRE>`
1192			`-----------------------------------------------------------+`
1193			`#001H T1 AB:000 DB:-- M1 \|`
1194			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1195			`#003H T3 AB:000 DB:-- RFSH \|`
1196			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1197			`-----------------------------------------------------------+`
1198			`#005H T1 AB:001 DB:-- M1 \|`
1199			`#006H T2 AB:001 DB:8C M1 MREQ RD \| Opcode read from 001 -> 8C`
1200			`#007H T3 AB:001 DB:-- RFSH \|`
1201			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1202			`-----------------------------------------------------------+`
1203			`</PRE>`
1204			`<H3 id="8D">Opcode: DD 8D => ADC A,IXl*</H3>`
1205			`<PRE>`
1206			`-----------------------------------------------------------+`
1207			`#001H T1 AB:000 DB:-- M1 \|`
1208			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1209			`#003H T3 AB:000 DB:-- RFSH \|`
1210			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1211			`-----------------------------------------------------------+`
1212			`#005H T1 AB:001 DB:-- M1 \|`
1213			`#006H T2 AB:001 DB:8D M1 MREQ RD \| Opcode read from 001 -> 8D`
1214			`#007H T3 AB:001 DB:-- RFSH \|`
1215			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1216			`-----------------------------------------------------------+`
1217			`</PRE>`
1218			`<H3 id="8E">Opcode: DD 8E d => ADC A,(IX+d)</H3>`
1219			`<PRE>`
1220			`-----------------------------------------------------------+`
1221			`#001H T1 AB:000 DB:-- M1 \|`
1222			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1223			`#003H T3 AB:000 DB:-- RFSH \|`
1224			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1225			`-----------------------------------------------------------+`
1226			`#005H T1 AB:001 DB:-- M1 \|`
1227			`#006H T2 AB:001 DB:8E M1 MREQ RD \| Opcode read from 001 -> 8E`
1228			`#007H T3 AB:001 DB:-- RFSH \|`
1229			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1230			`#009H T5 AB:002 DB:-- \|`
1231			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
1232			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
1233			`#012H T8 AB:002 DB:-- \|`
1234			`#013H T9 AB:002 DB:-- \|`
1235			`#014H T10 AB:002 DB:-- \|`
1236			`#015H T11 AB:002 DB:-- \|`
1237			`#016H T12 AB:002 DB:-- \|`
1238			`#017H T13 AB:000 DB:-- \|`
1239			`#018H T14 AB:000 DB:DD MREQ RD \| Memory read from 000 -> DD`
1240			`#019H T15 AB:000 DB:DD MREQ RD \| Memory read from 000 -> DD`
1241			`-----------------------------------------------------------+`
1242			`</PRE>`
1243			`<H3 id="94">Opcode: DD 94 => SUB IXh*</H3>`
1244			`<PRE>`
1245			`-----------------------------------------------------------+`
1246			`#001H T1 AB:000 DB:-- M1 \|`
1247			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1248			`#003H T3 AB:000 DB:-- RFSH \|`
1249			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1250			`-----------------------------------------------------------+`
1251			`#005H T1 AB:001 DB:-- M1 \|`
1252			`#006H T2 AB:001 DB:94 M1 MREQ RD \| Opcode read from 001 -> 94`
1253			`#007H T3 AB:001 DB:-- RFSH \|`
1254			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1255			`-----------------------------------------------------------+`
1256			`</PRE>`
1257			`<H3 id="95">Opcode: DD 95 => SUB IXl*</H3>`
1258			`<PRE>`
1259			`-----------------------------------------------------------+`
1260			`#001H T1 AB:000 DB:-- M1 \|`
1261			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1262			`#003H T3 AB:000 DB:-- RFSH \|`
1263			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1264			`-----------------------------------------------------------+`
1265			`#005H T1 AB:001 DB:-- M1 \|`
1266			`#006H T2 AB:001 DB:95 M1 MREQ RD \| Opcode read from 001 -> 95`
1267			`#007H T3 AB:001 DB:-- RFSH \|`
1268			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1269			`-----------------------------------------------------------+`
1270			`</PRE>`
1271			`<H3 id="96">Opcode: DD 96 d => SUB (IX+d)</H3>`
1272			`<PRE>`
1273			`-----------------------------------------------------------+`
1274			`#001H T1 AB:000 DB:-- M1 \|`
1275			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1276			`#003H T3 AB:000 DB:-- RFSH \|`
1277			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1278			`-----------------------------------------------------------+`
1279			`#005H T1 AB:001 DB:-- M1 \|`
1280			`#006H T2 AB:001 DB:96 M1 MREQ RD \| Opcode read from 001 -> 96`
1281			`#007H T3 AB:001 DB:-- RFSH \|`
1282			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1283			`#009H T5 AB:002 DB:-- \|`
1284			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
1285			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
1286			`#012H T8 AB:002 DB:-- \|`
1287			`#013H T9 AB:002 DB:-- \|`
1288			`#014H T10 AB:002 DB:-- \|`
1289			`#015H T11 AB:002 DB:-- \|`
1290			`#016H T12 AB:002 DB:-- \|`
1291			`#017H T13 AB:000 DB:-- \|`
1292			`#018H T14 AB:000 DB:DD MREQ RD \| Memory read from 000 -> DD`
1293			`#019H T15 AB:000 DB:DD MREQ RD \| Memory read from 000 -> DD`
1294			`-----------------------------------------------------------+`
1295			`</PRE>`
1296			`<H3 id="9C">Opcode: DD 9C => SBC A,IXh*</H3>`
1297			`<PRE>`
1298			`-----------------------------------------------------------+`
1299			`#001H T1 AB:000 DB:-- M1 \|`
1300			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1301			`#003H T3 AB:000 DB:-- RFSH \|`
1302			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1303			`-----------------------------------------------------------+`
1304			`#005H T1 AB:001 DB:-- M1 \|`
1305			`#006H T2 AB:001 DB:9C M1 MREQ RD \| Opcode read from 001 -> 9C`
1306			`#007H T3 AB:001 DB:-- RFSH \|`
1307			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1308			`-----------------------------------------------------------+`
1309			`</PRE>`
1310			`<H3 id="9D">Opcode: DD 9D => SBC A,IXl*</H3>`
1311			`<PRE>`
1312			`-----------------------------------------------------------+`
1313			`#001H T1 AB:000 DB:-- M1 \|`
1314			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1315			`#003H T3 AB:000 DB:-- RFSH \|`
1316			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1317			`-----------------------------------------------------------+`
1318			`#005H T1 AB:001 DB:-- M1 \|`
1319			`#006H T2 AB:001 DB:9D M1 MREQ RD \| Opcode read from 001 -> 9D`
1320			`#007H T3 AB:001 DB:-- RFSH \|`
1321			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1322			`-----------------------------------------------------------+`
1323			`</PRE>`
1324			`<H3 id="9E">Opcode: DD 9E d => SBC A,(IX+d)</H3>`
1325			`<PRE>`
1326			`-----------------------------------------------------------+`
1327			`#001H T1 AB:000 DB:-- M1 \|`
1328			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1329			`#003H T3 AB:000 DB:-- RFSH \|`
1330			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1331			`-----------------------------------------------------------+`
1332			`#005H T1 AB:001 DB:-- M1 \|`
1333			`#006H T2 AB:001 DB:9E M1 MREQ RD \| Opcode read from 001 -> 9E`
1334			`#007H T3 AB:001 DB:-- RFSH \|`
1335			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1336			`#009H T5 AB:002 DB:-- \|`
1337			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
1338			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
1339			`#012H T8 AB:002 DB:-- \|`
1340			`#013H T9 AB:002 DB:-- \|`
1341			`#014H T10 AB:002 DB:-- \|`
1342			`#015H T11 AB:002 DB:-- \|`
1343			`#016H T12 AB:002 DB:-- \|`
1344			`#017H T13 AB:000 DB:-- \|`
1345			`#018H T14 AB:000 DB:DD MREQ RD \| Memory read from 000 -> DD`
1346			`#019H T15 AB:000 DB:DD MREQ RD \| Memory read from 000 -> DD`
1347			`-----------------------------------------------------------+`
1348			`</PRE>`
1349			`<H3 id="A4">Opcode: DD A4 => AND IXh*</H3>`
1350			`<PRE>`
1351			`-----------------------------------------------------------+`
1352			`#001H T1 AB:000 DB:-- M1 \|`
1353			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1354			`#003H T3 AB:000 DB:-- RFSH \|`
1355			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1356			`-----------------------------------------------------------+`
1357			`#005H T1 AB:001 DB:-- M1 \|`
1358			`#006H T2 AB:001 DB:A4 M1 MREQ RD \| Opcode read from 001 -> A4`
1359			`#007H T3 AB:001 DB:-- RFSH \|`
1360			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1361			`-----------------------------------------------------------+`
1362			`</PRE>`
1363			`<H3 id="A5">Opcode: DD A5 => AND IXl*</H3>`
1364			`<PRE>`
1365			`-----------------------------------------------------------+`
1366			`#001H T1 AB:000 DB:-- M1 \|`
1367			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1368			`#003H T3 AB:000 DB:-- RFSH \|`
1369			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1370			`-----------------------------------------------------------+`
1371			`#005H T1 AB:001 DB:-- M1 \|`
1372			`#006H T2 AB:001 DB:A5 M1 MREQ RD \| Opcode read from 001 -> A5`
1373			`#007H T3 AB:001 DB:-- RFSH \|`
1374			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1375			`-----------------------------------------------------------+`
1376			`</PRE>`
1377			`<H3 id="A6">Opcode: DD A6 d => AND (IX+d)</H3>`
1378			`<PRE>`
1379			`-----------------------------------------------------------+`
1380			`#001H T1 AB:000 DB:-- M1 \|`
1381			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1382			`#003H T3 AB:000 DB:-- RFSH \|`
1383			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1384			`-----------------------------------------------------------+`
1385			`#005H T1 AB:001 DB:-- M1 \|`
1386			`#006H T2 AB:001 DB:A6 M1 MREQ RD \| Opcode read from 001 -> A6`
1387			`#007H T3 AB:001 DB:-- RFSH \|`
1388			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1389			`#009H T5 AB:002 DB:-- \|`
1390			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
1391			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
1392			`#012H T8 AB:002 DB:-- \|`
1393			`#013H T9 AB:002 DB:-- \|`
1394			`#014H T10 AB:002 DB:-- \|`
1395			`#015H T11 AB:002 DB:-- \|`
1396			`#016H T12 AB:002 DB:-- \|`
1397			`#017H T13 AB:000 DB:-- \|`
1398			`#018H T14 AB:000 DB:DD MREQ RD \| Memory read from 000 -> DD`
1399			`#019H T15 AB:000 DB:DD MREQ RD \| Memory read from 000 -> DD`
1400			`-----------------------------------------------------------+`
1401			`</PRE>`
1402			`<H3 id="AC">Opcode: DD AC => XOR IXh*</H3>`
1403			`<PRE>`
1404			`-----------------------------------------------------------+`
1405			`#001H T1 AB:000 DB:-- M1 \|`
1406			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1407			`#003H T3 AB:000 DB:-- RFSH \|`
1408			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1409			`-----------------------------------------------------------+`
1410			`#005H T1 AB:001 DB:-- M1 \|`
1411			`#006H T2 AB:001 DB:AC M1 MREQ RD \| Opcode read from 001 -> AC`
1412			`#007H T3 AB:001 DB:-- RFSH \|`
1413			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1414			`-----------------------------------------------------------+`
1415			`</PRE>`
1416			`<H3 id="AD">Opcode: DD AD => XOR IXl*</H3>`
1417			`<PRE>`
1418			`-----------------------------------------------------------+`
1419			`#001H T1 AB:000 DB:-- M1 \|`
1420			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1421			`#003H T3 AB:000 DB:-- RFSH \|`
1422			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1423			`-----------------------------------------------------------+`
1424			`#005H T1 AB:001 DB:-- M1 \|`
1425			`#006H T2 AB:001 DB:AD M1 MREQ RD \| Opcode read from 001 -> AD`
1426			`#007H T3 AB:001 DB:-- RFSH \|`
1427			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1428			`-----------------------------------------------------------+`
1429			`</PRE>`
1430			`<H3 id="AE">Opcode: DD AE d => XOR (IX+d)</H3>`
1431			`<PRE>`
1432			`-----------------------------------------------------------+`
1433			`#001H T1 AB:000 DB:-- M1 \|`
1434			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1435			`#003H T3 AB:000 DB:-- RFSH \|`
1436			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1437			`-----------------------------------------------------------+`
1438			`#005H T1 AB:001 DB:-- M1 \|`
1439			`#006H T2 AB:001 DB:AE M1 MREQ RD \| Opcode read from 001 -> AE`
1440			`#007H T3 AB:001 DB:-- RFSH \|`
1441			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1442			`#009H T5 AB:002 DB:-- \|`
1443			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
1444			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
1445			`#012H T8 AB:002 DB:-- \|`
1446			`#013H T9 AB:002 DB:-- \|`
1447			`#014H T10 AB:002 DB:-- \|`
1448			`#015H T11 AB:002 DB:-- \|`
1449			`#016H T12 AB:002 DB:-- \|`
1450			`#017H T13 AB:000 DB:-- \|`
1451			`#018H T14 AB:000 DB:DD MREQ RD \| Memory read from 000 -> DD`
1452			`#019H T15 AB:000 DB:DD MREQ RD \| Memory read from 000 -> DD`
1453			`-----------------------------------------------------------+`
1454			`</PRE>`
1455			`<H3 id="B4">Opcode: DD B4 => OR IXh*</H3>`
1456			`<PRE>`
1457			`-----------------------------------------------------------+`
1458			`#001H T1 AB:000 DB:-- M1 \|`
1459			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1460			`#003H T3 AB:000 DB:-- RFSH \|`
1461			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1462			`-----------------------------------------------------------+`
1463			`#005H T1 AB:001 DB:-- M1 \|`
1464			`#006H T2 AB:001 DB:B4 M1 MREQ RD \| Opcode read from 001 -> B4`
1465			`#007H T3 AB:001 DB:-- RFSH \|`
1466			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1467			`-----------------------------------------------------------+`
1468			`</PRE>`
1469			`<H3 id="B5">Opcode: DD B5 => OR IXl*</H3>`
1470			`<PRE>`
1471			`-----------------------------------------------------------+`
1472			`#001H T1 AB:000 DB:-- M1 \|`
1473			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1474			`#003H T3 AB:000 DB:-- RFSH \|`
1475			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1476			`-----------------------------------------------------------+`
1477			`#005H T1 AB:001 DB:-- M1 \|`
1478			`#006H T2 AB:001 DB:B5 M1 MREQ RD \| Opcode read from 001 -> B5`
1479			`#007H T3 AB:001 DB:-- RFSH \|`
1480			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1481			`-----------------------------------------------------------+`
1482			`</PRE>`
1483			`<H3 id="B6">Opcode: DD B6 d => OR (IX+d)</H3>`
1484			`<PRE>`
1485			`-----------------------------------------------------------+`
1486			`#001H T1 AB:000 DB:-- M1 \|`
1487			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1488			`#003H T3 AB:000 DB:-- RFSH \|`
1489			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1490			`-----------------------------------------------------------+`
1491			`#005H T1 AB:001 DB:-- M1 \|`
1492			`#006H T2 AB:001 DB:B6 M1 MREQ RD \| Opcode read from 001 -> B6`
1493			`#007H T3 AB:001 DB:-- RFSH \|`
1494			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1495			`#009H T5 AB:002 DB:-- \|`
1496			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
1497			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
1498			`#012H T8 AB:002 DB:-- \|`
1499			`#013H T9 AB:002 DB:-- \|`
1500			`#014H T10 AB:002 DB:-- \|`
1501			`#015H T11 AB:002 DB:-- \|`
1502			`#016H T12 AB:002 DB:-- \|`
1503			`#017H T13 AB:000 DB:-- \|`
1504			`#018H T14 AB:000 DB:DD MREQ RD \| Memory read from 000 -> DD`
1505			`#019H T15 AB:000 DB:DD MREQ RD \| Memory read from 000 -> DD`
1506			`-----------------------------------------------------------+`
1507			`</PRE>`
1508			`<H3 id="BC">Opcode: DD BC => CP IXh*</H3>`
1509			`<PRE>`
1510			`-----------------------------------------------------------+`
1511			`#001H T1 AB:000 DB:-- M1 \|`
1512			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1513			`#003H T3 AB:000 DB:-- RFSH \|`
1514			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1515			`-----------------------------------------------------------+`
1516			`#005H T1 AB:001 DB:-- M1 \|`
1517			`#006H T2 AB:001 DB:BC M1 MREQ RD \| Opcode read from 001 -> BC`
1518			`#007H T3 AB:001 DB:-- RFSH \|`
1519			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1520			`-----------------------------------------------------------+`
1521			`</PRE>`
1522			`<H3 id="BD">Opcode: DD BD => CP IXl*</H3>`
1523			`<PRE>`
1524			`-----------------------------------------------------------+`
1525			`#001H T1 AB:000 DB:-- M1 \|`
1526			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1527			`#003H T3 AB:000 DB:-- RFSH \|`
1528			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1529			`-----------------------------------------------------------+`
1530			`#005H T1 AB:001 DB:-- M1 \|`
1531			`#006H T2 AB:001 DB:BD M1 MREQ RD \| Opcode read from 001 -> BD`
1532			`#007H T3 AB:001 DB:-- RFSH \|`
1533			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1534			`-----------------------------------------------------------+`
1535			`</PRE>`
1536			`<H3 id="BE">Opcode: DD BE d => CP (IX+d)</H3>`
1537			`<PRE>`
1538			`-----------------------------------------------------------+`
1539			`#001H T1 AB:000 DB:-- M1 \|`
1540			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1541			`#003H T3 AB:000 DB:-- RFSH \|`
1542			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1543			`-----------------------------------------------------------+`
1544			`#005H T1 AB:001 DB:-- M1 \|`
1545			`#006H T2 AB:001 DB:BE M1 MREQ RD \| Opcode read from 001 -> BE`
1546			`#007H T3 AB:001 DB:-- RFSH \|`
1547			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1548			`#009H T5 AB:002 DB:-- \|`
1549			`#010H T6 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
1550			`#011H T7 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
1551			`#012H T8 AB:002 DB:-- \|`
1552			`#013H T9 AB:002 DB:-- \|`
1553			`#014H T10 AB:002 DB:-- \|`
1554			`#015H T11 AB:002 DB:-- \|`
1555			`#016H T12 AB:002 DB:-- \|`
1556			`#017H T13 AB:000 DB:-- \|`
1557			`#018H T14 AB:000 DB:DD MREQ RD \| Memory read from 000 -> DD`
1558			`#019H T15 AB:000 DB:DD MREQ RD \| Memory read from 000 -> DD`
1559			`-----------------------------------------------------------+`
1560			`</PRE>`
1561			`<H3 id="E1">Opcode: DD E1 => POP IX</H3>`
1562			`<PRE>`
1563			`-----------------------------------------------------------+`
1564			`#001H T1 AB:000 DB:-- M1 \|`
1565			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1566			`#003H T3 AB:000 DB:-- RFSH \|`
1567			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1568			`-----------------------------------------------------------+`
1569			`#005H T1 AB:001 DB:-- M1 \|`
1570			`#006H T2 AB:001 DB:E1 M1 MREQ RD \| Opcode read from 001 -> E1`
1571			`#007H T3 AB:001 DB:-- RFSH \|`
1572			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1573			`#009H T5 AB:0FF DB:-- \|`
1574			`#010H T6 AB:0FF DB:00 MREQ RD \| Memory read from 0FF -> 00`
1575			`#011H T7 AB:0FF DB:00 MREQ RD \| Memory read from 0FF -> 00`
1576			`#012H T8 AB:000 DB:-- \|`
1577			`#013H T9 AB:000 DB:DD MREQ RD \| Memory read from 000 -> DD`
1578			`#014H T10 AB:000 DB:DD MREQ RD \| Memory read from 000 -> DD`
1579			`-----------------------------------------------------------+`
1580			`</PRE>`
1581			`<H3 id="E3">Opcode: DD E3 => EX (SP),IX</H3>`
1582			`<PRE>`
1583			`-----------------------------------------------------------+`
1584			`#001H T1 AB:000 DB:-- M1 \|`
1585			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1586			`#003H T3 AB:000 DB:-- RFSH \|`
1587			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1588			`-----------------------------------------------------------+`
1589			`#005H T1 AB:001 DB:-- M1 \|`
1590			`#006H T2 AB:001 DB:E3 M1 MREQ RD \| Opcode read from 001 -> E3`
1591			`#007H T3 AB:001 DB:-- RFSH \|`
1592			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1593			`#009H T5 AB:001 DB:-- \|`
1594			`#010H T6 AB:001 DB:E3 MREQ RD \| Memory read from 001 -> E3`
1595			`#011H T7 AB:001 DB:E3 MREQ RD \| Memory read from 001 -> E3`
1596			`#012H T8 AB:002 DB:-- \|`
1597			`#013H T9 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
1598			`#014H T10 AB:002 DB:01 MREQ RD \| Memory read from 002 -> 01`
1599			`#015H T11 AB:002 DB:-- \|`
1600			`#016H T12 AB:002 DB:-- \|`
1601			`#017H T13 AB:002 DB:DD MREQ \|`
1602			`#018H T14 AB:002 DB:DD MREQ WR \| Memory write to 002 <- DD`
1603			`#019H T15 AB:001 DB:-- \|`
1604			`#020H T16 AB:001 DB:00 MREQ \|`
1605			`#021H T17 AB:001 DB:00 MREQ WR \| Memory write to 001 <- 00`
1606			`#022H T18 AB:001 DB:00 \|`
1607			`#023H T19 AB:001 DB:00 \|`
1608			`-----------------------------------------------------------+`
1609			`</PRE>`
1610			`<H3 id="E5">Opcode: DD E5 => PUSH IX</H3>`
1611			`<PRE>`
1612			`-----------------------------------------------------------+`
1613			`#001H T1 AB:000 DB:-- M1 \|`
1614			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1615			`#003H T3 AB:000 DB:-- RFSH \|`
1616			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1617			`-----------------------------------------------------------+`
1618			`#005H T1 AB:001 DB:-- M1 \|`
1619			`#006H T2 AB:001 DB:E5 M1 MREQ RD \| Opcode read from 001 -> E5`
1620			`#007H T3 AB:001 DB:-- RFSH \|`
1621			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1622			`#009H T5 AB:001 DB:-- \|`
1623			`#010H T6 AB:000 DB:-- \|`
1624			`#011H T7 AB:000 DB:01 MREQ \|`
1625			`#012H T8 AB:000 DB:01 MREQ WR \| Memory write to 000 <- 01`
1626			`#013H T9 AB:0FF DB:-- \|`
1627			`#014H T10 AB:0FF DB:E3 MREQ \|`
1628			`#015H T11 AB:0FF DB:E3 MREQ WR \| Memory write to 0FF <- E3`
1629			`-----------------------------------------------------------+`
1630			`</PRE>`
1631			`<H3 id="E9">Opcode: DD E9 => JP (IX)</H3>`
1632			`<PRE>`
1633			`-----------------------------------------------------------+`
1634			`#001H T1 AB:000 DB:-- M1 \|`
1635			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1636			`#003H T3 AB:000 DB:-- RFSH \|`
1637			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1638			`-----------------------------------------------------------+`
1639			`#005H T1 AB:001 DB:-- M1 \|`
1640			`#006H T2 AB:001 DB:E9 M1 MREQ RD \| Opcode read from 001 -> E9`
1641			`#007H T3 AB:001 DB:-- RFSH \|`
1642			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1643			`-----------------------------------------------------------+`
1644			`</PRE>`
1645			`<H3 id="F9">Opcode: DD F9 => LD SP,IX</H3>`
1646			`<PRE>`
1647			`-----------------------------------------------------------+`
1648			`#001H T1 AB:000 DB:-- M1 \|`
1649			`#002H T2 AB:000 DB:DD M1 MREQ RD \| Opcode read from 000 -> DD`
1650			`#003H T3 AB:000 DB:-- RFSH \|`
1651			`#004H T4 AB:000 DB:-- RFSH MREQ \| Refresh address 000`
1652			`-----------------------------------------------------------+`
1653			`#005H T1 AB:001 DB:-- M1 \|`
1654			`#006H T2 AB:001 DB:F9 M1 MREQ RD \| Opcode read from 001 -> F9`
1655			`#007H T3 AB:001 DB:-- RFSH \|`
1656			`#008H T4 AB:001 DB:-- RFSH MREQ \| Refresh address 001`
1657			`#009H T5 AB:001 DB:-- \|`
1658			`#010H T6 AB:001 DB:-- \|`
1659			`-----------------------------------------------------------+`
1660			`</PRE>`
1661			`</BODY></HTML>`

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