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[/] [a429_transmitter_receiver/] [trunk/] [rtl/] [a429_rx_iface.v] - Blame information for rev 2

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////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2019 Himar Alonso
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this hardware, software, and associated documentation files
// (the "Product"), to deal in the Product without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Product, and to permit
// persons to whom the Product is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Product.
//
// THE PRODUCT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE PRODUCT OR THE USE OR OTHER DEALINGS IN THE
// PRODUCT. 
//
////////////////////////////////////////////////////////////////////////////////
// A429 Receiving Interface
// 
// Designed by Himar Alonso (himar@opencores.org)
// Date: 15/08/2019
////////////////////////////////////////////////////////////////////////////////
 
module a429_rx_iface
(
        input             clk2M,
        input             reset,
        input             enable,
        input       [1:0] speed,
        input             a429_in_a,
        input             a429_in_b,
        input             parcheck,
        output reg [32:1] data,
        output reg        wr_en
);
 
        ////////////////////////////////////////
        // Constants for the sampling counter //
        ////////////////////////////////////////
        // Counter values for first/other sampling intervals
        // 2.5us/10us for 100Kbps mode,
        // 20us/80us for 12,5Kbps mode.
        wire [8:0] first_sc_value = (speed[0]) ? 9'd4  : 9'd39;
        wire [8:0] other_sc_value = (speed[0]) ? 9'd19 : 9'd159;
 
        // Counter values for gap search
        // 40us for 100Kbps mode, setting it to 30us
        // 320us for 12,5Kbps mode, setting it to 240us.
        wire [8:0] gap_sc_value = (speed[0]) ? 9'd59 : 9'd479;
 
        ///////////////////////////////////////////////////////
        // Register 'aorb' previous value for edge detection //
        ///////////////////////////////////////////////////////
        wire aandb = a429_in_a & a429_in_b;
        wire aorb = a429_in_a | a429_in_b;
        reg  aorb_prev;
 
        always @(posedge clk2M or posedge reset)
                if (reset)
                        aorb_prev <= 1'b0;
                else
                        aorb_prev <= aorb;
 
        ///////////////////////////////////////////////
        // RX state machine parameters and registers //
        ///////////////////////////////////////////////
        localparam IDLE       = 2'b00;
        localparam RECEIVING  = 2'b01;
        localparam WAITFORGAP = 2'b10;
 
        reg   [1:0] state;
        reg         parity;
        reg  [32:1] shift_reg;
        reg   [4:0] shift_counter;
        reg   [8:0] sampling_counter;
 
        /////////////////////////////////////
        // RX state machine implementation //
        /////////////////////////////////////
        always @(posedge clk2M or posedge reset)
                if (reset) begin
                        state <= WAITFORGAP;
                        sampling_counter <= gap_sc_value;
                        shift_counter <= 5'b0;
                        data <= 32'b0;
                        shift_reg <= 32'b0;
                        wr_en <= 1'b0;
                end else begin
                        case (state)
                                IDLE:
                                        //
                                        // Wait for 'aorb' rising edge
                                        //
                                        begin
                                                parity <= 1'b0;
                                                sampling_counter <= first_sc_value;
                                                shift_counter <= 5'd31;
                                                if (aorb & !aorb_prev)
                                                        state <= RECEIVING;
                                        end
                                RECEIVING:
                                        //
                                        // Logical shift right until shift_counter = 0
                                        //
                                        if (~|sampling_counter)
                                                if ((aandb == 1'b1) || (aorb == 1'b0)) begin // Bus error
                                                        sampling_counter <= gap_sc_value;
                                                        state <= WAITFORGAP;
                                                end else if (~|shift_counter) begin // Complete word received
                                                        data <= {a429_in_a, shift_reg[32:10],
                                                                shift_reg[2], shift_reg[3], shift_reg[4], shift_reg[5],
                                                                shift_reg[6], shift_reg[7], shift_reg[8], shift_reg[9]};
                                                        if ((parity == a429_in_b) || !parcheck) // Odd parity ok, or no parity check
                                                                wr_en <= 1'b1;
                                                        sampling_counter <= gap_sc_value;
                                                        state <= WAITFORGAP;
                                                end else begin // bit received
                                                        shift_reg <= {a429_in_a, shift_reg[32:2]};
                                                        parity <= parity ^ a429_in_a;
                                                        shift_counter <= shift_counter - 5'b1;
                                                        sampling_counter <= other_sc_value;
                                                end
                                        else
                                                sampling_counter <= sampling_counter - 9'b1;
                                WAITFORGAP:
                                        //
                                        // Wait until a new gap is found
                                        //
                                        begin
                                                wr_en <= 1'b0;
                                                if (~|sampling_counter)
                                                        state <= IDLE;
                                                else if (aorb == 1'b1)
                                                        sampling_counter <= gap_sc_value;
                                                else
                                                        sampling_counter <= sampling_counter - 9'b1;
                                        end
                                default: // This should never happen
                                        begin
                                                wr_en <= 1'b0;
                                                sampling_counter <= gap_sc_value;
                                                state <= WAITFORGAP;
                                        end
                        endcase
                end
 
endmodule

Line No.	Rev	Author	Line
1	2	himar
2			`////////////////////////////////////////////////////////////////////////////////`
3			`//`
4			`// Copyright (c) 2019 Himar Alonso`
5			`//`
6			`// Permission is hereby granted, free of charge, to any person obtaining a copy`
7			`// of this hardware, software, and associated documentation files`
8			`// (the "Product"), to deal in the Product without restriction, including`
9			`// without limitation the rights to use, copy, modify, merge, publish,`
10			`// distribute, sublicense, and/or sell copies of the Product, and to permit`
11			`// persons to whom the Product is furnished to do so, subject to the following`
12			`// conditions:`
13			`//`
14			`// The above copyright notice and this permission notice shall be included in`
15			`// all copies or substantial portions of the Product.`
16			`//`
17			`// THE PRODUCT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR`
18			`// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,`
19			`// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE`
20			`// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER`
21			`// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,`
22			`// OUT OF OR IN CONNECTION WITH THE PRODUCT OR THE USE OR OTHER DEALINGS IN THE`
23			`// PRODUCT.`
24			`//`
25			`////////////////////////////////////////////////////////////////////////////////`
26			`// A429 Receiving Interface`
27			`//`
28			`// Designed by Himar Alonso (himar@opencores.org)`
29			`// Date: 15/08/2019`
30			`////////////////////////////////////////////////////////////////////////////////`
31
32			`module a429_rx_iface`
33			`(`
34			`input clk2M,`
35			`input reset,`
36			`input enable,`
37			`input [1:0] speed,`
38			`input a429_in_a,`
39			`input a429_in_b,`
40			`input parcheck,`
41			`output reg [32:1] data,`
42			`output reg wr_en`
43			`);`
44
45			`////////////////////////////////////////`
46			`// Constants for the sampling counter //`
47			`////////////////////////////////////////`
48			`// Counter values for first/other sampling intervals`
49			`// 2.5us/10us for 100Kbps mode,`
50			`// 20us/80us for 12,5Kbps mode.`
51			`wire [8:0] first_sc_value = (speed[0]) ? 9'd4 : 9'd39;`
52			`wire [8:0] other_sc_value = (speed[0]) ? 9'd19 : 9'd159;`
53
54			`// Counter values for gap search`
55			`// 40us for 100Kbps mode, setting it to 30us`
56			`// 320us for 12,5Kbps mode, setting it to 240us.`
57			`wire [8:0] gap_sc_value = (speed[0]) ? 9'd59 : 9'd479;`
58
59			`///////////////////////////////////////////////////////`
60			`// Register 'aorb' previous value for edge detection //`
61			`///////////////////////////////////////////////////////`
62			`wire aandb = a429_in_a & a429_in_b;`
63			`wire aorb = a429_in_a \| a429_in_b;`
64			`reg aorb_prev;`
65
66			`always @(posedge clk2M or posedge reset)`
67			`if (reset)`
68			`aorb_prev <= 1'b0;`
69			`else`
70			`aorb_prev <= aorb;`
71
72			`///////////////////////////////////////////////`
73			`// RX state machine parameters and registers //`
74			`///////////////////////////////////////////////`
75			`localparam IDLE = 2'b00;`
76			`localparam RECEIVING = 2'b01;`
77			`localparam WAITFORGAP = 2'b10;`
78
79			`reg [1:0] state;`
80			`reg parity;`
81			`reg [32:1] shift_reg;`
82			`reg [4:0] shift_counter;`
83			`reg [8:0] sampling_counter;`
84
85			`/////////////////////////////////////`
86			`// RX state machine implementation //`
87			`/////////////////////////////////////`
88			`always @(posedge clk2M or posedge reset)`
89			`if (reset) begin`
90			`state <= WAITFORGAP;`
91			`sampling_counter <= gap_sc_value;`
92			`shift_counter <= 5'b0;`
93			`data <= 32'b0;`
94			`shift_reg <= 32'b0;`
95			`wr_en <= 1'b0;`
96			`end else begin`
97			`case (state)`
98			`IDLE:`
99			`//`
100			`// Wait for 'aorb' rising edge`
101			`//`
102			`begin`
103			`parity <= 1'b0;`
104			`sampling_counter <= first_sc_value;`
105			`shift_counter <= 5'd31;`
106			`if (aorb & !aorb_prev)`
107			`state <= RECEIVING;`
108			`end`
109			`RECEIVING:`
110			`//`
111			`// Logical shift right until shift_counter = 0`
112			`//`
113			`if (~\|sampling_counter)`
114			`if ((aandb == 1'b1) \|\| (aorb == 1'b0)) begin // Bus error`
115			`sampling_counter <= gap_sc_value;`
116			`state <= WAITFORGAP;`
117			`end else if (~\|shift_counter) begin // Complete word received`
118			`data <= {a429_in_a, shift_reg[32:10],`
119			`shift_reg[2], shift_reg[3], shift_reg[4], shift_reg[5],`
120			`shift_reg[6], shift_reg[7], shift_reg[8], shift_reg[9]};`
121			`if ((parity == a429_in_b) \|\| !parcheck) // Odd parity ok, or no parity check`
122			`wr_en <= 1'b1;`
123			`sampling_counter <= gap_sc_value;`
124			`state <= WAITFORGAP;`
125			`end else begin // bit received`
126			`shift_reg <= {a429_in_a, shift_reg[32:2]};`
127			`parity <= parity ^ a429_in_a;`
128			`shift_counter <= shift_counter - 5'b1;`
129			`sampling_counter <= other_sc_value;`
130			`end`
131			`else`
132			`sampling_counter <= sampling_counter - 9'b1;`
133			`WAITFORGAP:`
134			`//`
135			`// Wait until a new gap is found`
136			`//`
137			`begin`
138			`wr_en <= 1'b0;`
139			`if (~\|sampling_counter)`
140			`state <= IDLE;`
141			`else if (aorb == 1'b1)`
142			`sampling_counter <= gap_sc_value;`
143			`else`
144			`sampling_counter <= sampling_counter - 9'b1;`
145			`end`
146			`default: // This should never happen`
147			`begin`
148			`wr_en <= 1'b0;`
149			`sampling_counter <= gap_sc_value;`
150			`state <= WAITFORGAP;`
151			`end`
152			`endcase`
153			`end`
154
155			`endmodule`

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[/] [a429_transmitter_receiver/] [trunk/] [rtl/] [a429_rx_iface.v] - Blame information for rev 2